static uint32_t READ_CAUSE(void)
{
mips_get_cause( _ivcause );
_ivcause &= SR_IMASK; /* mask off everything other than the interrupt bits */
return ((_ivcause & (_ivsr & SR_IMASK)) >> CAUSE_IPSHIFT);
}
void mips_default_isr( int vector )
{
unsigned int sr;
unsigned int cause;
mips_get_sr( sr );
mips_get_cause( cause );
printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n",
vector, cause, sr );
rtems_fatal_error_occurred(1);
}
int assertSoftwareInterrupt( uint32_t n )
{
if( n<2 )
{
uint32_t c;
mips_get_cause(c);
c = ((n+1) << CAUSE_IPSHIFT);
mips_set_cause(c);
return n;
}
else return -1;
}
void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
{
unsigned int sr;
unsigned int cause;
unsigned int pending;
mips_get_sr( sr );
mips_get_cause( cause );
pending = (cause & sr & 0x700) >> CAUSE_IPSHIFT;
if ( pending & 0x4 ) { /* (IP[2] == 1) ==> IP[3-7] are valid */
unsigned int v = (cause >> (CAUSE_IPSHIFT + 3)) & 0x1f;
bsp_interrupt_handler_dispatch( MIPS_INTERRUPT_BASE + v );
}
int mips_default_isr( int vector )
{
unsigned int sr, sr2;
unsigned int cause;
mips_get_sr( sr );
mips_get_cause( cause );
sr2 = sr & ~0xffff;
mips_set_sr(sr2);
printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n", vector, cause, sr );
rtems_fatal_error_occurred(1);
return 0;
}
void bsp_interrupt_handler_default(rtems_vector_number vector)
{
uint32_t sr;
uint32_t cause;
mips_get_sr( sr );
mips_get_cause( cause );
printk( "Unhandled exception %d\n", vector );
printk( "sr: 0x%08x cause: 0x%08x --> %s\n", sr, cause,
cause_strings[(cause >> 2) &0x1f] );
#if 0
mips_dump_exception_frame( frame );
#endif
rtems_fatal_error_occurred(1);
}
void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
{
unsigned int sr;
unsigned int cause;
unsigned int i;
unsigned int mask;
mips_get_sr( sr );
mips_get_cause( cause );
cause &= (sr & SR_IMASK);
cause >>= CAUSE_IPSHIFT;
for ( i=1, mask=0x80 ; i<=8 ; i++, mask >>= 1 ) {
if ( cause & mask )
CALL_ISR( MIPS_INTERRUPT_BASE + 8 - i, frame );
}
}
void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
{
unsigned int sr;
unsigned int cause;
mips_get_sr( sr );
mips_get_cause( cause );
cause &= (sr & SR_IMASK);
cause >>= CAUSE_IPSHIFT;
if ( cause & 0x80 ) /* IP[5] ==> INT0 */
bsp_interrupt_handler_dispatch( TX3904_IRQ_INT0 );
if ( cause & 0x40 ) { /* (IP[4] == 1) ==> IP[0-3] are valid */
unsigned int v = (cause >> 2) & 0x0f;
bsp_interrupt_handler_dispatch( MIPS_INTERRUPT_BASE + v );
}
void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
{
unsigned int sr;
unsigned int cause;
mips_get_sr( sr );
mips_get_cause( cause );
cause &= (sr & SR_IMASK);
cause >>= CAUSE_IPSHIFT;
if ( cause & 0xfc ) {
uint32_t id = mips_cpu_id();
while (1) {
uint32_t s = SOCLIB_XICU_READ( SOCLIB_XICU_BASE, XICU_PRIO, id );
if (XICU_PRIO_HAS_PTI(s)) {
mips_irq_process(XICU_PRIO_PTI(s), frame);
continue;
}
if (XICU_PRIO_HAS_HWI(s)) {
mips_irq_process(XICU_PRIO_HWI(s), frame);
continue;
}
if (XICU_PRIO_HAS_WTI(s)) {
mips_irq_process(XICU_PRIO_WTI(s), frame);
continue;
}
break;
}
}
}