static void __init
lopec_init_IRQ(void)
{
int i;
/*
* Provide the open_pic code with the correct table of interrupts.
*/
OpenPIC_InitSenses = lopec_openpic_initsenses;
OpenPIC_NumInitSenses = sizeof(lopec_openpic_initsenses);
mpc10x_set_openpic();
/* We have a cascade on OpenPIC IRQ 0, Linux IRQ 16 */
openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade",
&i8259_irq);
/* Map i8259 interrupts */
for(i = 0; i < NUM_8259_INTERRUPTS; i++)
irq_desc[i].handler = &i8259_pic;
/*
* The EPIC allows for a read in the range of 0xFEF00000 ->
* 0xFEFFFFFF to generate a PCI interrupt-acknowledge transaction.
*/
i8259_init(0xfef00000);
}
static void __init
powerpmc250_init_IRQ(void)
{
OpenPIC_InitSenses = powerpmc250_openpic_initsenses;
OpenPIC_NumInitSenses = sizeof(powerpmc250_openpic_initsenses);
mpc10x_set_openpic();
}
/*
* Interrupt setup and service. Interrrupts on the Sandpoint come
* from the four PCI slots plus the 8259 in the Winbond Super I/O (SIO).
* The 8259 is cascaded from EPIC IRQ0, IRQ1-4 map to PCI slots 1-4,
* IDE is on EPIC 7 and 8.
*/
static void __init
sandpoint_init_IRQ(void)
{
int i;
OpenPIC_InitSenses = sandpoint_openpic_initsenses;
OpenPIC_NumInitSenses = sizeof(sandpoint_openpic_initsenses);
mpc10x_set_openpic();
openpic_hookup_cascade(sandpoint_is_x2 ? 17 : NUM_8259_INTERRUPTS, "82c59 cascade",
i8259_irq);
/*
* The EPIC allows for a read in the range of 0xFEF00000 ->
* 0xFEFFFFFF to generate a PCI interrupt-acknowledge transaction.
*/
i8259_init(0xfef00000, 0);
}
