static int mpi_init(void)
{
unsigned long data;
unsigned int chipid;
unsigned int chiprev;
unsigned int sdramsize;
chipid = (PERF->RevID & 0xFFFF0000) >> 16;
chiprev = (PERF->RevID & 0xFF);
sdramsize = getMemorySize();
#if defined(CONFIG_BCM96348)
/*
* Init the pci interface
*/
data = GPIO->GPIOMode; // GPIO mode register
data |= GROUP2_PCI | GROUP1_MII_PCCARD; // PCI internal arbiter + Cardbus
GPIO->GPIOMode = data; // PCI internal arbiter
#endif
/*
* CardBus support is defaulted to Slot 0
* because there is no external IDSEL for CardBus. To disable
* the CardBus and allow a standard PCI card in Slot 0
* set the cbus_idsel field to 0x1f.
*/
/*
uData = mpi->pcmcia_cntl1;
uData |= CARDBUS_IDSEL;
mpi->pcmcia_cntl1 = uData;
*/
// UBUS to PCI address range
// Memory Window 1. Used for devices in slot 0. Potentially can be CardBus
mpi->l2pmrange1 = ~(BCM_PCI_MEM_SIZE_16MB-1);
// UBUS to PCI Memory base address. This is akin to the ChipSelect base
// register.
mpi->l2pmbase1 = BCM_CB_MEM_BASE & BCM_PCI_ADDR_MASK;
// UBUS to PCI Remap Address. Replaces the masked address bits in the
// range register with this setting.
// Also, enable direct I/O and direct Memory accesses
mpi->l2pmremap1 = (BCM_PCI_MEM_BASE | MEM_WINDOW_EN);
// Memory Window 2. Used for devices in other slots
mpi->l2pmrange2 = ~(BCM_PCI_MEM_SIZE_16MB-1);
// UBUS to PCI Memory base address.
mpi->l2pmbase2 = BCM_PCI_MEM_BASE & BCM_PCI_ADDR_MASK;
// UBUS to PCI Remap Address
mpi->l2pmremap2 = (BCM_PCI_MEM_BASE | MEM_WINDOW_EN);
// Setup PCI I/O Window range. Give 64K to PCI I/O
mpi->l2piorange = ~(BCM_PCI_IO_SIZE_64KB-1);
// UBUS to PCI I/O base address
mpi->l2piobase = BCM_PCI_IO_BASE & BCM_PCI_ADDR_MASK;
// UBUS to PCI I/O Window remap
mpi->l2pioremap = (BCM_PCI_IO_BASE | MEM_WINDOW_EN);
// enable PCI related GPIO pins and data swap between system and PCI bus
mpi->locbuscntrl = (EN_PCI_GPIO | DIR_U2P_NOSWAP);
/* Enable BusMaster and Memory access mode */
data = mpi_GetLocalPciConfigReg(PCI_COMMAND);
data |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
mpi_SetLocalPciConfigReg(PCI_COMMAND, data);
/* Configure two 16 MByte PCI to System memory regions. */
/* These memory regions are used when PCI device is a bus master */
/* Accesses to the SDRAM from PCI bus will be "byte swapped" for this region */
mpi_SetLocalPciConfigReg(PCI_BASE_ADDRESS_3, BCM_HOST_MEM_SPACE1);
#if defined(CONFIG_BCM96348)
mpi->sp0remap = 0x0;
#else
mpi->sp0remap = MEM_WINDOW_EN;
#endif
/* Accesses to the SDRAM from PCI bus will be "byte swapped" for this region */
mpi_SetLocalPciConfigReg(PCI_BASE_ADDRESS_4, BCM_HOST_MEM_SPACE2);
#if defined(CONFIG_BCM96348)
mpi->sp1remap = 0x0;
#else
mpi->sp1remap = MEM_WINDOW_EN;
#endif
mpi->pcimodesel |= 0x40;
if (!((chipid == 0x6348) && ((chiprev & 0xF0) == 0xa0))) {
mpi->sp0range = ~(sdramsize-1);
mpi->sp1range = ~(sdramsize-1);
}
/*
* Change PCI Cfg Reg. offset 0x40 to PCI memory read retry count infinity
* by set 0 in bit 8~15. This resolve read Bcm4306 srom return 0xffff in
* first read.
*/
data = mpi_GetLocalPciConfigReg(BRCM_PCI_CONFIG_TIMER);
data &= ~BRCM_PCI_CONFIG_TIMER_RETRY_MASK;
data |= 0x00000080;
mpi_SetLocalPciConfigReg(BRCM_PCI_CONFIG_TIMER, data);
/* enable pci interrupt */
mpi->locintstat |= (EXT_PCI_INT << 16);
mpi_DetectPcCard();
ioport_resource.start = BCM_PCI_IO_BASE;
ioport_resource.end = BCM_PCI_IO_BASE + BCM_PCI_IO_SIZE_64KB;
#if defined(CONFIG_USB)
#if defined(CONFIG_BCM96348)
PERF->blkEnables |= USBH_CLK_EN;
mdelay(100);
*USBH = USBH_BYTE_SWAP;
#endif
#if defined(CONFIG_BCM96358)
USBH->SwapControl = EHCI_ENDIAN_SWAP | OHCI_ENDIAN_SWAP;
USBH->TestPortControl = 0x001c0020;
#endif
#endif
return 0;
}
static int __init bcm6358_hw_init(void)
{
#if defined(CONFIG_PCI)
unsigned long data;
#endif
unsigned short GPIOOverlays;
/* Enable SPI interface */
PERF->blkEnables |= SPI_CLK_EN;
GPIO->GPIOMode = 0;
/* Enable Serial LED Interface */
//dare sunmin disable SERIAL LED OVERLAY
//GPIO->GPIOMode |= GPIO_MODE_SERIAL_LED_OVERLAY;
//GPIO->GPIOMode |= GPIO_MODE_LED_OVERLAY;
GPIO->GPIODir |= 0x00c0;
if( BpGetGPIOverlays(&GPIOOverlays) == BP_SUCCESS ) {
if (GPIOOverlays & BP_LED) {
/* Enable LED Outputs */
GPIO->GPIOMode |= GPIO_MODE_LED_OVERLAY;
GPIO->GPIODir |= 0x000f;
}
if (GPIOOverlays & BP_UTOPIA) {
/* Enable UTOPIA interface */
GPIO->GPIOMode |= GPIO_MODE_UTOPIA_OVERLAY ;
PERF->blkEnables |= SAR_CLK_EN;
}
if (GPIOOverlays & BP_UART1) {
/* Enable secondary UART interface */
GPIO->GPIOMode |= GPIO_MODE_UART1_OVERLAY;
GPIO->GPIODir |= 0x20000000;
}
if (GPIOOverlays & BP_SPI_EXT_CS) {
/* Enable Overlay for SPI SS Pins */
GPIO->GPIOMode |= GPIO_MODE_SPI_SS_OVERLAY;
/* Enable SPI Slave Select as Output Pins */
/* GPIO 32 is SS2, GPIO 33 is SS3 */
GPIO->GPIODir_high |= 0x0003;
}
#if defined(CONFIG_PCI)
if (GPIOOverlays & BP_PCI) {
mpi_init();
if (GPIOOverlays & BP_CB) {
mpi_DetectPcCard();
}
else {
/*
* CardBus support is defaulted to Slot 0 because there is no external
* IDSEL for CardBus. To disable the CardBus and allow a standard PCI
* card in Slot 0 set the cbus_idsel field to 0x1f.
*/
data = MPI->pcmcia_cntl1;
data |= CARDBUS_IDSEL;
MPI->pcmcia_cntl1 = data;
}
}
#endif
}
#if defined(CONFIG_USB)
USBH->SwapControl = EHCI_ENDIAN_SWAP | OHCI_ENDIAN_SWAP;
USBH->TestPortControl = 0x001c0020;
#endif
return 0;
}
static int __init bcm6368_hw_init(void)
{
#if defined(CONFIG_PCI)
unsigned long data;
#endif
unsigned short GPIOOverlays;
/* Enable SPI interface */
PERF->blkEnables |= SPI_CLK_EN;
GPIO->GPIOMode = 0;
/* Enable Serial LED Interface */
GPIO->GPIOMode |= (GPIO_MODE_SERIAL_LED_CLK | GPIO_MODE_SERIAL_LED_DATA);
GPIO->GPIODir |= 0x00c0;
if( BpGetGPIOverlays(&GPIOOverlays) == BP_SUCCESS ) {
if (GPIOOverlays & BP_LED) {
/* Enable LED Outputs */
}
if (GPIOOverlays & BP_UTOPIA) {
/* Enable UTOPIA interface */
}
if (GPIOOverlays & BP_UART1) {
/* Enable secondary UART interface */
}
if (GPIOOverlays & BP_SPI_EXT_CS) {
/* Enable Overlay for SPI SS Pins */
}
#if defined(CONFIG_PCI)
if (GPIOOverlays & BP_PCI) {
GPIO->GPIOMode |= (GPIO_MODE_PCI_GNT0 |
GPIO_MODE_PCI_REQ0 |
GPIO_MODE_PCI_INTB |
GPIO_MODE_PCI_GNT1 |
GPIO_MODE_PCI_REQ1);
mpi_init();
if (GPIOOverlays & BP_CB) {
GPIO->GPIOMode |= (GPIO_MODE_PCMCIA_VS2 |
GPIO_MODE_PCMCIA_VS1 |
GPIO_MODE_PCMCIA_CD2 |
GPIO_MODE_PCMCIA_CD1);
mpi_DetectPcCard();
}
else {
/*
* CardBus support is defaulted to Slot 0 because there is no external
* IDSEL for CardBus. To disable the CardBus and allow a standard PCI
* card in Slot 0 set the cbus_idsel field to 0x1f.
*/
data = MPI->pcmcia_cntl1;
data |= CARDBUS_IDSEL;
MPI->pcmcia_cntl1 = data;
}
}
#endif
}
#if defined(CONFIG_USB)
PERF->blkEnables |= USBH_CLK_EN;
mdelay(100);
USBH->SwapControl = EHCI_ENDIAN_SWAP | OHCI_ENDIAN_SWAP;
USBH->Setup |= USBH_IOC;
#endif
return 0;
}
static int __init bcm6348_hw_init(void)
{
unsigned long data;
unsigned short GPIOOverlays;
/* Set MPI clock to 33MHz and Utopia clock to 25MHz */
data = PERF->pll_control;
data &= ~MPI_CLK_MASK;
data |= MPI_CLK_33MHZ;
data &= ~MPI_UTOPIA_MASK;
data |= MPI_UTOPIA_25MHZ; /* 6348 utopia frequency has to be 25MHZ */
PERF->pll_control = data;
/* Enable SPI interface */
PERF->blkEnables |= SPI_CLK_EN;
GPIO->GPIOMode = 0;
if( BpGetGPIOverlays(&GPIOOverlays) == BP_SUCCESS ) {
if (GPIOOverlays & BP_UTOPIA) {
/* Enable UTOPIA interface */
GPIO->GPIOMode |= GROUP4_UTOPIA | GROUP3_UTOPIA | GROUP1_UTOPIA;
PERF->blkEnables |= SAR_CLK_EN;
}
if (GPIOOverlays & BP_MII2) {
if (GPIOOverlays & BP_UTOPIA) {
printk ("*************** ERROR ***************\n");
printk ("Invalid GPIO configuration. External MII cannot be enabled with UTOPIA\n");
}
/* Enable external MII interface */
GPIO->GPIOMode |= (GROUP3_EXT_MII|GROUP0_EXT_MII); /* */
}
if (GPIOOverlays & BP_SPI_EXT_CS) {
if (GPIOOverlays & BP_UTOPIA) {
printk ("*************** ERROR ***************\n");
printk ("Invalid GPIO configuration. SPI Extra CS cannot be enabled with UTOPIA\n");
}
/* Enable Extra SPI CS */
GPIO->GPIOMode |= GROUP1_SPI_MASTER;
}
#if defined(CONFIG_PCI)
if (GPIOOverlays & BP_PCI) {
/* Enable PCI interface */
GPIO->GPIOMode |= GROUP2_PCI | GROUP1_MII_PCCARD;
mpi_init();
if (GPIOOverlays & BP_CB) {
mpi_DetectPcCard();
}
else {
/*
* CardBus support is defaulted to Slot 0 because there is no external
* IDSEL for CardBus. To disable the CardBus and allow a standard PCI
* card in Slot 0 set the cbus_idsel field to 0x1f.
*/
data = MPI->pcmcia_cntl1;
data |= CARDBUS_IDSEL;
MPI->pcmcia_cntl1 = data;
}
}
#endif
}
#if defined(CONFIG_USB)
PERF->blkEnables |= USBH_CLK_EN;
mdelay(100);
*USBH = USBH_BYTE_SWAP;
#endif
return 0;
}
