static void
msmsdcc_handle_irq_data(struct msmsdcc_host *host, u32 status,
void __iomem *base)
{
struct mmc_data *data = host->curr.data;
if (!data)
return;
/* Check for data errors */
if (status & (MCI_DATACRCFAIL | MCI_DATATIMEOUT |
MCI_TXUNDERRUN | MCI_RXOVERRUN)) {
msmsdcc_data_err(host, data, status);
host->curr.data_xfered = 0;
if (host->dma.sg)
msm_dmov_stop_cmd(host->dma.channel,
&host->dma.hdr, 0);
else {
msmsdcc_stop_data(host);
if (!data->stop)
msmsdcc_request_end(host, data->mrq);
else
msmsdcc_start_command(host, data->stop, 0);
}
}
/* Check for data done */
if (!host->curr.got_dataend && (status & MCI_DATAEND))
host->curr.got_dataend = 1;
if (!host->curr.got_datablkend && (status & MCI_DATABLOCKEND))
host->curr.got_datablkend = 1;
/*
* If DMA is still in progress, we complete via the completion handler
*/
if (host->curr.got_dataend && host->curr.got_datablkend &&
!host->dma.busy) {
/*
* There appears to be an issue in the controller where
* if you request a small block transfer (< fifo size),
* you may get your DATAEND/DATABLKEND irq without the
* PIO data irq.
*
* Check to see if there is still data to be read,
* and simulate a PIO irq.
*/
if (readl(base + MMCISTATUS) & MCI_RXDATAAVLBL)
msmsdcc_pio_irq(1, host);
msmsdcc_stop_data(host);
if (!data->error)
host->curr.data_xfered = host->curr.xfer_size;
if (!data->stop)
msmsdcc_request_end(host, data->mrq);
else
msmsdcc_start_command(host, data->stop, 0);
}
}
static void msmsdcc_do_cmdirq(struct msmsdcc_host *host, uint32_t status)
{
struct mmc_command *cmd = host->curr.cmd;
void __iomem *base = host->base;
host->curr.cmd = NULL;
cmd->resp[0] = readl(base + MMCIRESPONSE0);
cmd->resp[1] = readl(base + MMCIRESPONSE1);
cmd->resp[2] = readl(base + MMCIRESPONSE2);
cmd->resp[3] = readl(base + MMCIRESPONSE3);
del_timer(&host->command_timer);
if (status & MCI_CMDTIMEOUT) {
cmd->error = -ETIMEDOUT;
} else if (status & MCI_CMDCRCFAIL &&
cmd->flags & MMC_RSP_CRC) {
pr_err("%s: Command CRC error\n", mmc_hostname(host->mmc));
cmd->error = -EILSEQ;
}
if (!cmd->data || cmd->error) {
if (host->curr.data && host->dma.sg)
msm_dmov_stop_cmd(host->dma.channel,
&host->dma.hdr, 0);
else if (host->curr.data) { /* Non DMA */
msmsdcc_stop_data(host);
msmsdcc_request_end(host, cmd->mrq);
} else /* host->data == NULL */
msmsdcc_request_end(host, cmd->mrq);
} else if (!(cmd->data->flags & MMC_DATA_READ))
msmsdcc_start_data(host, cmd->data);
}
static irqreturn_t
msmsdcc_irq(int irq, void *dev_id)
{
struct msmsdcc_host *host = dev_id;
void __iomem *base = host->base;
u32 status;
int ret = 0;
int cardint = 0;
spin_lock(&host->lock);
do {
struct mmc_data *data;
status = readl(base + MMCISTATUS);
#if IRQ_DEBUG
msmsdcc_print_status(host, "irq0-r", status);
#endif
status &= (readl(base + MMCIMASK0) |
MCI_DATABLOCKENDMASK);
writel(status, base + MMCICLEAR);
#if IRQ_DEBUG
msmsdcc_print_status(host, "irq0-p", status);
#endif
data = host->curr.data;
if (data) {
/* Check for data errors */
if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|
MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
msmsdcc_data_err(host, data, status);
host->curr.data_xfered = 0;
if (host->dma.sg)
msm_dmov_stop_cmd(host->dma.channel,
&host->dma.hdr, 0);
else {
msmsdcc_stop_data(host);
if (!data->stop)
msmsdcc_request_end(host,
data->mrq);
else
msmsdcc_start_command(host,
data->stop,
0);
}
}
/* Check for data done */
if (!host->curr.got_dataend && (status & MCI_DATAEND))
host->curr.got_dataend = 1;
if (!host->curr.got_datablkend &&
(status & MCI_DATABLOCKEND)) {
host->curr.got_datablkend = 1;
}
if (host->curr.got_dataend &&
host->curr.got_datablkend) {
/*
* If DMA is still in progress, we complete
* via the completion handler
*/
if (!host->dma.busy) {
/*
* There appears to be an issue in the
* controller where if you request a
* small block transfer (< fifo size),
* you may get your DATAEND/DATABLKEND
* irq without the PIO data irq.
*
* Check to see if theres still data
* to be read, and simulate a PIO irq.
*/
if (readl(base + MMCISTATUS) &
MCI_RXDATAAVLBL)
msmsdcc_pio_irq(1, host);
msmsdcc_stop_data(host);
if (!data->error)
host->curr.data_xfered =
host->curr.xfer_size;
if (!data->stop)
msmsdcc_request_end(host,
data->mrq);
else
msmsdcc_start_command(host,
data->stop, 0);
}
}
}
if (status & (MCI_CMDSENT | MCI_CMDRESPEND | MCI_CMDCRCFAIL |
MCI_CMDTIMEOUT) && host->curr.cmd) {
msmsdcc_do_cmdirq(host, status);
}
if (status & MCI_SDIOINTOPER) {
cardint = 1;
status &= ~MCI_SDIOINTOPER;
}
ret = 1;
} while (status);
spin_unlock(&host->lock);
/*
* We have to delay handling the card interrupt as it calls
* back into the driver.
*/
if (cardint) {
mmc_signal_sdio_irq(host->mmc);
}
return IRQ_RETVAL(ret);
}
static irqreturn_t
msmsdcc_irq(int irq, void *dev_id)
{
struct msmsdcc_host *host = dev_id;
void __iomem *base = host->base;
u32 status;
int ret = 0;
int timer = 0;
spin_lock(&host->lock);
do {
struct mmc_command *cmd;
struct mmc_data *data;
if (timer) {
timer = 0;
msmsdcc_delay(host);
}
status = readl(host->base + MMCISTATUS);
#if IRQ_DEBUG
msmsdcc_print_status(host, "irq0-r", status);
#endif
status &= (readl(host->base + MMCIMASK0) |
MCI_DATABLOCKENDMASK);
writel(status, host->base + MMCICLEAR);
#if IRQ_DEBUG
msmsdcc_print_status(host, "irq0-p", status);
#endif
if ((host->plat->dummy52_required) &&
(host->dummy_52_state == DUMMY_52_STATE_SENT)) {
if (status & MCI_PROGDONE) {
host->dummy_52_state = DUMMY_52_STATE_NONE;
host->curr.cmd = NULL;
spin_unlock(&host->lock);
msmsdcc_request_start(host, host->curr.mrq);
return IRQ_HANDLED;
}
break;
}
data = host->curr.data;
#ifdef CONFIG_MMC_MSM_SDIO_SUPPORT
if (status & MCI_SDIOINTROPE)
mmc_signal_sdio_irq(host->mmc);
#endif
/*
* Check for proper command response
*/
cmd = host->curr.cmd;
if ((status & (MCI_CMDSENT | MCI_CMDRESPEND | MCI_CMDCRCFAIL |
MCI_CMDTIMEOUT | MCI_PROGDONE)) && cmd) {
host->curr.cmd = NULL;
cmd->resp[0] = readl(base + MMCIRESPONSE0);
cmd->resp[1] = readl(base + MMCIRESPONSE1);
cmd->resp[2] = readl(base + MMCIRESPONSE2);
cmd->resp[3] = readl(base + MMCIRESPONSE3);
if (status & MCI_CMDTIMEOUT) {
#if VERBOSE_COMMAND_TIMEOUTS
pr_err("%s: Command timeout\n",
mmc_hostname(host->mmc));
#endif
cmd->error = -ETIMEDOUT;
} else if (status & MCI_CMDCRCFAIL &&
cmd->flags & MMC_RSP_CRC) {
pr_err("%s: Command CRC error\n",
mmc_hostname(host->mmc));
cmd->error = -EILSEQ;
}
if (!cmd->data || cmd->error) {
if (host->curr.data && host->dma.sg)
msm_dmov_stop_cmd(host->dma.channel,
&host->dma.hdr, 0);
else if (host->curr.data) { /* Non DMA */
msmsdcc_stop_data(host);
timer |= msmsdcc_request_end(host,
cmd->mrq);
} else { /* host->data == NULL */
if (!cmd->error && host->prog_enable) {
if (status & MCI_PROGDONE) {
host->prog_scan = 0;
host->prog_enable = 0;
timer |=
msmsdcc_request_end(
host, cmd->mrq);
} else
host->curr.cmd = cmd;
} else {
if (host->prog_enable) {
host->prog_scan = 0;
host->prog_enable = 0;
}
timer |=
msmsdcc_request_end(
host, cmd->mrq);
}
}
} else if (cmd->data) {
if (!(cmd->data->flags & MMC_DATA_READ))
msmsdcc_start_data(host, cmd->data,
NULL, 0);
}
}
if (data) {
/* Check for data errors */
if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|
MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
msmsdcc_data_err(host, data, status);
host->curr.data_xfered = 0;
if (host->dma.sg)
msm_dmov_stop_cmd(host->dma.channel,
&host->dma.hdr, 0);
else {
msmsdcc_reset_and_restore(host);
if (host->curr.data)
msmsdcc_stop_data(host);
if (!data->stop)
timer |=
msmsdcc_request_end(host,
data->mrq);
else {
msmsdcc_start_command(host,
data->stop,
0);
timer = 1;
}
}
}
/* Check for data done */
if (!host->curr.got_dataend && (status & MCI_DATAEND))
host->curr.got_dataend = 1;
if (!host->curr.got_datablkend &&
(status & MCI_DATABLOCKEND)) {
host->curr.got_datablkend = 1;
}
if (host->curr.got_dataend &&
host->curr.got_datablkend) {
/*
* If DMA is still in progress, we complete
* via the completion handler
*/
if (!host->dma.busy) {
/*
* There appears to be an issue in the
* controller where if you request a
* small block transfer (< fifo size),
* you may get your DATAEND/DATABLKEND
* irq without the PIO data irq.
*
* Check to see if theres still data
* to be read, and simulate a PIO irq.
*/
if (readl(host->base + MMCISTATUS) &
MCI_RXDATAAVLBL)
msmsdcc_pio_irq(1, host);
msmsdcc_stop_data(host);
if (!data->error)
host->curr.data_xfered =
host->curr.xfer_size;
if (!data->stop)
timer |= msmsdcc_request_end(
host, data->mrq);
else {
#if defined (CONFIG_MACH_ACER_A1)
while ((host->pdev_id == 1) &&
(data->flags & MMC_DATA_WRITE) &&
(gpio_get_value(SDCC1_DATA_0) == 0)) {
udelay(5);
}
#endif
msmsdcc_start_command(host,
data->stop, 0);
timer = 1;
}
}
}
}
ret = 1;
} while (status);
spin_unlock(&host->lock);
return IRQ_RETVAL(ret);
}
static int irda_uart_release(struct inode *inode, struct file *file)
{
down(&irc->sem);
printk(KERN_INFO DRV_NAME ": %s\n", __func__);
/* Decrement refcount */
irc->refcount--;
/* Check refcount */
if (irc->refcount == 0) {
/* do discard flush */
if (irc->rx_state == IRDA_RX_START) {
irc->rx_state = IRDA_RX_IDLE;
msm_dmov_stop_cmd(irc->pfdata->chan_uartdm_rx,
&irc->rxdmov_cmd, 0);
}
/* Deactivate RXLEV IRQ */
irc->imr_reg &= ~BIT_RXLEV;
msm_uartdm_write(UARTDM_IMR, irc->imr_reg);
/* (state change)--> IRDA_UART_OPEN */
irc->state = IRDA_UART_CLOSE;
/* Disable the IRDA transceiver */
msm_uartdm_write(UARTDM_IRDA, IRUART_IRDA_DISABLE);
/* Disable Transmitter and Receiver */
msm_uartdm_write(UARTDM_CR, BIT_UART_TX_DISABLE);
msm_uartdm_write(UARTDM_CR, BIT_UART_RX_DISABLE);
/* Desable TXDM and RXDM mode */
msm_uartdm_write(UARTDM_DMEN, IRUART_IRDA_DISABLE);
/* Wait 1usec */
udelay(1);
/* Setting PM power off (Hig) */
pm8058_gpio_config(irc->pfdata->gpio_pow,
irc->pfdata->gpio_pwcfg_hig);
/* Clear UART SW buffer */
irda_txbuf_clear(&irc->txbuf);
irda_rxbuf_clear(&irc->rxbuf);
/* Reset TX and RX*/
msm_uartdm_write(UARTDM_CR, CCMD_RESET_RECEIVER);
msm_uartdm_write(UARTDM_CR, CCMD_RESET_TRANSMITTER);
msm_uartdm_write(UARTDM_CR, CCMD_RESET_ERROR_STATUS);
msm_uartdm_write(UARTDM_CR, CCMD_RESET_STALE_INTERRUPT);
/* Release DMOV data */
dma_free_coherent(NULL, sizeof(dmov_box),
irc->txbox, irc->mapped_txbox);
dma_free_coherent(NULL, sizeof(dmov_box),
irc->rxbox, irc->mapped_rxbox);
dma_free_coherent(NULL, sizeof(u32 *),
irc->txbox_ptr, irc->mapped_txbox_ptr);
dma_free_coherent(NULL, sizeof(u32 *),
irc->rxbox_ptr, irc->mapped_rxbox_ptr);
/* UARTDM clock stop */
clk_disable(irc->clk_uartdm);
/* UARTDM iounmap */
if (irc->iores_uartdm)
release_mem_region((u32) irc->pfdata->paddr_uartdm,
UARTDM_SIZE);
iounmap(irc->vaddr_uartdm);
/* Remove IRQ for UARTDM */
free_irq(irc->pfdata->irq_uartdm, irc);
/* Remove tasklets for UARTDM */
tasklet_kill(&irc->tasklet_rxfer_s);
tasklet_kill(&irc->tasklet_rxfer_e);
tasklet_kill(&irc->tasklet_txfer);
/* PM8058 UART MUX reset */
pm8058_misc_control(irc->nfcdev->pm_chip,
PM8058_UART_MUX_MASK, PM8058_UART_MUX_NO);
{
u8 misc = 0x0;
int ret = pm8058_read(irc->nfcdev->pm_chip,
SSBI_REG_ADDR_MISC, &misc, 1);
if (ret)
printk(KERN_ERR DRV_NAME
": cannot read pm8058 UART MUX reg.\n");
else
printk(KERN_INFO DRV_NAME
": misc register = %x\n", misc);
}
}
printk(KERN_INFO DRV_NAME ": Closed. Refcount = %d\n", irc->refcount);
up(&irc->sem);
return 0;
}