static int mt76x2_init_hardware(struct mt76x02_dev *dev)
{
int ret;
mt76x02_dma_disable(dev);
mt76x2_reset_wlan(dev, true);
mt76x2_power_on(dev);
ret = mt76x2_eeprom_init(dev);
if (ret)
return ret;
ret = mt76x2_mac_reset(dev, true);
if (ret)
return ret;
dev->mt76.rxfilter = mt76_rr(dev, MT_RX_FILTR_CFG);
ret = mt76x02_dma_init(dev);
if (ret)
return ret;
set_bit(MT76_STATE_INITIALIZED, &dev->mt76.state);
ret = mt76x2_mac_start(dev);
if (ret)
return ret;
ret = mt76x2_mcu_init(dev);
if (ret)
return ret;
mt76x2_mac_stop(dev, false);
return 0;
}
int mt76x2_init_hardware(struct mt76x2_dev *dev)
{
static const u16 beacon_offsets[16] = {
/* 1024 byte per beacon */
0xc000,
0xc400,
0xc800,
0xcc00,
0xd000,
0xd400,
0xd800,
0xdc00,
/* BSS idx 8-15 not used for beacons */
0xc000,
0xc000,
0xc000,
0xc000,
0xc000,
0xc000,
0xc000,
0xc000,
};
u32 val;
int ret;
dev->beacon_offsets = beacon_offsets;
tasklet_init(&dev->pre_tbtt_tasklet, mt76x2_pre_tbtt_tasklet,
(unsigned long) dev);
dev->chainmask = 0x202;
dev->slottime = 9;
val = mt76_rr(dev, MT_WPDMA_GLO_CFG);
val &= MT_WPDMA_GLO_CFG_DMA_BURST_SIZE |
MT_WPDMA_GLO_CFG_BIG_ENDIAN |
MT_WPDMA_GLO_CFG_HDR_SEG_LEN;
val |= MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE;
mt76_wr(dev, MT_WPDMA_GLO_CFG, val);
mt76x2_reset_wlan(dev, true);
mt76x2_power_on(dev);
ret = mt76x2_eeprom_init(dev);
if (ret)
return ret;
ret = mt76x2_mac_reset(dev, true);
if (ret)
return ret;
ret = mt76x2_dma_init(dev);
if (ret)
return ret;
set_bit(MT76_STATE_INITIALIZED, &dev->mt76.state);
ret = mt76x2_mac_start(dev);
if (ret)
return ret;
ret = mt76x2_mcu_init(dev);
if (ret)
return ret;
mt76x2_mac_stop(dev, false);
dev->rxfilter = mt76_rr(dev, MT_RX_FILTR_CFG);
return 0;
}
