void lk_scheduler(void)
{
	static enum handler_return ret;

	mt_irq_ack(MT6575_GPT_IRQ_ID);
	DRV_WriteReg32( GPT_IRQACK_REG, 0x10); 
	ret = timer_irq(0);
	if(ret == INT_RESCHEDULE) {
        	thread_preempt();
    	}
	DRV_WriteReg32(GPT5_CON_REG, GPT_CLEAR);
	DRV_WriteReg32(GPT5_CON_REG, GPT_ENABLE|GPT_MODE4_ONE_SHOT);
}
Beispiel #2
0
void dummy_ap_irq_handler(unsigned int irq)
{
	switch(irq){
	case MT_MD_WDT1_IRQ_ID:
		md_wdt_irq_handler(MT_MD_WDT1_IRQ_ID);
		mt_irq_ack(MT_MD_WDT1_IRQ_ID);
		mt_irq_unmask(MT_MD_WDT1_IRQ_ID);
		break;

	default:
		break;
	}
}
Beispiel #3
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enum handler_return lk_scheduler(void)
{
    static enum handler_return ret;

    /* ack GPT5 irq */
    DRV_WriteReg32(GPT_IRQACK_REG, 0x10);
    DRV_WriteReg32(GPT5_CON_REG, GPT_CLEAR);
    DRV_WriteReg32(GPT5_CON_REG, GPT_DISABLE);

    ret = timer_irq(0);

    /* ack GIC irq */
    mt_irq_ack(MT_GPT_IRQ_ID);

    /* enable GPT5 */
    DRV_WriteReg32(GPT5_CON_REG, GPT_ENABLE|GPT_MODE4_ONE_SHOT);

    return ret;
}
Beispiel #4
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void lk_scheduler(void)
{
	//static enum handler_return ret;

	/* ack GPT5 irq */
	DRV_WriteReg32(GPT_IRQACK_REG, 0x10);
	DRV_WriteReg32(GPT5_CON_REG, GPT_CLEAR);
	DRV_WriteReg32(GPT5_CON_REG, GPT_DISABLE);

	timer_irq(0);

	/*
	 * CAUTION! The de-assert signal to GIC might delay serveral clocks.
	 * Here must have enough delay to make sure the GPT signal had arrived GIC.
	 */
	/* ack GIC irq */
	mt_irq_ack(MT_GPT_IRQ_ID);

	/* enable GPT5 */
	DRV_WriteReg32(GPT5_CON_REG, GPT_ENABLE|GPT_MODE4_ONE_SHOT);

}