int disphal_pm_restore_noirq(struct device *device)
{
// DPI0
mt_irq_set_sens(MT6582_DISP_DPI0_IRQ_ID, MT_LEVEL_SENSITIVE);
mt_irq_set_polarity(MT6582_DISP_DPI0_IRQ_ID, MT_POLARITY_LOW);
// DSI
mt_irq_set_sens(MT6582_DISP_DSI_IRQ_ID, MT_LEVEL_SENSITIVE);
mt_irq_set_polarity(MT6582_DISP_DSI_IRQ_ID, MT_POLARITY_LOW);
return 0;
}
int spc_pm_restore_noirq(struct device *device)
{
mt_irq_set_sens(MT_APARM_DOMAIN_IRQ_ID, MT65xx_LEVEL_SENSITIVE);
mt_irq_set_polarity(MT_APARM_DOMAIN_IRQ_ID, MT65xx_POLARITY_LOW);
return 0;
}
status_t platform_set_periodic_timer(platform_timer_callback callback, void *arg, lk_time_t interval)
{
time_callback = callback;
tick_interval = interval;
callback_arg = arg;
DRV_WriteReg32(GPT_IRQEN_REG, 0);
DRV_WriteReg32(GPT_IRQACK_REG, 0x3f);
mt_irq_set_sens(MT_GPT_IRQ_ID, MT65xx_LEVEL_SENSITIVE);
mt_irq_set_polarity(MT_GPT_IRQ_ID, MT65xx_POLARITY_LOW);
DRV_WriteReg32(GPT5_CON_REG, 0x02);
DRV_WriteReg32(GPT_IRQACK_REG, 0x10);
DRV_WriteReg32(GPT5_CLK_REG , 0x10);
DRV_WriteReg32(GPT5_COMPARE_REG, TIMER_TICK_RATE*interval/1000);
DRV_WriteReg32(GPT_IRQEN_REG, 0x10);
mt_irq_unmask(MT_GPT_IRQ_ID);
DRV_WriteReg32(GPT5_CON_REG, GPT_ENABLE|GPT_MODE4_ONE_SHOT);
return NO_ERROR;
}
/*
* mt_irq_set_type: set interrupt type
* @irq: interrupt id
* @flow_type: interrupt type
* Always return 0.
*/
static int mt_irq_set_type(struct irq_data *data, unsigned int flow_type)
{
const unsigned int irq = data->irq;
if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
mt_irq_set_sens(irq, MT65xx_EDGE_SENSITIVE);
mt_irq_set_polarity(irq, (flow_type & IRQF_TRIGGER_FALLING) ? 0 : 1);
__irq_set_handler_locked(irq, handle_edge_irq);
} else if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) {
mt_irq_set_sens(irq, MT65xx_LEVEL_SENSITIVE);
mt_irq_set_polarity(irq, (flow_type & IRQF_TRIGGER_LOW) ? 0 : 1);
__irq_set_handler_locked(irq, handle_level_irq);
}
return 0;
}
static int devapc_pm_restore_noirq(struct device *device)
{
if (devapc_irq != 0) {
mt_irq_set_sens(devapc_irq, MT_LEVEL_SENSITIVE);
mt_irq_set_polarity(devapc_irq, MT_POLARITY_LOW);
}
return 0;
}
static int mjc_pm_restore_noirq(struct device *device)
{
//IRQF_TRIGGER_LOW
//Gary todo
mt_irq_set_sens(gi4IrqID, MT_LEVEL_SENSITIVE);
mt_irq_set_polarity(gi4IrqID, MT_POLARITY_LOW);
return 0;
}
int eemcs_helper_pm_restore_noirq(struct device *device)
{
pr_debug("calling %s()\n", __func__);
/*Not ready, need to check more details*/
#if 0
// CCIF AP0
mt_irq_set_sens(CCIF0_AP_IRQ_ID, MT_LEVEL_SENSITIVE);
mt_irq_set_polarity(CCIF0_AP_IRQ_ID, MT_POLARITY_LOW);
// MD1 WDT
mt_irq_set_sens(MD_WDT_IRQ_ID, MT_EDGE_SENSITIVE);
mt_irq_set_polarity(MD_WDT_IRQ_ID, MT_POLARITY_LOW);
// MD1
exec_ccci_kern_func_by_md_id(0, ID_IPO_H_RESTORE_CB, NULL, 0);
#endif
return 0;
}
int gpt_irq_init(void)
{
//1. Disable all gpt irq bits
DRV_WriteReg32(GPT_IRQ_EN, 0);
//2. Ack all gpt irq if needed
DRV_WriteReg32(GPT_IRQ_ACK, 0x3F);
//3. Register gpt irq for GIC
mt_irq_set_sens(MT_GPT_IRQ_ID, MT65xx_LEVEL_SENSITIVE);
mt_irq_set_polarity(MT_GPT_IRQ_ID, MT65xx_POLARITY_LOW);
return 0;
}
void md_wdt_init(void)
{
mt_irq_set_sens(MT_MD_WDT1_IRQ_ID, MT65xx_EDGE_SENSITIVE);
mt_irq_set_polarity(MT_MD_WDT1_IRQ_ID, MT65xx_POLARITY_LOW);
mt_irq_unmask(MT_MD_WDT1_IRQ_ID);
}
