/* * pci_pre_init * * This routine is called just prior to registering the hose and gives * the board the opportunity to check things. Returning a value of zero * indicates that things are bad & PCI initialization should be aborted. * * Different boards may wish to customize the pci controller structure * (add regions, override default access routines, etc) or perform * certain pre-initialization actions. * */ int pci_pre_init(struct pci_controller *hose) { unsigned long addr; if (!board_with_pci()) { return 0; } /* * Set priority for all PLB3 devices to 0. * Set PLB3 arbiter to fair mode. */ mfsdr(SD0_AMP1, addr); mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00); addr = mfdcr(PLB3_ACR); mtdcr(PLB3_ACR, addr | 0x80000000); /* Sequoia */ /* * Set priority for all PLB4 devices to 0. */ mfsdr(SD0_AMP0, addr); mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00); addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */ mtdcr(PLB4_ACR, addr); /* Sequoia */ /* * As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM. * Workaround: Disable write pipelining to DDR SDRAM by setting * PLB0_ACR[WRP] = 0. */ mtdcr(PLB0_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */ /* Segment1 */ mtdcr(PLB1_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */ return board_with_pci(); }
int misc_init_r(void) { u32 sdr0_srst1 = 0; u32 eth_cfg; /* * Set EMAC mode/configuration (GMII, SGMII, RGMII...). * This is board specific, so let's do it here. */ mfsdr(SDR0_ETH_CFG, eth_cfg); /* disable SGMII mode */ eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE | SDR0_ETH_CFG_SGMII1_ENABLE | SDR0_ETH_CFG_SGMII0_ENABLE); /* Set the for 2 RGMII mode */ /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */ eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL; eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL; mtsdr(SDR0_ETH_CFG, eth_cfg); /* * The AHB Bridge core is held in reset after power-on or reset * so enable it now */ mfsdr(SDR0_SRST1, sdr0_srst1); sdr0_srst1 &= ~SDR0_SRST1_AHB; mtsdr(SDR0_SRST1, sdr0_srst1); return 0; }
int board_early_init_f(void) { /* * Setup the interrupt controller polarities, triggers, etc. */ mtdcr(UIC0SR, 0xffffffff); /* clear all */ mtdcr(UIC0ER, 0x00000000); /* disable all */ mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */ mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ mtdcr(UIC0SR, 0xffffffff); /* clear all */ mtdcr(UIC1SR, 0xffffffff); /* clear all */ mtdcr(UIC1ER, 0x00000000); /* disable all */ mtdcr(UIC1CR, 0x00000000); /* all non-critical */ mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ mtdcr(UIC1SR, 0xffffffff); /* clear all */ mtdcr(UIC2SR, 0xffffffff); /* clear all */ mtdcr(UIC2ER, 0x00000000); /* disable all */ mtdcr(UIC2CR, 0x00000000); /* all non-critical */ mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ mtdcr(UIC2SR, 0xffffffff); /* clear all */ mtdcr(UIC3SR, 0xffffffff); /* clear all */ mtdcr(UIC3ER, 0x00000000); /* disable all */ mtdcr(UIC3CR, 0x00000000); /* all non-critical */ mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */ mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */ mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */ mtdcr(UIC3SR, 0xffffffff); /* clear all */ /* * Configure PFC (Pin Function Control) registers * enable GPIO 49-63 * UART0: 4 pins */ mtsdr(SDR0_PFC0, 0x00007fff); mtsdr(SDR0_PFC1, 0x00040000); /* Enable PCI host functionality in SDR0_PCI0 */ mtsdr(SDR0_PCI0, 0xe0000000); mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */ /* Setup PLB4-AHB bridge based on the system address map */ mtdcr(AHB_TOP, 0x8000004B); mtdcr(AHB_BOT, 0x8000004B); return 0; }
int pci_pre_init(struct pci_controller *hose) { unsigned long strap; unsigned long addr; /*--------------------------------------------------------------------------+ * Bamboo is always configured as the host & requires the * PCI arbiter to be enabled. *--------------------------------------------------------------------------*/ mfsdr(sdr_sdstp1, strap); if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) { printf("PCI: SDR0_STRP1[PAE] not set.\n"); printf("PCI: Configuration aborted.\n"); return 0; } /*-------------------------------------------------------------------------+ | Set priority for all PLB3 devices to 0. | Set PLB3 arbiter to fair mode. +-------------------------------------------------------------------------*/ mfsdr(sdr_amp1, addr); mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); addr = mfdcr(plb3_acr); mtdcr(plb3_acr, addr | 0x80000000); /*-------------------------------------------------------------------------+ | Set priority for all PLB4 devices to 0. +-------------------------------------------------------------------------*/ mfsdr(sdr_amp0, addr); mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ mtdcr(plb4_acr, addr); /*-------------------------------------------------------------------------+ | Set Nebula PLB4 arbiter to fair mode. +-------------------------------------------------------------------------*/ /* Segment0 */ addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; mtdcr(plb0_acr, addr); /* Segment1 */ addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; mtdcr(plb1_acr, addr); return 1; }
/************************************************************************* * int board_early_init_f() * ************************************************************************/ int board_early_init_f(void) { u32 mfr; mtebc( PB0AP, 0x03800000 ); /* set chip selects */ mtebc( PB0CR, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */ mtebc( PB1AP, 0x03800000 ); mtebc( PB1CR, 0xff018000 ); /* ebc0_b1cr, 1MB at 0xff000000 CS1 */ mtebc( PB2AP, 0x03800000 ); mtebc( PB2CR, 0xff838000 ); /* ebc0_b2cr, 2MB at 0xff800000 CS2 */ mtdcr( UIC1SR, 0xffffffff ); /* Clear all interrupts */ mtdcr( UIC1ER, 0x00000000 ); /* disable all interrupts */ mtdcr( UIC1CR, 0x00000000 ); /* Set Critical / Non Critical interrupts */ mtdcr( UIC1PR, 0x7fff83ff ); /* Set Interrupt Polarities */ mtdcr( UIC1TR, 0x001f8000 ); /* Set Interrupt Trigger Levels */ mtdcr( UIC1VR, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */ mtdcr( UIC1SR, 0x00000000 ); /* clear all interrupts */ mtdcr( UIC1SR, 0xffffffff ); mtdcr( UIC0SR, 0xffffffff ); /* Clear all interrupts */ mtdcr( UIC0ER, 0x00000000 ); /* disable all interrupts excepted cascade */ mtdcr( UIC0CR, 0x00000001 ); /* Set Critical / Non Critical interrupts */ mtdcr( UIC0PR, 0xffffffff ); /* Set Interrupt Polarities */ mtdcr( UIC0TR, 0x01000004 ); /* Set Interrupt Trigger Levels */ mtdcr( UIC0VR, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */ mtdcr( UIC0SR, 0x00000000 ); /* clear all interrupts */ mtdcr( UIC0SR, 0xffffffff ); mfsdr(SDR0_MFR, mfr); mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ mtsdr(SDR0_MFR, mfr); return 0; }
/************************************************************************* * int board_early_init_f() * ************************************************************************/ int board_early_init_f(void) { u32 mfr; mtebc( pb0ap, 0x03800000 ); /* set chip selects */ mtebc( pb0cr, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */ mtebc( pb1ap, 0x03800000 ); mtebc( pb1cr, 0xff018000 ); /* ebc0_b1cr, 1MB at 0xff000000 CS1 */ mtebc( pb2ap, 0x03800000 ); mtebc( pb2cr, 0xff838000 ); /* ebc0_b2cr, 2MB at 0xff800000 CS2 */ mtdcr( uic1sr, 0xffffffff ); /* Clear all interrupts */ mtdcr( uic1er, 0x00000000 ); /* disable all interrupts */ mtdcr( uic1cr, 0x00000000 ); /* Set Critical / Non Critical interrupts */ mtdcr( uic1pr, 0x7fff83ff ); /* Set Interrupt Polarities */ mtdcr( uic1tr, 0x001f8000 ); /* Set Interrupt Trigger Levels */ mtdcr( uic1vr, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */ mtdcr( uic1sr, 0x00000000 ); /* clear all interrupts */ mtdcr( uic1sr, 0xffffffff ); mtdcr( uic0sr, 0xffffffff ); /* Clear all interrupts */ mtdcr( uic0er, 0x00000000 ); /* disable all interrupts excepted cascade */ mtdcr( uic0cr, 0x00000001 ); /* Set Critical / Non Critical interrupts */ mtdcr( uic0pr, 0xffffffff ); /* Set Interrupt Polarities */ mtdcr( uic0tr, 0x01000004 ); /* Set Interrupt Trigger Levels */ mtdcr( uic0vr, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */ mtdcr( uic0sr, 0x00000000 ); /* clear all interrupts */ mtdcr( uic0sr, 0xffffffff ); mfsdr(sdr_mfr, mfr); mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ mtsdr(sdr_mfr, mfr); return 0; }
void ClockOn(const rtems_irq_connect_data* unused) { uint32_t iocr, r; ppc_cpu_id_t cpu; Clock_driver_ticks = 0; cpu = get_ppc_cpu_type(); if (cpu==PPC_405GP) { iocr = mfdcr(CPC0_CR1); if (bsp_timer_internal_clock) iocr &= ~CR1_CETE ;/* timer clocked from system clock */ else iocr |= CR1_CETE; /* select external timer clock */ mtdcr(CPC0_CR1,iocr); } else if (cpu==PPC_405EX) { mfsdr(SDR0_C405,iocr); if (bsp_timer_internal_clock) iocr &= ~SDR_CETE ;/* timer clocked from system clock */ else iocr |= SDR_CETE; /* select external timer clock */ mtsdr(SDR0_C405,iocr); } else { printk("clock.c:unrecognised CPU"); rtems_fatal_error_occurred(1); } pit_value = rtems_configuration_get_microseconds_per_tick() * bsp_clicks_per_usec; mtspr(PIT,pit_value); tick_time = mfspr(TBL) + pit_value; r = mfspr(TCR); mtspr(TCR, r | PIE | ARE); }
int board_early_init_f(void) { register uint reg; set_leds(0); /* display boot info counter */ /*-------------------------------------------------------------------- * Setup the external bus controller/chip selects *-------------------------------------------------------------------*/ mtdcr(ebccfga, xbcfg); reg = mfdcr(ebccfgd); mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */ /*-------------------------------------------------------------------- * GPIO's are alreay setup in cpu/ppc4xx/cpu_init.c * via define from board config file. *-------------------------------------------------------------------*/ /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. *-------------------------------------------------------------------*/ mtdcr(uic0sr, 0xffffffff); /* clear all */ mtdcr(uic0er, 0x00000000); /* disable all */ mtdcr(uic0cr, 0x00000001); /* UIC1 crit is critical */ mtdcr(uic0pr, 0xfffffe1f); /* per ref-board manual */ mtdcr(uic0tr, 0x01c00000); /* per ref-board manual */ mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr(uic0sr, 0xffffffff); /* clear all */ mtdcr(uic1sr, 0xffffffff); /* clear all */ mtdcr(uic1er, 0x00000000); /* disable all */ mtdcr(uic1cr, 0x00000000); /* all non-critical */ mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr(uic1sr, 0xffffffff); /* clear all */ /*-------------------------------------------------------------------- * Setup other serial configuration *-------------------------------------------------------------------*/ mfsdr(sdr_pci0, reg); mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */ mtsdr(sdr_pfc0, 0x00000100); /* Pin function: enable GPIO49-63 */ mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins, select IRQ5 */ return 0; }
static void InitUARTClock(void) { uint32_t reg; mfsdr(SDR0_UART0,reg); reg &= ~0x008000FF; reg |= 0x00800001; /* Ext clock, div 1 */ mtsdr(SDR0_UART0,reg); }
/* * pci_pre_init * * This routine is called just prior to registering the hose and gives * the board the opportunity to check things. Returning a value of zero * indicates that things are bad & PCI initialization should be aborted. * * Different boards may wish to customize the pci controller structure * (add regions, override default access routines, etc) or perform * certain pre-initialization actions. * */ int __pci_pre_init(struct pci_controller *hose) { u32 reg; /* * Set priority for all PLB3 devices to 0. * Set PLB3 arbiter to fair mode. */ mfsdr(SDR0_AMP1, reg); mtsdr(SDR0_AMP1, (reg & 0x000000FF) | 0x0000FF00); reg = mfdcr(PLB3A0_ACR); mtdcr(PLB3A0_ACR, reg | 0x80000000); /* * Set priority for all PLB4 devices to 0. */ mfsdr(SDR0_AMP0, reg); mtsdr(SDR0_AMP0, (reg & 0x000000FF) | 0x0000FF00); reg = mfdcr(PLB4A0_ACR) | 0xa0000000; mtdcr(PLB4A0_ACR, reg); /* * Set Nebula PLB4 arbiter to fair mode. */ /* Segment0 */ reg = (mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_PPM_MASK) | PLB4Ax_ACR_PPM_FAIR; reg = (reg & ~PLB4Ax_ACR_HBU_MASK) | PLB4Ax_ACR_HBU_ENABLED; reg = (reg & ~PLB4Ax_ACR_RDP_MASK) | PLB4Ax_ACR_RDP_4DEEP; reg = (reg & ~PLB4Ax_ACR_WRP_MASK) | PLB4Ax_ACR_WRP_2DEEP; mtdcr(PLB4A0_ACR, reg); /* Segment1 */ reg = (mfdcr(PLB4A1_ACR) & ~PLB4Ax_ACR_PPM_MASK) | PLB4Ax_ACR_PPM_FAIR; reg = (reg & ~PLB4Ax_ACR_HBU_MASK) | PLB4Ax_ACR_HBU_ENABLED; reg = (reg & ~PLB4Ax_ACR_RDP_MASK) | PLB4Ax_ACR_RDP_4DEEP; reg = (reg & ~PLB4Ax_ACR_WRP_MASK) | PLB4Ax_ACR_WRP_2DEEP; mtdcr(PLB4A1_ACR, reg); #if defined(CONFIG_SYS_PCI_BOARD_FIXUP_IRQ) hose->fixup_irq = board_pci_fixup_irq; #endif return 1; }
int pci_pre_init(struct pci_controller *hose) { unsigned long addr; /*-------------------------------------------------------------------------+ | Set priority for all PLB3 devices to 0. | Set PLB3 arbiter to fair mode. +-------------------------------------------------------------------------*/ mfsdr(sdr_amp1, addr); mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); addr = mfdcr(plb3_acr); mtdcr(plb3_acr, addr | 0x80000000); /*-------------------------------------------------------------------------+ | Set priority for all PLB4 devices to 0. +-------------------------------------------------------------------------*/ mfsdr(sdr_amp0, addr); mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ mtdcr(plb4_acr, addr); /*-------------------------------------------------------------------------+ | Set Nebula PLB4 arbiter to fair mode. +-------------------------------------------------------------------------*/ /* Segment0 */ addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; mtdcr(plb0_acr, addr); /* Segment1 */ addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; mtdcr(plb1_acr, addr); return 1; }
/* * phys_size_t initdram(int board_type) * * As the name already indicates, this function is called very early * from start.S and configures the SDRAM with fixed values. This is needed, * since the 440EP has no internal SRAM and the 4kB NAND_SPL loader has * not enough free space to implement the complete I2C SPD DDR autodetection * routines. Therefore the Bamboo only supports the onboard 64MBytes of SDRAM * when booting from NAND flash. * * Note: * As found out by Eugene O'Brien <*****@*****.**>, the fixed * DDR setup has problems (U-Boot crashes randomly upon TFTP), when the DIMM * modules are still plugged in. So it is recommended to remove the DIMM * modules while using the NAND booting code with the fixed SDRAM setup! */ phys_size_t initdram(int board_type) { /* * Soft-reset SDRAM controller. */ mtsdr(SDR0_SRST, SDR0_SRST_DMC); mtsdr(SDR0_SRST, 0x00000000); /* * Disable memory controller. */ mtsdram(SDRAM0_CFG0, 0x00000000); /* * Setup some default */ mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */ mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */ mtsdram(SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */ mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ /* * Following for CAS Latency = 2.5 @ 133 MHz PLB */ mtsdram(SDRAM0_B0CR, 0x00082001); mtsdram(SDRAM0_TR0, 0x41094012); mtsdram(SDRAM0_TR1, 0x8080083d); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/ mtsdram(SDRAM0_RTR, 0x04100000); /* Interval 7.8µs @ 133MHz PLB */ mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM*/ /* * Enable the controller, then wait for DCEN to complete */ mtsdram(SDRAM0_CFG0, 0x80000000); /* DCEN=1, PMUD=0*/ wait_init_complete(); return CONFIG_SYS_MBYTES_SDRAM << 20; }
/* * This function is called from the SPL U-Boot version for * early init stuff, that needs to be done for OS (e.g. Linux) * booting. Doing it later in the real U-Boot would not work * in case that the SPL U-Boot boots Linux directly. */ void spl_board_init(void) { const gdc_regs *regs = board_get_regs(); /* * Setup PFC registers, mainly for ethernet support * later on in Linux */ board_early_init_f(); /* enable the LSB transmitter */ gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1); /* * Clear resets */ mtsdr(SDR0_SRST1, 0x00000000); mtsdr(SDR0_SRST0, 0x00000000); /* * Reset Lime controller */ gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1); udelay(500); gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1); out_be32((void *)CONFIG_SYS_LIME_SDRAM_CLOCK, CONFIG_SYS_MB862xx_CCF); udelay(300); out_be32((void *)CONFIG_SYS_LIME_MMR, CONFIG_SYS_MB862xx_MMR); while (regs->index) { out_be32((void *)(CONFIG_SYS_LIME_BASE_0 + GC_DISP_BASE) + regs->index, regs->value); regs++; } board_backlight_brightness(DEFAULT_BRIGHTNESS); }
static void dwctwo_plb_attach(device_t parent, device_t self, void *aux) { struct dwc2_softc *sc = device_private(self); struct plb_attach_args *paa = aux; prop_dictionary_t dict = device_properties(self); uint32_t srst0; sc->sc_dev = self; /* get core parameters */ if (!prop_dictionary_get_uint32(dict, "params", (uint32_t *)&sc->sc_params)) { aprint_error("struct dwc2_core_params not found\n"); return; } dwctwo_tag.pbs_base = paa->plb_addr; dwctwo_tag.pbs_limit += paa->plb_addr; if (bus_space_init(&dwctwo_tag, "dwctwotag", ex_storage, sizeof(ex_storage))) panic("dwctwo_attach: Failed to initialise opb_tag"); sc->sc_iot = &dwctwo_tag; bus_space_map(sc->sc_iot, paa->plb_addr, DWCTWO_SIZE, 0, &sc->sc_ioh); sc->sc_bus.dmatag = paa->plb_dmat; intr_establish(paa->plb_irq, IST_LEVEL, IPL_SCHED, dwc2_intr, sc); /* Enable the USB interface. */ mtsdr(DCR_SDR0_PFC1, mfsdr(DCR_SDR0_PFC1) | SDR0_PFC1_USBEN); srst0 = mfsdr(DCR_SDR0_SRST0); mtsdr(DCR_SDR0_SRST0, srst0 | SDR0_SRST0_UPRST | SDR0_SRST0_AHB); delay(200 * 1000); /* XXXX */ mtsdr(DCR_SDR0_SRST0, srst0); config_defer(self, dwctwo_plb_deferred); }
phys_size_t initdram(int board_type) { #if defined(CONFIG_NAND_SPL) u32 reg; /* don't reinit PLL when booting via I2C bootstrap option */ mfsdr(SDR_PINSTP, reg); if (reg != 0xf0000000) board_pll_init_f(); #endif #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) int i; u32 val; /* 1. EBC need to program READY, CLK, ADV for ASync mode */ gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); gpio_config(CONFIG_SYS_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); gpio_config(CONFIG_SYS_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG); /* 2. EBC in Async mode */ mtebc(pb1ap, 0x078F1EC0); mtebc(pb2ap, 0x078F1EC0); mtebc(pb1cr, 0x000BC000); mtebc(pb2cr, 0x020BC000); /* 3. Set CRAM in Sync mode */ cram_bcr_write(0x7012); /* CRAM burst setting */ /* 4. EBC in Sync mode */ mtebc(pb1ap, 0x9C0201C0); mtebc(pb2ap, 0x9C0201C0); /* Set GPIO pins back to alternate function */ gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG); gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG); /* Config EBC to use RDY */ mfsdr(sdrultra0, val); mtsdr(sdrultra0, val | SDR_ULTRA0_EBCRDYEN); /* Wait a short while, since for NAND booting this is too fast */ for (i=0; i<200000; i++) ; #endif return (CONFIG_SYS_MBYTES_RAM << 20); }
int misc_init_f (void) { uint reg; out16(FPGA_REG10, (in16(FPGA_REG10) & ~(FPGA_REG10_AUTO_NEG_DIS|FPGA_REG10_RESET_ETH)) | FPGA_REG10_10MHZ_ENABLE | FPGA_REG10_100MHZ_ENABLE | FPGA_REG10_GIGABIT_ENABLE | FPGA_REG10_FULL_DUPLEX ); udelay(10000); /* wait 10ms */ out16(FPGA_REG10, (in16(FPGA_REG10) | FPGA_REG10_RESET_ETH)); /* minimal init for PCIe */ /* pci express 0 Endpoint Mode */ mfsdr(SDRN_PESDR_DLPSET(0), reg); reg &= (~0x00400000); mtsdr(SDRN_PESDR_DLPSET(0), reg); /* pci express 1 Rootpoint Mode */ mfsdr(SDRN_PESDR_DLPSET(1), reg); reg |= 0x00400000; mtsdr(SDRN_PESDR_DLPSET(1), reg); /* pci express 2 Rootpoint Mode */ mfsdr(SDRN_PESDR_DLPSET(2), reg); reg |= 0x00400000; mtsdr(SDRN_PESDR_DLPSET(2), reg); out16(FPGA_REG1C,(in16 (FPGA_REG1C) & ~FPGA_REG1C_PE0_ROOTPOINT & ~FPGA_REG1C_PE1_ENDPOINT & ~FPGA_REG1C_PE2_ENDPOINT)); return 0; }
int board_early_init_f(void) { unsigned int reg; #if !defined(CONFIG_NAND_U_BOOT) /* don't reinit PLL when booting via I2C bootstrap option */ mfsdr(SDR_PINSTP, reg); if (reg != 0xf0000000) board_pll_init_f(); #endif acadia_gpio_init(); /* Configure 405EZ for NAND usage */ mtsdr(sdrnand0, SDR_NAND0_NDEN | SDR_NAND0_NDAREN | SDR_NAND0_NDRBEN); mfsdr(sdrultra0, reg); reg &= ~SDR_ULTRA0_CSN_MASK; reg |= (SDR_ULTRA0_CSNSEL0 >> CONFIG_SYS_NAND_CS) | SDR_ULTRA0_NDGPIOBP | SDR_ULTRA0_EBCRDYEN | SDR_ULTRA0_NFSRSTEN; mtsdr(sdrultra0, reg); /* USB Host core needs this bit set */ mfsdr(sdrultra1, reg); mtsdr(sdrultra1, reg | SDR_ULTRA1_LEDNENABLE); mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ mtdcr(uicer, 0x00000000); /* disable all ints */ mtdcr(uiccr, 0x00000010); mtdcr(uicpr, 0xFE7FFFF0); /* set int polarities */ mtdcr(uictr, 0x00000010); /* set int trigger levels */ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ return 0; }
int pci_pre_init(struct pci_controller * hose ) { unsigned long strap; /* See if we're supposed to setup the pci */ mfsdr(sdr_sdstp1, strap); if ((strap & 0x00010000) == 0) { return (0); } #if defined(CFG_PCI_FORCE_PCI_CONV) /* Setup System Device Register PCIX0_XCR */ mfsdr(sdr_xcr, strap); strap &= 0x0f000000; mtsdr(sdr_xcr, strap); #endif return 1; }
int pci_pre_init(struct pci_controller * hose) { unsigned long strap; /* See if we're supposed to setup the pci */ mfsdr(SDR0_SDSTP1, strap); if ((strap & 0x00010000) == 0) return 0; #if defined(CONFIG_SYS_PCI_FORCE_PCI_CONV) /* Setup System Device Register PCIL0_XCR */ mfsdr(SDR0_XCR, strap); strap &= 0x0f000000; mtsdr(SDR0_XCR, strap); #endif return 1; }
phys_size_t initdram(int board_type) { int i; u32 val; /* 1. EBC need to program READY, CLK, ADV for ASync mode */ gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); gpio_config(CONFIG_SYS_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); gpio_config(CONFIG_SYS_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG); /* 2. EBC in Async mode */ mtebc(PB1AP, 0x078F1EC0); mtebc(PB2AP, 0x078F1EC0); mtebc(PB1CR, 0x000BC000); mtebc(PB2CR, 0x020BC000); /* 3. Set CRAM in Sync mode */ cram_bcr_write(0x7012); /* CRAM burst setting */ /* 4. EBC in Sync mode */ mtebc(PB1AP, 0x9C0201C0); mtebc(PB2AP, 0x9C0201C0); /* Set GPIO pins back to alternate function */ gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG); gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG); /* Config EBC to use RDY */ mfsdr(SDR0_ULTRA0, val); mtsdr(SDR0_ULTRA0, val | SDR_ULTRA0_EBCRDYEN); /* Wait a short while, since for NAND booting this is too fast */ for (i=0; i<200000; i++) ; return (CONFIG_SYS_MBYTES_RAM << 20); }
int misc_init_r(void) { u32 pbcr; int size_val = 0; u32 reg; unsigned long usb2d0cr = 0; unsigned long usb2phy0cr, usb2h0cr = 0; unsigned long sdr0_pfc1, sdr0_srst; /* * FLASH stuff... */ /* Re-do sizing to get full correct info */ /* adjust flash start and offset */ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; gd->bd->bi_flashoffset = 0; mfebc(PB0CR, pbcr); size_val = ffs(gd->bd->bi_flashsize) - 21; pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); mtebc(PB0CR, pbcr); /* * Re-check to get correct base address */ flash_get_size(gd->bd->bi_flashstart, 0); /* Monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, -CONFIG_SYS_MONITOR_LEN, 0xffffffff, &flash_info[cfi_flash_num_flash_banks - 1]); /* Env protection ON by default */ flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, CONFIG_ENV_ADDR_REDUND + 2 * CONFIG_ENV_SECT_SIZE - 1, &flash_info[cfi_flash_num_flash_banks - 1]); /* * USB suff... */ /* Reset USB */ /* Reset of USB2PHY0 must be active at least 10 us */ mtsdr(SDR0_SRST0, SDR0_SRST0_USB2H | SDR0_SRST0_USB2D); udelay(2000); mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY | SDR0_SRST1_USB2HUTMI | SDR0_SRST1_USB2HPHY | SDR0_SRST1_OPBA2 | SDR0_SRST1_PLB42OPB1 | SDR0_SRST1_OPB2PLB40); udelay(2000); /* Errata CHIP_6 */ /* 1. Set internal PHY configuration */ /* SDR Setting */ mfsdr(SDR0_PFC1, sdr0_pfc1); mfsdr(SDR0_USB0, usb2d0cr); mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); mfsdr(SDR0_USB2H0CR, usb2h0cr); usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK; usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK; usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/ usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK; usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/ usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK; usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/ usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK; usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/ /* * An 8-bit/60MHz interface is the only possible alternative * when connecting the Device to the PHY */ usb2h0cr = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK; usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/ mtsdr(SDR0_PFC1, sdr0_pfc1); mtsdr(SDR0_USB0, usb2d0cr); mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); mtsdr(SDR0_USB2H0CR, usb2h0cr); /* 2. De-assert internal PHY reset */ mfsdr(SDR0_SRST1, sdr0_srst); sdr0_srst = sdr0_srst & ~SDR0_SRST1_USB20PHY; mtsdr(SDR0_SRST1, sdr0_srst); /* 3. Wait for more than 1 ms */ udelay(2000); /* 4. De-assert USB 2.0 Host main reset */ mfsdr(SDR0_SRST0, sdr0_srst); sdr0_srst = sdr0_srst &~ SDR0_SRST0_USB2H; mtsdr(SDR0_SRST0, sdr0_srst); udelay(1000); /* 5. De-assert reset of OPB2 cores */ mfsdr(SDR0_SRST1, sdr0_srst); sdr0_srst = sdr0_srst &~ SDR0_SRST1_PLB42OPB1; sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPB2PLB40; sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPBA2; mtsdr(SDR0_SRST1, sdr0_srst); udelay(1000); /* 6. Set EHCI Configure FLAG */ /* 7. Reassert internal PHY reset: */ mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY); udelay(1000); /* * Clear resets */ mtsdr(SDR0_SRST1, 0x00000000); mtsdr(SDR0_SRST0, 0x00000000); printf("USB: Host(int phy) Device(ext phy)\n"); /* * Clear PLB4A0_ACR[WRP] * This fix will make the MAL burst disabling patch for the Linux * EMAC driver obsolete. */ reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK; mtdcr(PLB4A0_ACR, reg); /* * Init matrix keyboard */ misc_init_r_kbd(); return 0; }
int board_early_init_f(void) { unsigned long sdrreg; /* TBS: Setup the GPIO access for the user LEDs */ mfsdr(sdr_pfc0, sdrreg); mtsdr(sdr_pfc0, (sdrreg & ~0x00000100) | 0x00000E00); out32(CFG_GPIO_BASE + 0x018, (USR_LED0 | USR_LED1 | USR_LED2 | USR_LED3)); LED0_OFF(); LED1_OFF(); LED2_OFF(); LED3_OFF(); /*-------------------------------------------------------------------- * Setup the external bus controller/chip selects *-------------------------------------------------------------------*/ /* set the bus controller */ mtebc (pb0ap, 0x04055200); /* FLASH/SRAM */ mtebc (pb0cr, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */ mtebc (pb1ap, 0x04055200); /* FLASH/SRAM */ mtebc (pb1cr, 0xfe098000); /* BAS=0xff8 16MB R/W 8-bit */ /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. *-------------------------------------------------------------------*/ mtdcr (uic0sr, 0xffffffff); /* clear all */ mtdcr (uic0er, 0x00000000); /* disable all */ mtdcr (uic0cr, 0x00000003); /* SMI & UIC1 crit are critical */ mtdcr (uic0pr, 0xfffffe00); /* per ref-board manual */ mtdcr (uic0tr, 0x01c00000); /* per ref-board manual */ mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr (uic0sr, 0xffffffff); /* clear all */ mtdcr (uic1sr, 0xffffffff); /* clear all */ mtdcr (uic1er, 0x00000000); /* disable all */ mtdcr (uic1cr, 0x00000000); /* all non-critical */ mtdcr (uic1pr, 0xffffc0ff); /* per ref-board manual */ mtdcr (uic1tr, 0x00ff8000); /* per ref-board manual */ mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr (uic1sr, 0xffffffff); /* clear all */ mtdcr (uic2sr, 0xffffffff); /* clear all */ mtdcr (uic2er, 0x00000000); /* disable all */ mtdcr (uic2cr, 0x00000000); /* all non-critical */ mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */ mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */ mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr (uic2sr, 0xffffffff); /* clear all */ mtdcr (uicb0sr, 0xfc000000); /* clear all */ mtdcr (uicb0er, 0x00000000); /* disable all */ mtdcr (uicb0cr, 0x00000000); /* all non-critical */ mtdcr (uicb0pr, 0xfc000000); /* */ mtdcr (uicb0tr, 0x00000000); /* */ mtdcr (uicb0vr, 0x00000001); /* */ LED0_ON(); return 0; }
void fpga_init(void) { unsigned long group; unsigned long sdr0_pfc0; unsigned long sdr0_pfc1; unsigned long sdr0_cust0; unsigned long pvr; mfsdr (SDR0_PFC0, sdr0_pfc0); mfsdr (SDR0_PFC1, sdr0_pfc1); group = SDR0_PFC1_EPS_DECODE(sdr0_pfc1); pvr = get_pvr (); sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_GEIE_MASK) | SDR0_PFC0_GEIE_TRE; if ( ((pvr == PVR_440GX_RA) || (pvr == PVR_440GX_RB)) && ((group == 4) || (group == 5))) { sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_DISABLE; sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS; out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) | FPGA_REG2_EXT_INTFACE_ENABLE); mtsdr (SDR0_PFC0, sdr0_pfc0); mtsdr (SDR0_PFC1, sdr0_pfc1); } else { sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_ENABLE; switch (group) { case 0: case 1: case 2: /* CPU trace A */ out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) | FPGA_REG2_EXT_INTFACE_ENABLE); sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS; mtsdr (SDR0_PFC0, sdr0_pfc0); mtsdr (SDR0_PFC1, sdr0_pfc1); break; case 3: case 4: case 5: case 6: /* CPU trace B - Over EBMI */ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_CPUTRACE; mtsdr (SDR0_PFC0, sdr0_pfc0); mtsdr (SDR0_PFC1, sdr0_pfc1); out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) | FPGA_REG2_EXT_INTFACE_DISABLE); break; } } /* Initialize the ethernet specific functions in the fpga */ mfsdr(SDR0_PFC1, sdr0_pfc1); mfsdr(SDR0_CUST0, sdr0_cust0); if ( (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) == 4) && ((SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) || (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_TBI))) { if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1) { out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) | FPGA_REG3_ENET_GROUP7); } else { if (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) { out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) | FPGA_REG3_ENET_GROUP7); } else { out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) | FPGA_REG3_ENET_GROUP8); } } } else { if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1) { out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) | FPGA_REG3_ENET_ENCODE1(SDR0_PFC1_EPS_DECODE(sdr0_pfc1))); } else { out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) | FPGA_REG3_ENET_ENCODE2(SDR0_PFC1_EPS_DECODE(sdr0_pfc1))); } } out8(FPGA_REG4, FPGA_REG4_GPHY_MODE10 | FPGA_REG4_GPHY_MODE100 | FPGA_REG4_GPHY_MODE1000 | FPGA_REG4_GPHY_FRC_DPLX | FPGA_REG4_CONNECT_PHYS); /* reset the gigabyte phy if necessary */ if (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) >= 3) { if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1) { out8(FPGA_REG3, in8(FPGA_REG3) & ~FPGA_REG3_GIGABIT_RESET_DISABLE); udelay(10000); out8(FPGA_REG3, in8(FPGA_REG3) | FPGA_REG3_GIGABIT_RESET_DISABLE); } else { out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_GIGABIT_RESET_DISABLE); udelay(10000); out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_GIGABIT_RESET_DISABLE); } } /* * new Ocotea with Rev. F (pass 3) chips has SMII PHY reset */ if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER2) { out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_SMII_RESET_DISABLE); udelay(10000); out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_SMII_RESET_DISABLE); } /* Turn off the LED's */ out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_STAT_MASK) | FPGA_REG3_STAT_LED8_DISAB | FPGA_REG3_STAT_LED4_DISAB | FPGA_REG3_STAT_LED2_DISAB | FPGA_REG3_STAT_LED1_DISAB); return; }
int board_early_init_f(void) { #ifdef BOOTSTRAP_OPTION_A_ACTIVE /* Booting with Bootstrap Option A * First boot, with CPR0_ICFG_RLI_MASK == 0 * no we setup varios boot strapping register, * then we do reset the PPC440 using a chip reset * Unfortunately, we cannot use this option, as Nto1 is not set * with Bootstrap Option A and cannot be changed later on by SW * There are no other possible boostrap options with a 8 bit ROM * See Errata (Version 1.04) CHIP_9 */ u32 cpr0icfg; u32 dbcr; mfcpr(CPR0_ICFG, cpr0icfg); if (!(cpr0icfg & CPR0_ICFG_RLI_MASK)) { mtcpr(CPR0_MALD, 0x02000000); mtcpr(CPR0_OPBD, 0x02000000); mtcpr(CPR0_PERD, 0x05000000); /* 1:5 */ mtcpr(CPR0_PLLC, 0x40000238); mtcpr(CPR0_PLLD, 0x01010414); mtcpr(CPR0_PRIMAD, 0x01000000); mtcpr(CPR0_PRIMBD, 0x01000000); mtcpr(CPR0_SPCID, 0x03000000); mtsdr(SDR0_PFC0, 0x00003E00); /* [CTE] = 0 */ mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/ mtcpr(CPR0_ICFG, cpr0icfg | CPR0_ICFG_RLI_MASK); /* * Initiate system reset in debug control register DBCR */ dbcr = mfspr(SPRN_DBCR0); mtspr(SPRN_DBCR0, dbcr | CHIP_RESET); } mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/ #endif mtdcr(EBC0_CFGADDR, EBC0_CFG); mtdcr(EBC0_CFGDATA, 0xb8400000); /* * Setup the GPIO pins */ out32(GPIO0_OR, 0x00000000); out32(GPIO0_TCR, 0x7C2FF1CF); out32(GPIO0_OSRL, 0x40055000); out32(GPIO0_OSRH, 0x00000000); out32(GPIO0_TSRL, 0x40055000); out32(GPIO0_TSRH, 0x00000400); out32(GPIO0_ISR1L, 0x40000000); out32(GPIO0_ISR1H, 0x00000000); out32(GPIO0_ISR2L, 0x00000000); out32(GPIO0_ISR2H, 0x00000000); out32(GPIO0_ISR3L, 0x00000000); out32(GPIO0_ISR3H, 0x00000000); out32(GPIO1_OR, 0x00000000); out32(GPIO1_TCR, 0xC6007FFF); out32(GPIO1_OSRL, 0x00140000); out32(GPIO1_OSRH, 0x00000000); out32(GPIO1_TSRL, 0x00000000); out32(GPIO1_TSRH, 0x00000000); out32(GPIO1_ISR1L, 0x05415555); out32(GPIO1_ISR1H, 0x40000000); out32(GPIO1_ISR2L, 0x00000000); out32(GPIO1_ISR2H, 0x00000000); out32(GPIO1_ISR3L, 0x00000000); out32(GPIO1_ISR3H, 0x00000000); /* * Setup the interrupt controller polarities, triggers, etc. */ mtdcr(UIC0SR, 0xffffffff); /* clear all */ mtdcr(UIC0ER, 0x00000000); /* disable all */ mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */ mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ mtdcr(UIC0SR, 0xffffffff); /* clear all */ mtdcr(UIC1SR, 0xffffffff); /* clear all */ mtdcr(UIC1ER, 0x00000000); /* disable all */ mtdcr(UIC1CR, 0x00000000); /* all non-critical */ mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ mtdcr(UIC1SR, 0xffffffff); /* clear all */ mtdcr(UIC2SR, 0xffffffff); /* clear all */ mtdcr(UIC2ER, 0x00000000); /* disable all */ mtdcr(UIC2CR, 0x00000000); /* all non-critical */ mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ mtdcr(UIC2SR, 0xffffffff); /* clear all */ mtsdr(SDR0_PFC0, 0x00003E00); /* Pin function: */ mtsdr(SDR0_PFC1, 0x00848000); /* Pin function: UART0 has 4 pins */ /* setup BOOT FLASH */ mtsdr(SDR0_CUST0, 0xC0082350); return 0; }
/* * Autodetect onboard DDR SDRAM on 440 platforms * * NOTE: Some of the hardcoded values are hardware dependant, * so this should be extended for other future boards * using this routine! */ phys_size_t initdram(int board_type) { int i; int tr1_bank1; #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \ defined(CONFIG_440GR) || defined(CONFIG_440SP) /* * Soft-reset SDRAM controller. */ mtsdr(SDR0_SRST, SDR0_SRST_DMC); mtsdr(SDR0_SRST, 0x00000000); #endif for (i=0; i<N_MB0CF; i++) { /* * Disable memory controller. */ mtsdram(SDRAM0_CFG0, 0x00000000); /* * Setup some default */ mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */ mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */ mtsdram(SDRAM0_WDDCTR, CONFIG_SYS_SDRAM0_WDDCTR); mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ /* * Following for CAS Latency = 2.5 @ 133 MHz PLB */ mtsdram(SDRAM0_B0CR, mb0cf[i].reg); mtsdram(SDRAM0_TR0, CONFIG_SYS_SDRAM0_TR0); mtsdram(SDRAM0_TR1, 0x80800800); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/ mtsdram(SDRAM0_RTR, CONFIG_SYS_SDRAM0_RTR); mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM*/ udelay(400); /* Delay 200 usecs (min) */ /* * Enable the controller, then wait for DCEN to complete */ mtsdram(SDRAM0_CFG0, CONFIG_SYS_SDRAM0_CFG0); udelay(10000); if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) { phys_size_t size = mb0cf[i].size; /* * Optimize TR1 to current hardware environment */ sdram_tr1_set(0x00000000, &tr1_bank1); mtsdram(SDRAM0_TR1, (tr1_bank1 | 0x80800800)); /* * OK, size detected. Enable second bank if * defined (assumes same type as bank 0) */ #ifdef CONFIG_SDRAM_BANK1 mtsdram(SDRAM0_CFG0, 0); mtsdram(SDRAM0_B1CR, mb0cf[i].size | mb0cf[i].reg); mtsdram(SDRAM0_CFG0, CONFIG_SYS_SDRAM0_CFG0); udelay(10000); /* * Check if 2nd bank is really available. * If the size not equal to the size of the first * bank, then disable the 2nd bank completely. */ if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size) != mb0cf[i].size) { mtsdram(SDRAM0_CFG0, 0); mtsdram(SDRAM0_B1CR, 0); mtsdram(SDRAM0_CFG0, CONFIG_SYS_SDRAM0_CFG0); udelay(10000); } else { /* * We have two identical banks, so the size * is twice the bank size */ size = 2 * size; } #endif #ifdef CONFIG_SDRAM_ECC ecc_init(0, size); #endif /* * OK, size detected -> all done */ return size; } } return 0; /* nothing found ! */ }
int board_early_init_f(void) { u32 sdr0_pfc1, sdr0_pfc2; u32 reg; /* PLB Write pipelining disabled. Denali Core workaround */ mtdcr(PLB4A0_ACR, 0xDE000000); mtdcr(PLB4A1_ACR, 0xDE000000); /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. *-------------------------------------------------------------------*/ mtdcr(UIC0SR, 0xffffffff); /* clear all. if write with 1 then the status is cleared */ mtdcr(UIC0ER, 0x00000000); /* disable all */ mtdcr(UIC0CR, 0x00000000); /* we have not critical interrupts at the moment */ mtdcr(UIC0PR, 0xFFBFF1EF); /* Adjustment of the polarity */ mtdcr(UIC0TR, 0x00000900); /* per ref-board manual */ mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ mtdcr(UIC0SR, 0xffffffff); /* clear all */ mtdcr(UIC1SR, 0xffffffff); /* clear all */ mtdcr(UIC1ER, 0x00000000); /* disable all */ mtdcr(UIC1CR, 0x00000000); /* all non-critical */ mtdcr(UIC1PR, 0xFFFFC6A5); /* Adjustment of the polarity */ mtdcr(UIC1TR, 0x60000040); /* per ref-board manual */ mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ mtdcr(UIC1SR, 0xffffffff); /* clear all */ mtdcr(UIC2SR, 0xffffffff); /* clear all */ mtdcr(UIC2ER, 0x00000000); /* disable all */ mtdcr(UIC2CR, 0x00000000); /* all non-critical */ mtdcr(UIC2PR, 0x27C00000); /* Adjustment of the polarity */ mtdcr(UIC2TR, 0x3C000000); /* per ref-board manual */ mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ mtdcr(UIC2SR, 0xffffffff); /* clear all */ /* Trace Pins are disabled. SDR0_PFC0 Register */ mtsdr(SDR0_PFC0, 0x0); /* select Ethernet pins */ mfsdr(SDR0_PFC1, sdr0_pfc1); /* SMII via ZMII */ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | SDR0_PFC1_SELECT_CONFIG_6; mfsdr(SDR0_PFC2, sdr0_pfc2); sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | SDR0_PFC2_SELECT_CONFIG_6; /* enable SPI (SCP) */ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL; mtsdr(SDR0_PFC2, sdr0_pfc2); mtsdr(SDR0_PFC1, sdr0_pfc1); mtsdr(SDR0_PFC4, 0x80000000); /* PCI arbiter disabled */ /* PCI Host Configuration disbaled */ mfsdr(SDR0_PCI0, reg); reg = 0; mtsdr(SDR0_PCI0, 0x00000000 | reg); gpio_write_bit(CONFIG_SYS_GPIO_FLASH_WP, 1); #if CONFIG_POST & CONFIG_SYS_POST_BSPEC1 /* enable the LSB transmitter */ gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1); /* enable the CAN transmitter */ gpio_write_bit(CONFIG_SYS_GPIO_CAN_ENABLE, 1); reg = 0; /* reuse as counter */ out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR, in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) & ~CONFIG_SYS_DSPIC_TEST_MASK); while (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) { udelay(1000); } if (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY)) { /* set "boot error" flag */ out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR, in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) | CONFIG_SYS_DSPIC_TEST_MASK); } #endif /* * Reset PHY's: * The PHY's need a 2nd reset pulse, since the MDIO address is latched * upon reset, and with the first reset upon powerup, the addresses are * not latched reliable, since the IRQ line is multiplexed with an * MDIO address. A 2nd reset at this time will make sure, that the * correct address is latched. */ gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1); gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1); udelay(1000); gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 0); gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 0); udelay(1000); gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1); gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1); return 0; }
/* * misc_init_r. */ int misc_init_r(void) { unsigned long usb2d0cr = 0; unsigned long usb2phy0cr, usb2h0cr = 0; unsigned long sdr0_pfc1; #ifdef CONFIG_ENV_IS_IN_FLASH /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, -CONFIG_SYS_MONITOR_LEN, 0xffffffff, &flash_info[0]); #ifdef CONFIG_ENV_ADDR_REDUND /* Env protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1, &flash_info[0]); #endif #endif /* * USB stuff... */ /* SDR Setting */ mfsdr(SDR0_PFC1, sdr0_pfc1); mfsdr(SDR0_USB2D0CR, usb2d0cr); mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); mfsdr(SDR0_USB2H0CR, usb2h0cr); usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/ /* An 8-bit/60MHz interface is the only possible alternative * when connecting the Device to the PHY */ usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/ /* To enable the USB 2.0 Device function through the UTMI interface */ usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1*/ sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/ mtsdr(SDR0_PFC1, sdr0_pfc1); mtsdr(SDR0_USB2D0CR, usb2d0cr); mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); mtsdr(SDR0_USB2H0CR, usb2h0cr); /*clear resets*/ udelay(1000); mtsdr(SDR0_SRST1, 0x00000000); udelay(1000); mtsdr(SDR0_SRST0, 0x00000000); printf("USB: Host(int phy) Device(ext phy)\n"); common_misc_init_r(); set_params_for_sw_install( sys_install_requested(), "hcu5" ); /* We cannot easily enable trace before, as there are other * routines messing around with sdr0_pfc1. And I do not need it. */ if (mfspr(SPRN_DBCR0) & 0x80000000) { /* External debugger alive * enable trace facilty for Lauterbach * CCR0[DTB]=0 Enable broadcast of trace information * SDR0_PFC0[TRE] Trace signals are enabled instead of * GPIO49-63 */ mtspr(SPRN_CCR0, mfspr(SPRN_CCR0) &~ (CCR0_DTB)); mtsdr(SDR0_PFC0, sdr0_pfc1 | SDR0_PFC0_TRE_ENABLE); } return 0; }
int board_early_init_f(void) { register uint reg; /*-------------------------------------------------------------------- * Setup the external bus controller/chip selects *-------------------------------------------------------------------*/ mtdcr(ebccfga, xbcfg); reg = mfdcr(ebccfgd); mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */ mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */ mtebc(pb0cr, 0xfe0ba000); /* BAS=0xfe0 32MB r/w 16-bit */ mtebc(pb1ap, 0x00000000); mtebc(pb1cr, 0x00000000); mtebc(pb2ap, 0x04814500); /*CPLD*/ mtebc(pb2cr, 0x80018000); /*BAS=0x800 1MB r/w 8-bit */ mtebc(pb3ap, 0x00000000); mtebc(pb3cr, 0x00000000); mtebc(pb4ap, 0x00000000); mtebc(pb4cr, 0x00000000); mtebc(pb5ap, 0x00000000); mtebc(pb5cr, 0x00000000); /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. *-------------------------------------------------------------------*/ mtdcr(uic0sr, 0xffffffff); /* clear all */ mtdcr(uic0er, 0x00000000); /* disable all */ mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */ mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */ mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */ mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr(uic0sr, 0xffffffff); /* clear all */ mtdcr(uic1sr, 0xffffffff); /* clear all */ mtdcr(uic1er, 0x00000000); /* disable all */ mtdcr(uic1cr, 0x00000000); /* all non-critical */ mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr(uic1sr, 0xffffffff); /* clear all */ /*-------------------------------------------------------------------- * Setup the GPIO pins *-------------------------------------------------------------------*/ /*CPLD cs */ /*setup Address lines for flash sizes larger than 16Meg. */ out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x40010000); out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40010000); out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x40000000); /*setup emac */ out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080); out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40); out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55); out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000); out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000); /*UART1 */ out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000); out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000); out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000); /*setup USB 2.0 */ out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000); out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000); out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf); out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa); out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500); /*-------------------------------------------------------------------- * Setup other serial configuration *-------------------------------------------------------------------*/ mfsdr(sdr_pci0, reg); mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */ mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */ mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */ /*clear tmrclk divisor */ *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00; /*enable ethernet */ *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0; /*enable usb 1.1 fs device and remove usb 2.0 reset */ *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00; /*get rid of flash write protect */ *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x40; return 0; }
int board_early_init_f (void) { /*----------------------------------------------------------------------------+ | Define Boot devices +----------------------------------------------------------------------------*/ #define BOOT_FROM_SMALL_FLASH 0x00 #define BOOT_FROM_LARGE_FLASH_OR_SRAM 0x01 #define BOOT_FROM_PCI 0x02 #define BOOT_DEVICE_UNKNOWN 0x03 /*----------------------------------------------------------------------------+ | EBC Devices Characteristics | Peripheral Bank Access Parameters - EBC_BxAP | Peripheral Bank Configuration Register - EBC_BxCR +----------------------------------------------------------------------------*/ /* * Small Flash and FRAM * BU Value * BxAP : 0x03800000 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000 * B0CR : 0xff098000 - BAS = ff0 - 100 11 00 0000000000000 * B2CR : 0xe7098000 - BAS = e70 - 100 11 00 0000000000000 */ #define EBC_BXAP_SMALL_FLASH EBC_BXAP_BME_DISABLED | \ EBC_BXAP_TWT_ENCODE(7) | \ EBC_BXAP_BCE_DISABLE | \ EBC_BXAP_BCT_2TRANS | \ EBC_BXAP_CSN_ENCODE(0) | \ EBC_BXAP_OEN_ENCODE(0) | \ EBC_BXAP_WBN_ENCODE(0) | \ EBC_BXAP_WBF_ENCODE(0) | \ EBC_BXAP_TH_ENCODE(0) | \ EBC_BXAP_RE_DISABLED | \ EBC_BXAP_SOR_DELAYED | \ EBC_BXAP_BEM_WRITEONLY | \ EBC_BXAP_PEN_DISABLED #define EBC_BXCR_SMALL_FLASH_CS0 EBC_BXCR_BAS_ENCODE(0xFF000000) | \ EBC_BXCR_BS_16MB | \ EBC_BXCR_BU_RW | \ EBC_BXCR_BW_8BIT #define EBC_BXCR_SMALL_FLASH_CS2 EBC_BXCR_BAS_ENCODE(0xe7000000) | \ EBC_BXCR_BS_16MB | \ EBC_BXCR_BU_RW | \ EBC_BXCR_BW_8BIT /* * Large Flash and SRAM * BU Value * BxAP : 0x048ff240 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000 * B0CR : 0xff09a000 - BAS = ff0 - 100 11 01 0000000000000 * B2CR : 0xe709a000 - BAS = e70 - 100 11 01 0000000000000 */ #define EBC_BXAP_LARGE_FLASH EBC_BXAP_BME_DISABLED | \ EBC_BXAP_TWT_ENCODE(7) | \ EBC_BXAP_BCE_DISABLE | \ EBC_BXAP_BCT_2TRANS | \ EBC_BXAP_CSN_ENCODE(0) | \ EBC_BXAP_OEN_ENCODE(0) | \ EBC_BXAP_WBN_ENCODE(0) | \ EBC_BXAP_WBF_ENCODE(0) | \ EBC_BXAP_TH_ENCODE(0) | \ EBC_BXAP_RE_DISABLED | \ EBC_BXAP_SOR_DELAYED | \ EBC_BXAP_BEM_WRITEONLY | \ EBC_BXAP_PEN_DISABLED #define EBC_BXCR_LARGE_FLASH_CS0 EBC_BXCR_BAS_ENCODE(0xFF000000) | \ EBC_BXCR_BS_16MB | \ EBC_BXCR_BU_RW | \ EBC_BXCR_BW_16BIT #define EBC_BXCR_LARGE_FLASH_CS2 EBC_BXCR_BAS_ENCODE(0xE7000000) | \ EBC_BXCR_BS_16MB | \ EBC_BXCR_BU_RW | \ EBC_BXCR_BW_16BIT /* * FPGA * BU value : * B1AP = 0x05895240 - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000 * B1CR = 0xe201a000 - BAS = e20 - 000 11 01 00000000000000 */ #define EBC_BXAP_FPGA EBC_BXAP_BME_DISABLED | \ EBC_BXAP_TWT_ENCODE(11) | \ EBC_BXAP_BCE_DISABLE | \ EBC_BXAP_BCT_2TRANS | \ EBC_BXAP_CSN_ENCODE(10) | \ EBC_BXAP_OEN_ENCODE(1) | \ EBC_BXAP_WBN_ENCODE(1) | \ EBC_BXAP_WBF_ENCODE(1) | \ EBC_BXAP_TH_ENCODE(1) | \ EBC_BXAP_RE_DISABLED | \ EBC_BXAP_SOR_DELAYED | \ EBC_BXAP_BEM_RW | \ EBC_BXAP_PEN_DISABLED #define EBC_BXCR_FPGA_CS1 EBC_BXCR_BAS_ENCODE(0xe2000000) | \ EBC_BXCR_BS_1MB | \ EBC_BXCR_BU_RW | \ EBC_BXCR_BW_16BIT unsigned long mfr; /* * Define Variables for EBC initialization depending on BOOTSTRAP option */ unsigned long sdr0_pinstp, sdr0_sdstp1 ; unsigned long bootstrap_settings, ebc_data_width, boot_selection; int computed_boot_device = BOOT_DEVICE_UNKNOWN; /*-------------------------------------------------------------------+ | Initialize EBC CONFIG - | Keep the Default value, but the bit PDT which has to be set to 1 ?TBC | default value : | 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000 | +-------------------------------------------------------------------*/ mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_16PERCLK | EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS | EBC_CFG_OEO_PREVIOUS | EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE | EBC_CFG_PR_16); /*-------------------------------------------------------------------+ | | PART 1 : Initialize EBC Bank 1 | ============================== | Bank1 is always associated to the EPLD. | It has to be initialized prior to other banks settings computation | since some board registers values may be needed to determine the | boot type | +-------------------------------------------------------------------*/ mtebc(PB1AP, EBC_BXAP_FPGA); mtebc(PB1CR, EBC_BXCR_FPGA_CS1); /*-------------------------------------------------------------------+ | | PART 2 : Determine which boot device was selected | ================================================= | | Read Pin Strap Register in PPC440SPe | Result can either be : | - Boot strap = boot from EBC 8bits => Small Flash | - Boot strap = boot from PCI | - Boot strap = IIC | In case of boot from IIC, read Serial Device Strap Register1 | | Result can either be : | - Boot from EBC - EBC Bus Width = 8bits => Small Flash | - Boot from EBC - EBC Bus Width = 16bits => Large Flash or SRAM | - Boot from PCI | +-------------------------------------------------------------------*/ /* Read Pin Strap Register in PPC440SP */ mfsdr(SDR0_PINSTP, sdr0_pinstp); bootstrap_settings = sdr0_pinstp & SDR0_PINSTP_BOOTSTRAP_MASK; switch (bootstrap_settings) { case SDR0_PINSTP_BOOTSTRAP_SETTINGS0: /* * Strapping Option A * Boot from EBC - 8 bits , Small Flash */ computed_boot_device = BOOT_FROM_SMALL_FLASH; break; case SDR0_PINSTP_BOOTSTRAP_SETTINGS1: /* * Strappping Option B * Boot from PCI */ computed_boot_device = BOOT_FROM_PCI; break; case SDR0_PINSTP_BOOTSTRAP_IIC_50_EN: case SDR0_PINSTP_BOOTSTRAP_IIC_54_EN: /* * Strapping Option C or D * Boot Settings in IIC EEprom address 0x50 or 0x54 * Read Serial Device Strap Register1 in PPC440SPe */ mfsdr(SDR0_SDSTP1, sdr0_sdstp1); boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_ERPN_MASK; ebc_data_width = sdr0_sdstp1 & SDR0_SDSTP1_EBCW_MASK; switch (boot_selection) { case SDR0_SDSTP1_ERPN_EBC: switch (ebc_data_width) { case SDR0_SDSTP1_EBCW_16_BITS: computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM; break; case SDR0_SDSTP1_EBCW_8_BITS : computed_boot_device = BOOT_FROM_SMALL_FLASH; break; } break; case SDR0_SDSTP1_ERPN_PCI: computed_boot_device = BOOT_FROM_PCI; break; default: /* should not occure */ computed_boot_device = BOOT_DEVICE_UNKNOWN; } break; default: /* should not be */ computed_boot_device = BOOT_DEVICE_UNKNOWN; break; } /*-------------------------------------------------------------------+ | | PART 3 : Compute EBC settings depending on selected boot device | ====== ====================================================== | | Resulting EBC init will be among following configurations : | | - Boot from EBC 8bits => boot from Small Flash selected | EBC-CS0 = Small Flash | EBC-CS2 = Large Flash and SRAM | | - Boot from EBC 16bits => boot from Large Flash or SRAM | EBC-CS0 = Large Flash or SRAM | EBC-CS2 = Small Flash | | - Boot from PCI | EBC-CS0 = not initialized to avoid address contention | EBC-CS2 = same as boot from Small Flash selected | +-------------------------------------------------------------------*/ unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0; unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0; switch (computed_boot_device) { /*-------------------------------------------------------------------*/ case BOOT_FROM_PCI: /*-------------------------------------------------------------------*/ /* * By Default CS2 is affected to LARGE Flash * do not initialize SMALL FLASH to avoid address contention * Large Flash */ ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH; ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2; break; /*-------------------------------------------------------------------*/ case BOOT_FROM_SMALL_FLASH: /*-------------------------------------------------------------------*/ ebc0_cs0_bxap_value = EBC_BXAP_SMALL_FLASH; ebc0_cs0_bxcr_value = EBC_BXCR_SMALL_FLASH_CS0; /* * Large Flash or SRAM */ /* ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH; */ ebc0_cs2_bxap_value = 0x048ff240; ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2; break; /*-------------------------------------------------------------------*/ case BOOT_FROM_LARGE_FLASH_OR_SRAM: /*-------------------------------------------------------------------*/ ebc0_cs0_bxap_value = EBC_BXAP_LARGE_FLASH; ebc0_cs0_bxcr_value = EBC_BXCR_LARGE_FLASH_CS0; /* Small flash */ ebc0_cs2_bxap_value = EBC_BXAP_SMALL_FLASH; ebc0_cs2_bxcr_value = EBC_BXCR_SMALL_FLASH_CS2; break; /*-------------------------------------------------------------------*/ default: /*-------------------------------------------------------------------*/ /* BOOT_DEVICE_UNKNOWN */ break; } mtebc(PB0AP, ebc0_cs0_bxap_value); mtebc(PB0CR, ebc0_cs0_bxcr_value); mtebc(PB2AP, ebc0_cs2_bxap_value); mtebc(PB2CR, ebc0_cs2_bxcr_value); /*--------------------------------------------------------------------+ | Interrupt controller setup for the AMCC 440SPe Evaluation board. +--------------------------------------------------------------------+ +---------------------------------------------------------------------+ |Interrupt| Source | Pol. | Sensi.| Crit. | +---------+-----------------------------------+-------+-------+-------+ | IRQ 00 | UART0 | High | Level | Non | | IRQ 01 | UART1 | High | Level | Non | | IRQ 02 | IIC0 | High | Level | Non | | IRQ 03 | IIC1 | High | Level | Non | | IRQ 04 | PCI0X0 MSG IN | High | Level | Non | | IRQ 05 | PCI0X0 CMD Write | High | Level | Non | | IRQ 06 | PCI0X0 Power Mgt | High | Level | Non | | IRQ 07 | PCI0X0 VPD Access | Rising| Edge | Non | | IRQ 08 | PCI0X0 MSI level 0 | High | Lvl/ed| Non | | IRQ 09 | External IRQ 15 - (PCI-Express) | pgm H | Pgm | Non | | IRQ 10 | UIC2 Non-critical Int. | NA | NA | Non | | IRQ 11 | UIC2 Critical Interrupt | NA | NA | Crit | | IRQ 12 | PCI Express MSI Level 0 | Rising| Edge | Non | | IRQ 13 | PCI Express MSI Level 1 | Rising| Edge | Non | | IRQ 14 | PCI Express MSI Level 2 | Rising| Edge | Non | | IRQ 15 | PCI Express MSI Level 3 | Rising| Edge | Non | | IRQ 16 | UIC3 Non-critical Int. | NA | NA | Non | | IRQ 17 | UIC3 Critical Interrupt | NA | NA | Crit | | IRQ 18 | External IRQ 14 - (PCI-Express) | Pgm | Pgm | Non | | IRQ 19 | DMA Channel 0 FIFO Full | High | Level | Non | | IRQ 20 | DMA Channel 0 Stat FIFO | High | Level | Non | | IRQ 21 | DMA Channel 1 FIFO Full | High | Level | Non | | IRQ 22 | DMA Channel 1 Stat FIFO | High | Level | Non | | IRQ 23 | I2O Inbound Doorbell | High | Level | Non | | IRQ 24 | Inbound Post List FIFO Not Empt | High | Level | Non | | IRQ 25 | I2O Region 0 LL PLB Write | High | Level | Non | | IRQ 26 | I2O Region 1 LL PLB Write | High | Level | Non | | IRQ 27 | I2O Region 0 HB PLB Write | High | Level | Non | | IRQ 28 | I2O Region 1 HB PLB Write | High | Level | Non | | IRQ 29 | GPT Down Count Timer | Rising| Edge | Non | | IRQ 30 | UIC1 Non-critical Int. | NA | NA | Non | | IRQ 31 | UIC1 Critical Interrupt | NA | NA | Crit. | |---------------------------------------------------------------------- | IRQ 32 | Ext. IRQ 13 - (PCI-Express) |pgm (H)|pgm/Lvl| Non | | IRQ 33 | MAL Serr | High | Level | Non | | IRQ 34 | MAL Txde | High | Level | Non | | IRQ 35 | MAL Rxde | High | Level | Non | | IRQ 36 | DMC CE or DMC UE | High | Level | Non | | IRQ 37 | EBC or UART2 | High |Lvl Edg| Non | | IRQ 38 | MAL TX EOB | High | Level | Non | | IRQ 39 | MAL RX EOB | High | Level | Non | | IRQ 40 | PCIX0 MSI Level 1 | High |Lvl Edg| Non | | IRQ 41 | PCIX0 MSI level 2 | High |Lvl Edg| Non | | IRQ 42 | PCIX0 MSI level 3 | High |Lvl Edg| Non | | IRQ 43 | L2 Cache | Risin | Edge | Non | | IRQ 44 | GPT Compare Timer 0 | Risin | Edge | Non | | IRQ 45 | GPT Compare Timer 1 | Risin | Edge | Non | | IRQ 46 | GPT Compare Timer 2 | Risin | Edge | Non | | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non | | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non | | IRQ 49 | Ext. IRQ 12 - PCI-X |pgm/Fal|pgm/Lvl| Non | | IRQ 50 | Ext. IRQ 11 - |pgm (H)|pgm/Lvl| Non | | IRQ 51 | Ext. IRQ 10 - |pgm (H)|pgm/Lvl| Non | | IRQ 52 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non | | IRQ 53 | Ext. IRQ 8 |pgm (H)|pgm/Lvl| Non | | IRQ 54 | DMA Error | High | Level | Non | | IRQ 55 | DMA I2O Error | High | Level | Non | | IRQ 56 | Serial ROM | High | Level | Non | | IRQ 57 | PCIX0 Error | High | Edge | Non | | IRQ 58 | Ext. IRQ 7- |pgm (H)|pgm/Lvl| Non | | IRQ 59 | Ext. IRQ 6- |pgm (H)|pgm/Lvl| Non | | IRQ 60 | EMAC0 Interrupt | High | Level | Non | | IRQ 61 | EMAC0 Wake-up | High | Level | Non | | IRQ 62 | Reserved | High | Level | Non | | IRQ 63 | XOR | High | Level | Non | |---------------------------------------------------------------------- | IRQ 64 | PE0 AL | High | Level | Non | | IRQ 65 | PE0 VPD Access | Risin | Edge | Non | | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non | | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non | | IRQ 68 | PE0 TCR | High | Level | Non | | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non | | IRQ 70 | PE0 DCR Error | High | Level | Non | | IRQ 71 | Reserved | N/A | N/A | Non | | IRQ 72 | PE1 AL | High | Level | Non | | IRQ 73 | PE1 VPD Access | Risin | Edge | Non | | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non | | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non | | IRQ 76 | PE1 TCR | High | Level | Non | | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non | | IRQ 78 | PE1 DCR Error | High | Level | Non | | IRQ 79 | Reserved | N/A | N/A | Non | | IRQ 80 | PE2 AL | High | Level | Non | | IRQ 81 | PE2 VPD Access | Risin | Edge | Non | | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non | | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non | | IRQ 84 | PE2 TCR | High | Level | Non | | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non | | IRQ 86 | PE2 DCR Error | High | Level | Non | | IRQ 87 | Reserved | N/A | N/A | Non | | IRQ 88 | External IRQ(5) | Progr | Progr | Non | | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non | | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non | | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non | | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non | | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non | | IRQ 94 | Reserved | N/A | N/A | Non | | IRQ 95 | Reserved | N/A | N/A | Non | |--------------------------------------------------------------------- | IRQ 96 | PE0 INTA | High | Level | Non | | IRQ 97 | PE0 INTB | High | Level | Non | | IRQ 98 | PE0 INTC | High | Level | Non | | IRQ 99 | PE0 INTD | High | Level | Non | | IRQ 100 | PE1 INTA | High | Level | Non | | IRQ 101 | PE1 INTB | High | Level | Non | | IRQ 102 | PE1 INTC | High | Level | Non | | IRQ 103 | PE1 INTD | High | Level | Non | | IRQ 104 | PE2 INTA | High | Level | Non | | IRQ 105 | PE2 INTB | High | Level | Non | | IRQ 106 | PE2 INTC | High | Level | Non | | IRQ 107 | PE2 INTD | Risin | Edge | Non | | IRQ 108 | PCI Express MSI Level 4 | Risin | Edge | Non | | IRQ 109 | PCI Express MSI Level 5 | Risin | Edge | Non | | IRQ 110 | PCI Express MSI Level 6 | Risin | Edge | Non | | IRQ 111 | PCI Express MSI Level 7 | Risin | Edge | Non | | IRQ 116 | PCI Express MSI Level 12 | Risin | Edge | Non | | IRQ 112 | PCI Express MSI Level 8 | Risin | Edge | Non | | IRQ 113 | PCI Express MSI Level 9 | Risin | Edge | Non | | IRQ 114 | PCI Express MSI Level 10 | Risin | Edge | Non | | IRQ 115 | PCI Express MSI Level 11 | Risin | Edge | Non | | IRQ 117 | PCI Express MSI Level 13 | Risin | Edge | Non | | IRQ 118 | PCI Express MSI Level 14 | Risin | Edge | Non | | IRQ 119 | PCI Express MSI Level 15 | Risin | Edge | Non | | IRQ 120 | PCI Express MSI Level 16 | Risin | Edge | Non | | IRQ 121 | PCI Express MSI Level 17 | Risin | Edge | Non | | IRQ 122 | PCI Express MSI Level 18 | Risin | Edge | Non | | IRQ 123 | PCI Express MSI Level 19 | Risin | Edge | Non | | IRQ 124 | PCI Express MSI Level 20 | Risin | Edge | Non | | IRQ 125 | PCI Express MSI Level 21 | Risin | Edge | Non | | IRQ 126 | PCI Express MSI Level 22 | Risin | Edge | Non | | IRQ 127 | PCI Express MSI Level 23 | Risin | Edge | Non | +---------+-----------------------------------+-------+-------+------*/ /*--------------------------------------------------------------------+ | Put UICs in PowerPC440SPemode. | Initialise UIC registers. Clear all interrupts. Disable all | interrupts. | Set critical interrupt values. Set interrupt polarities. Set | interrupt trigger levels. Make bit 0 High priority. Clear all | interrupts again. +-------------------------------------------------------------------*/ mtdcr (UIC3SR, 0xffffffff); /* Clear all interrupts */ mtdcr (UIC3ER, 0x00000000); /* disable all interrupts */ mtdcr (UIC3CR, 0x00000000); /* Set Critical / Non Critical * interrupts */ mtdcr (UIC3PR, 0xffffffff); /* Set Interrupt Polarities */ mtdcr (UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */ mtdcr (UIC3VR, 0x00000001); /* Set Vect base=0,INT31 Highest * priority */ mtdcr (UIC3SR, 0x00000000); /* clear all interrupts */ mtdcr (UIC3SR, 0xffffffff); /* clear all interrupts */ mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */ mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */ mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical * interrupts */ mtdcr (UIC2PR, 0xebebebff); /* Set Interrupt Polarities */ mtdcr (UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */ mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest * priority */ mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */ mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */ mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */ mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */ mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical * interrupts */ mtdcr (UIC1PR, 0xffffffff); /* Set Interrupt Polarities */ mtdcr (UIC1TR, 0x001f8040); /* Set Interrupt Trigger Levels */ mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest * priority */ mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */ mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */ mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */ mtdcr (UIC0ER, 0x00000000); /* disable all interrupts excepted * cascade to be checked */ mtdcr (UIC0CR, 0x00104001); /* Set Critical / Non Critical * interrupts */ mtdcr (UIC0PR, 0xffffffff); /* Set Interrupt Polarities */ mtdcr (UIC0TR, 0x010f0004); /* Set Interrupt Trigger Levels */ mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest * priority */ mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */ mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */ mfsdr(SDR0_MFR, mfr); mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ mtsdr(SDR0_MFR, mfr); fpga_init(); return 0; }
void pcie_setup_hoses(int busno) { struct pci_controller *hose; int i, bus; char *env; unsigned int delay; /* * assume we're called after the PCIX hose is initialized, which takes * bus ID 0 and therefore start numbering PCIe's from 1. */ bus = busno; for (i = 0; i <= 2; i++) { /* Check for yucca card presence */ if (!yucca_pcie_card_present(i)) continue; #ifdef PCIE_ENDPOINT yucca_setup_pcie_fpga_endpoint(i); if (ppc440spe_init_pcie_endport(i)) { #else yucca_setup_pcie_fpga_rootpoint(i); if (ppc440spe_init_pcie_rootport(i)) { #endif printf("PCIE%d: initialization failed\n", i); continue; } hose = &pcie_hose[i]; hose->first_busno = bus; hose->last_busno = bus; hose->current_busno = bus; /* setup mem resource */ pci_set_region(hose->regions + 0, CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, CFG_PCIE_MEMSIZE, PCI_REGION_MEM ); hose->region_count = 1; pci_register_hose(hose); #ifdef PCIE_ENDPOINT ppc440spe_setup_pcie_endpoint(hose, i); /* * Reson for no scanning is endpoint can not generate * upstream configuration accesses. */ #else ppc440spe_setup_pcie_rootpoint(hose, i); env = getenv ("pciscandelay"); if (env != NULL) { delay = simple_strtoul (env, NULL, 10); if (delay > 5) printf ("Warning, expect noticable delay before PCIe" "scan due to 'pciscandelay' value!\n"); mdelay (delay * 1000); } /* * Config access can only go down stream */ hose->last_busno = pci_hose_scan(hose); bus = hose->last_busno + 1; #endif } } #endif /* defined(CONFIG_PCI) */ int misc_init_f (void) { uint reg; #if defined(CONFIG_STRESS) uint i ; uint disp; #endif out16(FPGA_REG10, (in16(FPGA_REG10) & ~(FPGA_REG10_AUTO_NEG_DIS|FPGA_REG10_RESET_ETH)) | FPGA_REG10_10MHZ_ENABLE | FPGA_REG10_100MHZ_ENABLE | FPGA_REG10_GIGABIT_ENABLE | FPGA_REG10_FULL_DUPLEX ); udelay(10000); /* wait 10ms */ out16(FPGA_REG10, (in16(FPGA_REG10) | FPGA_REG10_RESET_ETH)); /* minimal init for PCIe */ /* pci express 0 Endpoint Mode */ mfsdr(SDR0_PE0DLPSET, reg); reg &= (~0x00400000); mtsdr(SDR0_PE0DLPSET, reg); /* pci express 1 Rootpoint Mode */ mfsdr(SDR0_PE1DLPSET, reg); reg |= 0x00400000; mtsdr(SDR0_PE1DLPSET, reg); /* pci express 2 Rootpoint Mode */ mfsdr(SDR0_PE2DLPSET, reg); reg |= 0x00400000; mtsdr(SDR0_PE2DLPSET, reg); out16(FPGA_REG1C,(in16 (FPGA_REG1C) & ~FPGA_REG1C_PE0_ROOTPOINT & ~FPGA_REG1C_PE1_ENDPOINT & ~FPGA_REG1C_PE2_ENDPOINT)); #if defined(CONFIG_STRESS) /* * all this setting done by linux only needed by stress an charac. test * procedure * PCIe 1 Rootpoint PCIe2 Endpoint * PCIe 0 FIR Pre-emphasis Filter Coefficients & Transmit Driver * Power Level */ for (i = 0, disp = 0; i < 8; i++, disp += 3) { mfsdr(SDR0_PE0HSSSET1L0 + disp, reg); reg |= 0x33000000; mtsdr(SDR0_PE0HSSSET1L0 + disp, reg); } /* * PCIe 1 FIR Pre-emphasis Filter Coefficients & Transmit Driver * Power Level */ for (i = 0, disp = 0; i < 4; i++, disp += 3) { mfsdr(SDR0_PE1HSSSET1L0 + disp, reg); reg |= 0x33000000; mtsdr(SDR0_PE1HSSSET1L0 + disp, reg); } /* * PCIE 2 FIR Pre-emphasis Filter Coefficients & Transmit Driver * Power Level */ for (i = 0, disp = 0; i < 4; i++, disp += 3) { mfsdr(SDR0_PE2HSSSET1L0 + disp, reg); reg |= 0x33000000; mtsdr(SDR0_PE2HSSSET1L0 + disp, reg); } reg = 0x21242222; mtsdr(SDR0_PE2UTLSET1, reg); reg = 0x11000000; mtsdr(SDR0_PE2UTLSET2, reg); /* pci express 1 Endpoint Mode */ reg = 0x00004000; mtsdr(SDR0_PE2DLPSET, reg); mtsdr(SDR0_UART1, 0x2080005a); /* patch for TG */ #endif return 0; }