int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
return 0;
}
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
/*
* The KM_FLASH_GPIO_PIN switches between using a
* NAND or a SPI FLASH. Set this pin on start
* to NAND mode.
*/
kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
#if defined(CONFIG_SYS_I2C_SOFT)
/*
* Reinit the GPIO for I2C Bitbang driver so that the now
* available gpio framework is consistent. The calls to
* direction output in are not necessary, they are already done in
* board_early_init_f
*/
kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);
kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1);
#endif
#if defined(CONFIG_SYS_EEPROM_WREN)
kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38);
kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1);
#endif
#if defined(CONFIG_KM_FPGA_CONFIG)
trigger_fpga_config();
#endif
return 0;
}
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
set_led(LED_POWER_BLINKING);
return 0;
}
int board_init(void)
{
/*
* arch number of board
*/
gd->bd->bi_arch_number = MACH_TYPE_SHEEVAPLUG;
/* adress of boot parameters */
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
return 0;
}
int board_init(void)
{
int i;
/* adress of boot parameters */
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
/* Init I2C IO expanders */
for (i = 0; i < ARRAY_SIZE(io_exp); i++)
i2c_write(io_exp[i].chip, io_exp[i].addr, 1, &io_exp[i].val, 1);
return 0;
}
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
/* window for NVS */
mbus_dt_setup_win(&mbus_state, CONFIG_NVS_LOCATION, CONFIG_NVS_SIZE,
CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS1);
/* DEV_READYn is not needed for NVS, ignore it when accessing CS1 */
writel(0x00004001, MVEBU_DEV_BUS_BASE + 0xc8);
return 0;
}
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
/*
* Map SPI devices via MBUS so that they can be accessed via
* the SPI direct access mode
*/
mbus_dt_setup_win(&mbus_state, SPI_BUS0_DEV1_BASE, SPI_BUS0_DEV1_SIZE,
CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI0_CS1);
mbus_dt_setup_win(&mbus_state, SPI_BUS1_DEV2_BASE, SPI_BUS0_DEV1_SIZE,
CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI1_CS2);
return 0;
}
int board_init(void)
{
int ret;
/* adress of boot parameters */
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
/*
* Map SPI devices via MBUS so that they can be accessed via
* the SPI direct access mode
*/
mbus_dt_setup_win(&mbus_state, SPI_BUS0_DEV1_BASE, SPI_BUS0_DEV1_SIZE,
CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI0_CS1);
mbus_dt_setup_win(&mbus_state, SPI_BUS1_DEV2_BASE, SPI_BUS0_DEV1_SIZE,
CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI1_CS2);
/*
* Set RX Channel Control 0 Register:
* Tests have shown, that setting the LPF_COEF from 0 (1/8)
* to 3 (1/1) results in a more stable USB connection.
*/
setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 1), 0xc);
setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 2), 0xc);
setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 3), 0xc);
/* Toggle USB power */
ret = gpio_request(GPIO_USB0_PWR_ON, "USB0_PWR_ON");
if (ret < 0)
return ret;
gpio_direction_output(GPIO_USB0_PWR_ON, 0);
ret = gpio_request(GPIO_USB1_PWR_ON, "USB1_PWR_ON");
if (ret < 0)
return ret;
gpio_direction_output(GPIO_USB1_PWR_ON, 0);
mdelay(1);
gpio_set_value(GPIO_USB0_PWR_ON, 1);
gpio_set_value(GPIO_USB1_PWR_ON, 1);
return 0;
}
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
#ifndef CONFIG_SPL_BUILD
# ifdef CONFIG_WDT_ORION
if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
puts("Cannot find Armada 385 watchdog!\n");
} else {
puts("Enabling Armada 385 watchdog.\n");
wdt_start(watchdog_dev, (u32) 25000000 * 120, 0);
}
# endif
if (disable_mcu_watchdog())
puts("Disabled MCU startup watchdog.\n");
set_regdomain();
#endif
return 0;
}
int board_init(void)
{
int i;
/* Address of boot parameters */
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
/* Toggle GPIO41 to reset onboard switch and phy */
clrbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
clrbits_le32(MVEBU_GPIO1_BASE + 0x4, BIT(9));
/* GPIO 19 on ClearFog rev 2.1 controls the uSOM onboard phy reset */
clrbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
clrbits_le32(MVEBU_GPIO0_BASE + 0x4, BIT(19));
mdelay(1);
setbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
setbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
mdelay(10);
/* Init I2C IO expanders */
for (i = 0; i < ARRAY_SIZE(io_exp); i++)
i2c_write(io_exp[i].chip, io_exp[i].addr, 1, &io_exp[i].val, 1);
return 0;
}
