void si4702_reset(void)
{
mxc_set_gpio_dataout(MX31_PIN_SRST0, 0);
msleep(100);
mxc_set_gpio_dataout(MX31_PIN_SRST0, 1);
msleep(100);
}
void si4702_reset(void)
{
mxc_set_gpio_dataout(MX51_PIN_EIM_DTACK, 0);
msleep(100);
mxc_set_gpio_dataout(MX51_PIN_EIM_DTACK, 1);
msleep(100);
}
/*!
* Setup GPIO for an I2C device to be active
*
* @param i2c_num an I2C device
*/
void gpio_i2c_active(int i2c_num)
{
iomux_pad_config_t regval = 0;
switch (i2c_num) {
case 0:
/* fuel gauge and rtc */
mxc_request_iomux(MX37_PIN_I2C1_CLK, IOMUX_CONFIG_ALT4);
mxc_set_gpio_direction(MX37_PIN_I2C1_CLK, 0);
mxc_set_gpio_dataout(MX37_PIN_I2C1_CLK, 0);
mxc_request_iomux(MX37_PIN_I2C1_DAT, IOMUX_CONFIG_ALT4);
mxc_set_gpio_direction(MX37_PIN_I2C1_DAT, 0);
mxc_set_gpio_dataout(MX37_PIN_I2C1_DAT, 0);
/* select I2C1_SCK as daisy chain input */
mxc_request_iomux(MX37_PIN_I2C1_CLK, IOMUX_CONFIG_ALT0);
mxc_iomux_set_input(MUX_IN_I2C1_SCL, INPUT_CTL_PATH1);
/* OpenDrain enabled, 100k PU enabled */
regval =
PAD_CTL_ODE_OPENDRAIN_ENABLE | PAD_CTL_100K_PU |
PAD_CTL_PKE_ENABLE;
mxc_iomux_set_pad(MX37_PIN_I2C1_CLK, regval);
/*select I2C1_SDA as daisy chain input */
mxc_request_iomux(MX37_PIN_I2C1_DAT, IOMUX_CONFIG_ALT0);
mxc_iomux_set_input(MUX_IN_I2C1_SDA, INPUT_CTL_PATH1);
mxc_iomux_set_pad(MX37_PIN_I2C1_DAT, regval);
mxc_iomux_set_pad(MX37_PIN_GRP_H3, PAD_CTL_HYS_ENABLE);
break;
case 1:
mxc_request_iomux(MX37_PIN_GPIO1_0, IOMUX_CONFIG_ALT0);
mxc_set_gpio_direction(MX37_PIN_GPIO1_0, 0);
mxc_set_gpio_dataout(MX37_PIN_GPIO1_0, 0);
mxc_request_iomux(MX37_PIN_GPIO1_1, IOMUX_CONFIG_ALT0);
mxc_set_gpio_direction(MX37_PIN_GPIO1_1, 0);
mxc_set_gpio_dataout(MX37_PIN_GPIO1_1, 0);
/*select I2C2_SCL as daisy chain input */
mxc_iomux_set_input(MUX_IN_I2C2_SCL, INPUT_CTL_PATH1);
regval = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
PAD_CTL_PUE_PULL | PAD_CTL_100K_PU |
PAD_CTL_ODE_OPENDRAIN_ENABLE | PAD_CTL_DRV_HIGH;
mxc_iomux_set_pad(MX37_PIN_GPIO1_0, regval);
mxc_request_iomux(MX37_PIN_GPIO1_0,
(IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT2));
/*select I2C2_SDA as daisy chain input */
mxc_iomux_set_input(MUX_IN_I2C2_SDA, INPUT_CTL_PATH1);
mxc_iomux_set_pad(MX37_PIN_GPIO1_1, regval);
mxc_request_iomux(MX37_PIN_GPIO1_1,
(IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT2));
break;
case 2:
break;
default:
break;
}
}
static void lcd_reset(void)
{
mxc_set_gpio_dataout(MX51_PIN_DISPB2_SER_RS, 0);
mxc_set_gpio_direction(MX51_PIN_DISPB2_SER_RS, 0);
/* do reset */
msleep(10); /* tRES >= 100us */
mxc_set_gpio_dataout(MX51_PIN_DISPB2_SER_RS, 1);
msleep(60);
}
void mxc_wifi_hardreset(struct work_struct* work)
{
mxc_request_iomux(MX31_PIN_DCD_DCE1, OUTPUTCONFIG_GPIO,
INPUTCONFIG_NONE);
mxc_set_gpio_direction(MX31_PIN_DCD_DCE1, 0);
mxc_set_gpio_dataout(MX31_PIN_DCD_DCE1, 0);
msleep(1);
mxc_set_gpio_dataout(MX31_PIN_DCD_DCE1, 1);
}
int gpio_gps_access(int para)
{
iomux_pin_name_t pin;
pin = (para & 0x1) ? MX51_PIN_EIM_CS2 : MX51_PIN_EIM_CRE;
if (para & 0x4) /* Read GPIO */
return mxc_get_gpio_datain(pin);
else if (para & 0x2) /* Write GPIO */
mxc_set_gpio_dataout(pin, 1);
else
mxc_set_gpio_dataout(pin, 0);
return 0;
}
/*!
* Setup GPIO for LCD to be active
*
*/
void gpio_lcd_active(void)
{
mxc_request_iomux(MX31_PIN_LD0, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
mxc_request_iomux(MX31_PIN_LD1, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
mxc_request_iomux(MX31_PIN_LD2, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
mxc_request_iomux(MX31_PIN_LD3, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
mxc_request_iomux(MX31_PIN_LD4, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
mxc_request_iomux(MX31_PIN_LD5, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
mxc_request_iomux(MX31_PIN_LD6, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
mxc_request_iomux(MX31_PIN_LD7, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
mxc_request_iomux(MX31_PIN_LD8, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
mxc_request_iomux(MX31_PIN_LD9, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
mxc_request_iomux(MX31_PIN_LD10, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
mxc_request_iomux(MX31_PIN_LD11, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
mxc_request_iomux(MX31_PIN_LD12, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
mxc_request_iomux(MX31_PIN_LD13, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
mxc_request_iomux(MX31_PIN_LD14, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
mxc_request_iomux(MX31_PIN_LD15, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
mxc_request_iomux(MX31_PIN_LD16, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // LD16
mxc_request_iomux(MX31_PIN_LD17, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // LD17
mxc_request_iomux(MX31_PIN_VSYNC3, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // VSYNC
mxc_request_iomux(MX31_PIN_HSYNC, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // HSYNC
mxc_request_iomux(MX31_PIN_FPSHIFT, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // CLK
mxc_request_iomux(MX31_PIN_CONTRAST, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); // CONTR
#ifdef CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL
mxc_request_iomux(MX31_PIN_DRDY0,
OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); /* DRDY */
mxc_request_iomux(MX31_PIN_D3_REV,
OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); /* REV */
mxc_request_iomux(MX31_PIN_D3_SPL,
OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); /* SPL */
mxc_request_iomux(MX31_PIN_D3_CLS,
OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC); /* CLS */
#else
/* ensure that LCDIO(1.8V) has been turn on */
/* active reset line GPIO */
mxc_request_iomux(MX31_PIN_LCS1, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
mxc_set_gpio_direction(MX31_PIN_LCS1, 0);
/* do reset */
mdelay(10); /* tRES >= 100us */
mxc_set_gpio_dataout(MX31_PIN_LCS1, 1);
/* enable data */
mxc_request_iomux(MX31_PIN_SER_RS, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
mxc_set_gpio_direction(MX31_PIN_SER_RS, 0);
mxc_set_gpio_dataout(MX31_PIN_SER_RS, 1);
#endif
}
static void lcd_reset(void)
{
/* ensure that LCDIO(1.8V) has been turn on */
/* active reset line GPIO */
mxc_request_iomux(MX31_PIN_LCS1, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
mxc_set_gpio_dataout(MX31_PIN_LCS1, 0);
mxc_set_gpio_direction(MX31_PIN_LCS1, 0);
/* do reset */
msleep(10); /* tRES >= 100us */
mxc_set_gpio_dataout(MX31_PIN_LCS1, 1);
msleep(60);
#ifdef CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL
mxc_set_gpio_dataout(MX31_PIN_LCS1, 0);
#endif
}
static void flexcan_xcvr_enable(int id, int en)
{
static int pwdn;
if (id != 1) /* MX25 3-stack uses only CAN2 */
return;
if (en) {
if (!pwdn++)
mxc_set_gpio_dataout(MX25_PIN_D14, 0);
} else {
if (!--pwdn)
mxc_set_gpio_dataout(MX25_PIN_D14, 1);
}
}
/*!
* Setup GPIO for sensor to be active
*
*/
void gpio_sensor_active(void)
{
gpio_sensor_select(0);
/*
* Configure the iomuxen for the CSI.
*/
mxc_request_iomux(MX31_PIN_CSI_D5, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
mxc_set_gpio_direction(MX31_PIN_CSI_D5, 0);
mxc_set_gpio_dataout(MX31_PIN_CSI_D5, 0);
mxc_request_iomux(MX31_PIN_CSI_D6, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
mxc_request_iomux(MX31_PIN_CSI_D7, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
mxc_request_iomux(MX31_PIN_CSI_D8, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
mxc_request_iomux(MX31_PIN_CSI_D9, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
mxc_request_iomux(MX31_PIN_CSI_D10, OUTPUTCONFIG_FUNC,
INPUTCONFIG_FUNC);
mxc_request_iomux(MX31_PIN_CSI_D11, OUTPUTCONFIG_FUNC,
INPUTCONFIG_FUNC);
mxc_request_iomux(MX31_PIN_CSI_D12, OUTPUTCONFIG_FUNC,
INPUTCONFIG_FUNC);
mxc_request_iomux(MX31_PIN_CSI_D13, OUTPUTCONFIG_FUNC,
INPUTCONFIG_FUNC);
mxc_request_iomux(MX31_PIN_CSI_D14, OUTPUTCONFIG_FUNC,
INPUTCONFIG_FUNC);
mxc_request_iomux(MX31_PIN_CSI_D15, OUTPUTCONFIG_FUNC,
INPUTCONFIG_FUNC);
mxc_request_iomux(MX31_PIN_CSI_HSYNC, OUTPUTCONFIG_FUNC,
INPUTCONFIG_FUNC);
mxc_request_iomux(MX31_PIN_CSI_MCLK, OUTPUTCONFIG_FUNC,
INPUTCONFIG_FUNC);
mxc_request_iomux(MX31_PIN_CSI_PIXCLK, OUTPUTCONFIG_FUNC,
INPUTCONFIG_FUNC);
mxc_request_iomux(MX31_PIN_CSI_VSYNC, OUTPUTCONFIG_FUNC,
INPUTCONFIG_FUNC);
if (mxc_request_iomux(MX31_PIN_A23, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE)
== 0) {
printk(KERN_ERR "%s:REGEN set request gpio ok\n", __func__);
} else {
printk(KERN_ERR "%s:REGEN set error, request gpio error\n",
__func__);
return;
}
mxc_set_gpio_direction(MX31_PIN_SD_D_IO, 0);
mxc_set_gpio_dataout(MX31_PIN_SD_D_IO, 1);
}
static void lcd_reset(void)
{
static int first;
/* active reset line GPIO */
if (!first) {
mxc_request_iomux(MX37_PIN_DI1_PIN13, IOMUX_CONFIG_ALT4);
first = 1;
}
mxc_set_gpio_direction(MX37_PIN_DI1_PIN13, 0);
mxc_set_gpio_dataout(MX37_PIN_DI1_PIN13, 0);
msleep(1); //1 reset low active, wait 10us more
mxc_set_gpio_dataout(MX37_PIN_DI1_PIN13, 1);
msleep(10); //1 wait 10us more, refer the operating manual
}
/*!
* This function enable and reset GPS GPIO
*/
void gpio_gps_active(void)
{
/* Pull GPIO1_5 to be low for routing signal to UART3/GPS */
if (board_is_mx35(BOARD_REV_2)) {
mxc_request_iomux(MX35_PIN_COMPARE, MUX_CONFIG_GPIO);
mxc_iomux_set_pad(MX35_PIN_COMPARE, PAD_CTL_DRV_NORMAL |
PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU |
PAD_CTL_DRV_3_3V | PAD_CTL_PUE_PUD |
PAD_CTL_SRE_SLOW);
mxc_set_gpio_direction(MX35_PIN_COMPARE, 0);
mxc_set_gpio_dataout(MX35_PIN_COMPARE, 0);
}
/* PWR_EN_GPS is set to be 0, will be toggled on in app by ioctl */
pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_2, 0, 0);
/* GPS 32KHz clock enbale */
pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 7, 1);
/* GPS reset */
pmic_gpio_set_bit_val(MCU_GPIO_REG_RESET_1, 5, 0);
msleep(5);
pmic_gpio_set_bit_val(MCU_GPIO_REG_RESET_1, 5, 1);
msleep(5);
}
void mxc_external_mute(void)
{
/* external mute */
mxc_request_iomux(MX37_PIN_AUD3_BB_FS, IOMUX_CONFIG_ALT4); // GPIO2_17
mxc_set_gpio_direction(MX37_PIN_AUD3_BB_FS, 0); // OUTPUT
mxc_set_gpio_dataout(MX37_PIN_AUD3_BB_FS, 0); // MUTE ON
}
static void lcd_reset_to2(void)
{
mxc_set_gpio_dataout(MX51_PIN_DI1_D1_CS, 0);
ipu_reset_disp_panel();
return;
}
/*!
* Setup GPIO for Keypad to be active
*
*/
void gpio_keypad_active(void)
{
#if 0
int pad_val;
/*
* Configure the IOMUX control register for keypad signals.
*/
/*KEY_INT */
mxc_request_iomux(MX37_PIN_GPIO1_3, IOMUX_CONFIG_ALT0);
/*KEY_WAKE */
mxc_request_iomux(MX37_PIN_DISP1_DAT18, IOMUX_CONFIG_ALT4);
/* fast slew rate */
pad_val = (PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_22K_PU | \
PAD_CTL_ODE_OPENDRAIN_ENABLE | PAD_CTL_HYS_NONE | \
PAD_CTL_DDR_INPUT_CMOS | PAD_CTL_DRV_VOT_LOW);
/*KEY_INT */
mxc_iomux_set_pad(MX37_PIN_GPIO1_3, pad_val);
/* fast slew rate */
pad_val = (PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | \
PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_HYS_NONE | \
PAD_CTL_DDR_INPUT_CMOS | PAD_CTL_DRV_VOT_LOW);
/*KEY_WAKE */
mxc_iomux_set_pad(MX37_PIN_DISP1_DAT18, pad_val);
mxc_set_gpio_direction(MX37_PIN_DISP1_DAT18, 0);
mxc_set_gpio_direction(MX37_PIN_GPIO1_3, 1);
/* drive initial value */
mxc_set_gpio_dataout(MX37_PIN_DISP1_DAT18, 1);
#endif
}
static void lcd_reset(void)
{
static int first;
/* ensure that LCDIO(1.8V) has been turn on */
/* active reset line GPIO */
if (!first) {
mxc_request_iomux(MX37_PIN_GPIO1_5, IOMUX_CONFIG_GPIO);
first = 1;
}
mxc_set_gpio_dataout(MX37_PIN_GPIO1_5, 0);
mxc_set_gpio_direction(MX37_PIN_GPIO1_5, 0);
/* do reset */
msleep(10); /* tRES >= 100us */
mxc_set_gpio_dataout(MX37_PIN_GPIO1_5, 1);
msleep(60);
}
void mxc_init_pmu_port(void)
{
// lp_core_gpio
mxc_request_iomux(MX37_PIN_EIM_RW, IOMUX_CONFIG_ALT3);
mxc_iomux_set_pad(MX37_PIN_EIM_RW, PAD_CTL_DRV_HIGH |PAD_CTL_HYS_NONE);
mxc_set_gpio_direction(MX37_PIN_EIM_RW, 0);
mxc_set_gpio_dataout(MX37_PIN_EIM_RW, 1);
}
/*!
* GPS GPIO
*/
void gpio_gps_active(void)
{
/* POWER_EN */
mxc_request_iomux(MX31_PIN_SCLK0,
OUTPUTCONFIG_GPIO, INPUTCONFIG_GPIO);
mxc_set_gpio_direction(MX31_PIN_SCLK0, 0);
/* Reset Pin */
mxc_request_iomux(MX31_PIN_DCD_DTE1,
OUTPUTCONFIG_GPIO, INPUTCONFIG_GPIO);
mxc_set_gpio_direction(MX31_PIN_DCD_DTE1, 0);
mxc_set_gpio_dataout(MX31_PIN_SCLK0, 0);
mxc_set_gpio_dataout(MX31_PIN_DCD_DTE1, 0);
msleep(5);
mxc_set_gpio_dataout(MX31_PIN_DCD_DTE1, 1);
msleep(5);
}
/*!
* Enable battery charge
* */
void mxc_enable_charge_poweron(void)
{
#if 0
/* Enable power on */
mxc_request_iomux(MX37_PIN_GPIO1_5, IOMUX_CONFIG_ALT0);
mxc_set_gpio_direction(MX37_PIN_GPIO1_5, 0);
mxc_set_gpio_dataout(MX37_PIN_GPIO1_5, 1);
/* Enable charge */
mxc_request_iomux(MX37_PIN_SD1_DATA0, IOMUX_CONFIG_ALT3);
mxc_set_gpio_direction(MX37_PIN_SD1_DATA0, 0);
mxc_set_gpio_dataout(MX37_PIN_SD1_DATA0, 1);
/* config change status pin to gpio in */
mxc_request_iomux(MX37_PIN_EIM_OE, IOMUX_CONFIG_ALT3);
mxc_set_gpio_direction(MX37_PIN_EIM_OE, 1);
#endif
}
/*!
* Board specific initialization.
*/
static void __init mxc_board_init(void)
{
/* config CS5 for debug board */
mxc_request_iomux(MX31_PIN_CS5, OUTPUTCONFIG_FUNC, INPUTCONFIG_FUNC);
mxc_cpu_common_init();
mxc_gpio_init();
early_console_setup(saved_command_line);
mxc_init_devices();
/*Pull down MX31_PIN_USB_BYP to reset USB3317 */
mxc_request_iomux(MX31_PIN_USB_BYP, OUTPUTCONFIG_GPIO,
INPUTCONFIG_NONE);
mxc_set_gpio_direction(MX31_PIN_USB_BYP, 0);
mxc_set_gpio_dataout(MX31_PIN_USB_BYP, 0);
mxc_free_iomux(MX31_PIN_USB_BYP, OUTPUTCONFIG_GPIO, INPUTCONFIG_NONE);
/* Reset BT/WiFi chip */
mxc_request_iomux(MX31_PIN_DCD_DCE1, OUTPUTCONFIG_GPIO,
INPUTCONFIG_NONE);
mxc_set_gpio_direction(MX31_PIN_DCD_DCE1, 0);
mxc_set_gpio_dataout(MX31_PIN_DCD_DCE1, 0);
mxc_init_pmic_audio();
mxc_expio_init();
mxc_init_keypad();
mxc_init_enet();
mxc_init_nand_mtd();
mxc_init_ch7024();
mx3_3stack_init_mc13783();
i2c_register_board_info(0, mxc_i2c_board_info,
ARRAY_SIZE(mxc_i2c_board_info));
spi_register_board_info(mxc_spi_board_info,
ARRAY_SIZE(mxc_spi_board_info));
mxc_init_fb();
mxc_init_bl();
mxc_init_mmc();
mxc_init_ide();
mxc_init_pata();
mxc_init_bluetooth();
mxc_init_gps();
}
/* workaround for ecspi chipselect pin may not keep correct level when idle */
void gpio_spi_chipselect_active(int cspi_mode, int status, int chipselect)
{
switch (cspi_mode) {
case 1:
switch (chipselect) {
case 0x1:
mxc_request_iomux(MX51_PIN_CSPI1_SS0,
IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0,
PAD_CTL_HYS_ENABLE |
PAD_CTL_PKE_ENABLE |
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
mxc_request_iomux(MX51_PIN_CSPI1_SS1,
IOMUX_CONFIG_GPIO);
mxc_set_gpio_direction(MX51_PIN_CSPI1_SS1, 0);
mxc_set_gpio_dataout(MX51_PIN_CSPI1_SS1, 2 & (~status));
break;
case 0x2:
mxc_request_iomux(MX51_PIN_CSPI1_SS1,
IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1,
PAD_CTL_HYS_ENABLE |
PAD_CTL_PKE_ENABLE |
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
mxc_request_iomux(MX51_PIN_CSPI1_SS0,
IOMUX_CONFIG_GPIO);
mxc_set_gpio_direction(MX51_PIN_CSPI1_SS0, 0);
mxc_set_gpio_dataout(MX51_PIN_CSPI1_SS0, 1 & (~status));
break;
default:
break;
}
break;
case 2:
break;
case 3:
break;
default:
break;
}
}
/*
* USB Host2 HS port
*/
static int gpio_usbh2_active(void)
{
/* Set USBH2_STP to GPIO and toggle it */
mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_GPIO);
mxc_set_gpio_direction(MX51_PIN_EIM_A26, 0);
mxc_set_gpio_dataout(MX51_PIN_EIM_A26, 1);
msleep(100);
return 0;
}
/*!
* Setup GPIO for SDHC1 to be inactive
*
* @param module SDHC module number
*/
void gpio_sdhc_inactive(int module)
{
switch (module) {
case 0:
mxc_free_iomux(MX31_PIN_SD1_CLK, OUTPUTCONFIG_FUNC,
INPUTCONFIG_FUNC);
mxc_free_iomux(MX31_PIN_SD1_CMD, OUTPUTCONFIG_FUNC,
INPUTCONFIG_FUNC);
mxc_free_iomux(MX31_PIN_SD1_DATA0, OUTPUTCONFIG_FUNC,
INPUTCONFIG_FUNC);
mxc_free_iomux(MX31_PIN_SD1_DATA1, OUTPUTCONFIG_FUNC,
INPUTCONFIG_FUNC);
mxc_free_iomux(MX31_PIN_SD1_DATA2, OUTPUTCONFIG_FUNC,
INPUTCONFIG_FUNC);
mxc_free_iomux(MX31_PIN_SD1_DATA3, OUTPUTCONFIG_FUNC,
INPUTCONFIG_FUNC);
mxc_free_iomux(MX31_PIN_SIMPD0, OUTPUTCONFIG_GPIO,
INPUTCONFIG_GPIO);
mxc_iomux_set_pad(MX31_PIN_SD1_CLK,
(PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW));
mxc_iomux_set_pad(MX31_PIN_SD1_CMD,
(PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW));
mxc_iomux_set_pad(MX31_PIN_SD1_DATA0,
(PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW));
mxc_iomux_set_pad(MX31_PIN_SD1_DATA1,
(PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW));
mxc_iomux_set_pad(MX31_PIN_SD1_DATA2,
(PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW));
mxc_iomux_set_pad(MX31_PIN_SD1_DATA3,
(PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW));
break;
case 1:
/* TODO:what are the pins for SDHC2? */
mxc_free_iomux(MX31_PIN_PC_CD2_B, OUTPUTCONFIG_FUNC,
INPUTCONFIG_NONE);
mxc_free_iomux(MX31_PIN_PC_CD1_B, OUTPUTCONFIG_FUNC,
INPUTCONFIG_NONE);
mxc_free_iomux(MX31_PIN_PC_WAIT_B, OUTPUTCONFIG_FUNC,
INPUTCONFIG_NONE);
mxc_free_iomux(MX31_PIN_PC_READY, OUTPUTCONFIG_FUNC,
INPUTCONFIG_NONE);
mxc_free_iomux(MX31_PIN_PC_VS1, OUTPUTCONFIG_FUNC,
INPUTCONFIG_NONE);
mxc_free_iomux(MX31_PIN_PC_PWRON, OUTPUTCONFIG_FUNC,
INPUTCONFIG_NONE);
mxc_set_gpio_direction(MX31_PIN_DSR_DCE1, 0);
mxc_set_gpio_dataout(MX31_PIN_DSR_DCE1, 0);
break;
default:
break;
}
}
/*!
* Setup GPIO PA25 high to end hard reset FS453 TV encoder
*
*/
void gpio_fs453_reset_high(void)
{
gpio_free_mux(MX27_PIN_CLS);
if (gpio_request_mux(MX27_PIN_CLS, GPIO_MUX_GPIO)) {
printk(KERN_ERR "bug: request GPIO PA25 failed.\n");
return;
}
/* PA25 (CLS) as output */
mxc_set_gpio_direction(MX27_PIN_CLS, 0);
gpio_config_mux(MX27_PIN_CLS, GPIO_MUX_GPIO);
mxc_set_gpio_dataout(MX27_PIN_CLS, 1);
}
static void bt_reset(void)
{
struct regulator *gpo4;
if (board_is_mx37(BOARD_REV_2)) {
gpo4 = regulator_get(NULL, "GPO4");
if (!IS_ERR(gpo4))
regulator_enable(gpo4);
regulator_put(gpo4);
} else {
mxc_request_iomux(MX37_PIN_AUD5_RXC, IOMUX_CONFIG_GPIO);
mxc_set_gpio_dataout(MX37_PIN_AUD5_RXC, 1);
mxc_set_gpio_direction(MX37_PIN_AUD5_RXC, 0);
}
}
/*!
* This function activates DAM ports 4 & 5 to enable
* audio I/O.
*/
void gpio_activate_audio_ports(void)
{
//
// AUD5_WB_TXD AUD_DATA_OUT
// AUD5_WB_RXD AUD_DATA_IN
// AUD5_WB_CK AUD_BCLK
// AUD5_WB_FS AUD_LRCK
// GPIO1_6 AUD_MCLK
unsigned int pad_val;
#if 0
/* AUD4_TXD */
mxc_request_iomux(MX37_PIN_DISP1_DAT20, IOMUX_CONFIG_ALT5);
/* AUD4_RXD */
mxc_request_iomux(MX37_PIN_DISP1_DAT21, IOMUX_CONFIG_ALT5);
/* AUD4_TXC */
mxc_request_iomux(MX37_PIN_DISP1_DAT22, IOMUX_CONFIG_ALT5);
/* AUD4_TXFS */
mxc_request_iomux(MX37_PIN_DISP1_DAT23, IOMUX_CONFIG_ALT5);
#endif
pad_val = PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST;
mxc_iomux_set_pad(MX37_PIN_AUD5_WB_CK, PAD_CTL_100K_PU | pad_val);
mxc_request_iomux(MX37_PIN_AUD5_WB_CK, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX37_PIN_AUD5_WB_RXD, pad_val);
mxc_request_iomux(MX37_PIN_AUD5_WB_RXD, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX37_PIN_AUD5_WB_TXD, pad_val);
mxc_request_iomux(MX37_PIN_AUD5_WB_TXD, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX37_PIN_AUD5_WB_FS, PAD_CTL_100K_PU | pad_val);
mxc_request_iomux(MX37_PIN_AUD5_WB_FS, IOMUX_CONFIG_ALT0);
/* Enable hysteresis for AUD5_WB_CK, AUD5_WB_RXD, AUD5_WB_TXD, AUD5_WB_FS */
mxc_iomux_set_pad(MX37_PIN_GRP_H5, PAD_CTL_HYS_ENABLE);
/* CLKO */
mxc_request_iomux(MX37_PIN_GPIO1_6, IOMUX_CONFIG_ALT2);
/* Mute */
mxc_request_iomux(MX37_PIN_AUD3_BB_FS, IOMUX_CONFIG_ALT4);
mxc_set_gpio_direction(MX37_PIN_AUD3_BB_FS, 0); // Output
mxc_set_gpio_dataout(MX37_PIN_AUD3_BB_FS, 0); // Mute On
mxc_free_iomux(MX37_PIN_AUD3_BB_FS, IOMUX_CONFIG_ALT4);
/* EARPHONE_DET */
mxc_request_iomux(MX37_PIN_GPIO1_5, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX37_PIN_GPIO1_5, PAD_CTL_HYS_ENABLE);
mxc_set_gpio_direction(MX37_PIN_GPIO1_5, 1); // Input
mxc_free_iomux(MX37_PIN_GPIO1_5, IOMUX_CONFIG_ALT0);
}
static void mxc_unifi_hardreset(int pin_level)
{
struct regulator *gpo4;
if (board_is_mx37(BOARD_REV_2)) {
gpo4 = regulator_get(NULL, "GPO4");
if (!IS_ERR(gpo4)) {
if (pin_level & 0x01)
regulator_enable(gpo4);
else
regulator_disable(gpo4);
}
regulator_put(gpo4);
} else {
mxc_request_iomux(MX37_PIN_AUD5_RXC, IOMUX_CONFIG_GPIO);
mxc_set_gpio_dataout(MX37_PIN_AUD5_RXC, pin_level & 0x01);
mxc_set_gpio_direction(MX37_PIN_AUD5_RXC, 0);
mxc_free_iomux(MX37_PIN_AUD5_RXC, IOMUX_CONFIG_GPIO);
}
}
static void wvga_reset(void)
{
mxc_set_gpio_dataout(MX51_PIN_DI1_D1_CS, 1);
}
static void bt_reset(void)
{
mxc_set_gpio_dataout(MX51_PIN_EIM_D19, 1);
}
static void mxc_unifi_hardreset(int pin_level)
{
mxc_set_gpio_dataout(MX51_PIN_EIM_D19, pin_level & 0x01);
}