// Send data packet // input: // pBuf - buffer with data to send // return: // nRF24_MASK_MAX_RT - if transmit failed with maximum auto retransmit count // nRF24_MAX_TX_DS - if transmit succeed // contents of STATUS register otherwise uint8_t nRF24_TXPacket(uint8_t * pBuf, uint8_t TX_PAYLOAD) { uint8_t status; CE_L(); nRF24_WriteBuf(nRF24_CMD_WREG | nRF24_REG_TX_ADDR,nRF24_TX_addr,nRF24_TX_ADDR_WIDTH); // Set static TX address nRF24_WriteBuf(nRF24_CMD_WREG | nRF24_REG_RX_ADDR_P0,nRF24_RX_addr,nRF24_RX_ADDR_WIDTH); // Set static RX address for auto ack nRF24_RWReg(nRF24_CMD_WREG | nRF24_REG_EN_AA,0x01); // Enable auto acknowledgement for data pipe 0 nRF24_RWReg(nRF24_CMD_WREG | nRF24_REG_SETUP_RETR,0x1A); // Automatic retransmission: wait 500us, 10 retries nRF24_RWReg(nRF24_CMD_WREG | nRF24_REG_RF_CH,0x6E); // Set frequency channel 110 (2.510MHz) nRF24_RWReg(nRF24_CMD_WREG | nRF24_REG_RF_SETUP,0x07); // Setup: 1Mbps, 0dBm, LNA on nRF24_WriteBuf(nRF24_CMD_W_TX_PAYLOAD,pBuf,TX_PAYLOAD); // Write specified buffer to FIFO nRF24_RWReg(nRF24_CMD_WREG | nRF24_REG_CONFIG,0x0E); // Config: CRC on (2 bytes), Power UP, RX/TX ctl = PTX CE_H(); // CE pin high => Start transmit // Delay_us(10); // Must hold CE at least 10us //while(PB_IDR_bit.IDR2 != 0); // Wait for IRQ from nRF24L01 CE_L(); status = nRF24_ReadReg(nRF24_REG_STATUS); // Read status register nRF24_RWReg(nRF24_CMD_WREG | nRF24_REG_STATUS,status | 0x70); // Clear RX_DR, TX_DS, MAX_RT flags if (status & nRF24_MASK_MAX_RT) { // Auto retransmit counter exceeds the programmed maximum limit. FIFO is not removed. nRF24_RWReg(nRF24_CMD_FLUSH_TX,0xFF); // Flush TX FIFO buffer return nRF24_MASK_MAX_RT; }; if (status & nRF24_MASK_TX_DS) { // Transmit ok nRF24_RWReg(nRF24_CMD_FLUSH_TX,0xFF); // Flush TX FIFO buffer return nRF24_MASK_TX_DS; } // Some banana happens return status; }
// Check if nRF24L01 present (send byte sequence, read it back and compare) // return: // 0 - looks like an nRF24L01 is online // 1 - received sequence differs from original uint8_t nRF24_Check(void) { uint8_t txbuf[5] = { 'W','o','l','k','?' }; uint8_t rxbuf[5]; uint8_t i; nRF24_WriteBuf(nRF24_CMD_WREG | nRF24_REG_TX_ADDR,txbuf,5); // Write fake TX address nRF24_ReadBuf(nRF24_REG_TX_ADDR,rxbuf,5); // Try to read TX_ADDR register for (i = 0; i < 5; i++) if (rxbuf[i] != txbuf[i]) return 1; return 0; }
// Put nRF24L01 in RX mode void nRF24_RXMode(uint8_t RX_PAYLOAD) { CE_L(); nRF24_RWReg(nRF24_CMD_WREG | nRF24_REG_EN_AA,0x01); // Enable ShockBurst for data pipe 0 nRF24_RWReg(nRF24_CMD_WREG | nRF24_REG_EN_RXADDR,0x01); // Enable data pipe 0 nRF24_RWReg(nRF24_CMD_WREG | nRF24_REG_RF_CH,0x6E); // Set frequency channel 110 (2.510MHz) nRF24_RWReg(nRF24_CMD_WREG | nRF24_REG_RX_PW_P0,RX_PAYLOAD); // Set RX payload length nRF24_RWReg(nRF24_CMD_WREG | nRF24_REG_RF_SETUP,0x06); // Setup: 1Mbps, 0dBm, LNA off nRF24_RWReg(nRF24_CMD_WREG | nRF24_REG_CONFIG,0x0F); // Config: CRC on (2 bytes), Power UP, RX/TX ctl = PRX nRF24_WriteBuf(nRF24_CMD_WREG | nRF24_REG_RX_ADDR_P0,nRF24_RX_addr,nRF24_RX_ADDR_WIDTH); // Set static RX address CE_H(); // Delay_us(10); // Hold CE high at least 10us }