static int nand_resume(struct platform_device *pdev)
{
struct nxp_nand *nxp = platform_get_drvdata(pdev);
struct mtd_info *mtd = &nxp->mtd;
struct nand_chip *chip = mtd->priv;
PM_DBGOUT("+%s\n", __func__);
/* Select the device */
nand_dev_init(mtd);
chip->select_chip(mtd, 0);
#if defined (CONFIG_MTD_NAND_ECC_HW)
nand_hw_ecc_init_device(mtd);
#endif
nxp_nand_timing_set(mtd);
/*
* Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
* after power-up
*/
chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
PM_DBGOUT("-%s\n", __func__);
return 0;
}
/*
* calling from nand_init (drivers/mtd/nand/nand.c)
*/
int board_nand_init(struct nand_chip *chip)
{
struct mtd_info *mtd = &nand_info[0];
int ret = 0;
nand_dev_init(mtd);
/*
* nand callbacks
*/
chip->IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
chip->IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
chip->cmd_ctrl = nand_cmd_ctrl;
chip->dev_ready = nand_dev_ready;
chip->select_chip = nand_select_chip;
chip->chip_delay = 15;
#if defined (CONFIG_MTD_NAND_ECC_BCH)
chip->write_page = nand_bch_write_page;
#endif
/*
* error correct mode
*/
#if defined (CONFIG_MTD_NAND_ECC_HW)
ret = nand_hw_ecc_init_device(mtd);
printk(KERN_INFO "NAND ecc: Hardware (delay %d)\n", chip->chip_delay);
#elif defined (CONFIG_MTD_NAND_ECC_BCH)
chip->ecc.mode = NAND_ECC_SOFT_BCH;
/* refer to nand_ecc.c */
switch (ECC_BCH_BITS) {
case 4: chip->ecc.bytes = 7; chip->ecc.size = 512; break;
case 8: chip->ecc.bytes = 13; chip->ecc.size = 512; break;
case 12: chip->ecc.bytes = 20; chip->ecc.size = 512; break;
case 16: chip->ecc.bytes = 26; chip->ecc.size = 512; break;
case 24: chip->ecc.bytes = 42; chip->ecc.size = 1024; break;
case 40: chip->ecc.bytes = 70; chip->ecc.size = 1024; break;
//case 60: chip->ecc.bytes = 105; chip->ecc.size = 1024; break; /* not test */
default:
printk("Fail: not supoort bch ecc %d mode !!!\n", ECC_BCH_BITS);
return -1;
}
printk(KERN_INFO "NAND ecc: Software BCH %d \n", ECC_BCH_BITS);
#else
chip->ecc.mode = NAND_ECC_SOFT;
printk(KERN_INFO "NAND ecc: Software \n");
#endif
nexell_nand_timing_set(mtd);
return ret;
}
static void android_mips_init_(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename,
const char *cpu_model)
{
CPUOldState *env;
qemu_irq *goldfish_pic;
int i;
ram_addr_t ram_offset;
if (!cpu_model)
cpu_model = "24Kf";
env = cpu_init(cpu_model);
register_savevm(NULL,
"cpu",
0,
MIPS_CPU_SAVE_VERSION,
cpu_save,
cpu_load,
env);
if (ram_size > GOLDFISH_IO_SPACE)
ram_size = GOLDFISH_IO_SPACE; /* avoid overlap of ram and IO regs */
ram_offset = qemu_ram_alloc(NULL, "android_mips", ram_size);
cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
/* Init internal devices */
cpu_mips_irq_init_cpu(env);
cpu_mips_clock_init(env);
goldfish_pic = goldfish_interrupt_init(GOLDFISH_INTERRUPT,
env->irq[2], env->irq[3]);
goldfish_device_init(goldfish_pic, GOLDFISH_DEVICES, 0x7f0000, 10, 22);
goldfish_device_bus_init(GOLDFISH_DEVICEBUS, 1);
goldfish_timer_and_rtc_init(GOLDFISH_RTC, 3);
goldfish_tty_add(serial_hds[0], 0, GOLDFISH_TTY, 4);
for(i = 1; i < MAX_SERIAL_PORTS; i++) {
if(serial_hds[i]) {
goldfish_tty_add(serial_hds[i], i, 0, 0);
}
}
for(i = 0; i < MAX_NICS; i++) {
if (nd_table[i].vlan) {
if (nd_table[i].model == NULL
|| strcmp(nd_table[i].model, "smc91c111") == 0) {
struct goldfish_device *smc_device;
smc_device = g_malloc0(sizeof(*smc_device));
smc_device->name = "smc91x";
smc_device->id = i;
smc_device->size = 0x1000;
smc_device->irq_count = 1;
goldfish_add_device_no_io(smc_device);
smc91c111_init(&nd_table[i], smc_device->base, goldfish_pic[smc_device->irq]);
} else {
fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
exit (1);
}
}
}
goldfish_fb_init(0);
#ifdef HAS_AUDIO
goldfish_audio_init(GOLDFISH_AUDIO, 0, audio_input_source);
#endif
{
DriveInfo* info = drive_get( IF_IDE, 0, 0 );
if (info != NULL) {
goldfish_mmc_init(GOLDFISH_MMC, 0, info->bdrv);
}
}
goldfish_battery_init(android_hw->hw_battery);
goldfish_add_device_no_io(&event0_device);
events_dev_init(event0_device.base, goldfish_pic[event0_device.irq]);
#ifdef CONFIG_NAND
goldfish_add_device_no_io(&nand_device);
nand_dev_init(nand_device.base);
#endif
#ifdef CONFIG_ANDROID_MEMCHECK
if (memcheck_enabled) {
trace_dev_init();
}
#endif // CONFIG_ANDROID_MEMCHECK
bool newDeviceNaming =
(androidHwConfig_getKernelDeviceNaming(android_hw) >= 1);
pipe_dev_init(newDeviceNaming);
android_load_kernel(env, ram_size, kernel_filename, kernel_cmdline, initrd_filename);
}
static int nand_probe(struct platform_device *pdev)
{
struct nxp_nand_plat_data *pdata = dev_get_platdata(&pdev->dev);
struct nxp_nand *nxp;
struct mtd_info *mtd;
struct nand_chip *chip;
int maxchips = CONFIG_SYS_NAND_MAX_CHIPS;
int chip_delay = !pdata ? 15 : (pdata->chip_delay ? pdata->chip_delay : 15);
#ifdef CFG_NAND_ECCIRQ_MODE
int irq = 0; /* platform_get_irq(pdev, 0); */
#endif
int ret = 0;
if (pdata == NULL)
dev_warn(&pdev->dev, "NULL platform data!\n");
nxp = kzalloc(sizeof (*nxp), GFP_KERNEL);
if (!nxp) {
printk(KERN_ERR "NAND: failed to allocate device structure.\n");
ret = -ENOMEM;
goto err_kzalloc;
}
nxp->pdev = pdev;
platform_set_drvdata(pdev, nxp);
mtd = &nxp->mtd;
chip = &nxp->chip;
mtd->priv = chip;
mtd->name = DEV_NAME_NAND;
mtd->owner = THIS_MODULE;
nand_dev_init(mtd);
/* insert callbacks */
chip->IO_ADDR_R = (void __iomem *)__PB_IO_MAP_NAND_VIRT;
chip->IO_ADDR_W = (void __iomem *)__PB_IO_MAP_NAND_VIRT;
chip->cmd_ctrl = nand_cmd_ctrl;
chip->dev_ready = nand_dev_ready;
chip->select_chip = nand_select_chip;
chip->chip_delay = chip_delay;
// chip->read_buf = nand_read_buf;
// chip->write_buf = nand_write_buf;
#if defined (CONFIG_MTD_NAND_ECC_BCH)
// chip->write_page = nand_bch_write_page;
#endif
#if defined (CONFIG_MTD_NAND_ECC_HW)
ret = nand_hw_ecc_init_device(mtd);
printk(KERN_INFO "NAND ecc: Hardware (delay %d)\n", chip_delay);
#elif defined (CONFIG_MTD_NAND_ECC_BCH)
chip->ecc.mode = NAND_ECC_SOFT_BCH;
/* refer to nand_ecc.c */
switch (ECC_BCH_BITS) {
case 4: chip->ecc.bytes = 7; chip->ecc.size = 512; break;
case 8: chip->ecc.bytes = 13; chip->ecc.size = 512; break;
case 12: chip->ecc.bytes = 20; chip->ecc.size = 512; break;
case 16: chip->ecc.bytes = 26; chip->ecc.size = 512; break;
case 24: chip->ecc.bytes = 42; chip->ecc.size = 1024; break;
case 40: chip->ecc.bytes = 70; chip->ecc.size = 1024; break;
// case 60: chip->ecc.bytes = 105; chip->ecc.size = 1024; break; /* not test */
default:
printk("Fail: not supoort bch ecc %d mode !!!\n", ECC_BCH_BITS);
ret = -1;
goto err_something;
}
printk(KERN_INFO "NAND ecc: Software BCH (delay %d)\n", chip_delay);
#else
chip->ecc.mode = NAND_ECC_SOFT;
printk(KERN_INFO "NAND ecc: Software (delay %d)\n", chip_delay);
#endif
printk(KERN_NOTICE "Scanning NAND device ...\n");
if (nand_scan(mtd, maxchips)) {
ret = -ENXIO;
goto err_something;
}
if (nand_ecc_layout_check(mtd)){
ret = -ENXIO;
goto err_something;
}
#ifdef CFG_NAND_ECCIRQ_MODE
ret = request_irq(irq, nxp_irq, 0, DEV_NAME_NAND, nxp);
if (ret < 0) {
pr_err("%s: failed to request_irq(%d)\n", __func__, 0);
ret = -ENODEV;
goto err_something;
}
nxp->irq = irq;
#endif
/* set command partition */
ret = mtd_device_parse_register(mtd, NULL, 0, pdata->parts, pdata->nr_parts);
if (ret) {
nand_release(mtd);
goto err_something;
} else {
// platform_set_drvdata(pdev, chip);
}
#ifdef CONFIG_NAND_RANDOMIZER
nxp->pages_per_block_mask = (mtd->erasesize/mtd->writesize) - 1;
if (!nxp->randomize_buf)
nxp->randomize_buf = kzalloc(mtd->writesize, GFP_KERNEL);
if (!nxp->randomize_buf) {
ERROUT("randomize buffer alloc failed\n");
goto err_something;
}
#endif
#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
if (!nxp->verify_page)
nxp->verify_page = kzalloc(NAND_MAX_PAGESIZE, GFP_KERNEL);
if (!nxp->verify_page) {
ERROUT("verify buffer alloc failed\n");
goto err_something;
}
#endif
nxp_nand_timing_set(mtd);
printk(KERN_NOTICE "%s: Nand partition \n", ret?"FAIL":"DONE");
return ret;
err_something:
#ifdef CONFIG_NAND_RANDOMIZER
if (nxp->randomize_buf)
kfree (nxp->randomize_buf);
#endif
#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
if (nxp->verify_page)
kfree (nxp->verify_page);
#endif
kfree(nxp);
err_kzalloc:
return ret;
}
static void android_arm_init_(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename,
const char *cpu_model)
{
CPUState *env;
qemu_irq *cpu_pic;
qemu_irq *goldfish_pic;
int i;
struct arm_boot_info info;
ram_addr_t ram_offset;
DisplayState* ds = get_displaystate();
if (!cpu_model)
cpu_model = "arm926";
env = cpu_init(cpu_model);
register_savevm( "cpu", 0, ARM_CPU_SAVE_VERSION, cpu_save, cpu_load, env );
ram_offset = qemu_ram_alloc(ram_size);
cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
cpu_pic = arm_pic_init_cpu(env);
goldfish_pic = goldfish_interrupt_init(0xff000000, cpu_pic[ARM_PIC_CPU_IRQ], cpu_pic[ARM_PIC_CPU_FIQ]);
goldfish_device_init(goldfish_pic, 0xff010000, 0x7f0000, 10, 22);
goldfish_device_bus_init(0xff001000, 1);
goldfish_timer_and_rtc_init(0xff003000, 3);
goldfish_tty_add(serial_hds[0], 0, 0xff002000, 4);
for(i = 1; i < MAX_SERIAL_PORTS; i++) {
//printf("android_arm_init serial %d %x\n", i, serial_hds[i]);
if(serial_hds[i]) {
goldfish_tty_add(serial_hds[i], i, 0, 0);
}
}
for(i = 0; i < MAX_NICS; i++) {
if (nd_table[i].vlan) {
if (nd_table[i].model == NULL
|| strcmp(nd_table[i].model, "smc91c111") == 0) {
struct goldfish_device *smc_device;
smc_device = qemu_mallocz(sizeof(*smc_device));
smc_device->name = "smc91x";
smc_device->id = i;
smc_device->size = 0x1000;
smc_device->irq_count = 1;
goldfish_add_device_no_io(smc_device);
smc91c111_init(&nd_table[i], smc_device->base, goldfish_pic[smc_device->irq]);
} else {
fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
exit (1);
}
}
}
goldfish_fb_init(ds, 0);
#ifdef HAS_AUDIO
goldfish_audio_init(0xff004000, 0, audio_input_source);
#endif
{
int idx = drive_get_index( IF_IDE, 0, 0 );
if (idx >= 0)
goldfish_mmc_init(0xff005000, 0, drives_table[idx].bdrv);
}
goldfish_memlog_init(0xff006000);
if (android_hw->hw_battery)
goldfish_battery_init();
goldfish_sensor_init();
goldfish_add_device_no_io(&event0_device);
events_dev_init(event0_device.base, goldfish_pic[event0_device.irq]);
#ifdef CONFIG_NAND
goldfish_add_device_no_io(&nand_device);
nand_dev_init(nand_device.base);
#endif
#ifdef CONFIG_TRACE
extern const char *trace_filename;
/* Init trace device if either tracing, or memory checking is enabled. */
if (trace_filename != NULL
#ifdef CONFIG_MEMCHECK
|| memcheck_enabled
#endif // CONFIG_MEMCHECK
) {
trace_dev_init();
}
if (trace_filename != NULL) {
D( "Trace file name is set to %s\n", trace_filename );
} else {
D("Trace file name is not set\n");
}
#endif
#if TEST_SWITCH
{
void *sw;
sw = goldfish_switch_add("test", NULL, NULL, 0);
goldfish_switch_set_state(sw, 1);
goldfish_switch_add("test2", switch_test_write, sw, 1);
}
#endif
memset(&info, 0, sizeof info);
info.ram_size = ram_size;
info.kernel_filename = kernel_filename;
info.kernel_cmdline = kernel_cmdline;
info.initrd_filename = initrd_filename;
info.nb_cpus = 1;
info.board_id = 1441;
arm_load_kernel(env, &info);
}
static void android_mips_init_(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename,
const char *cpu_model)
{
CPUState *env;
qemu_irq *goldfish_pic;
int i;
ram_addr_t ram_offset;
if (!cpu_model)
cpu_model = "24Kf";
env = cpu_init(cpu_model);
register_savevm( "cpu", 0, MIPS_CPU_SAVE_VERSION, cpu_save, cpu_load, env );
if (ram_size > GOLDFISH_IO_SPACE)
ram_size = GOLDFISH_IO_SPACE; /* avoid overlap of ram and IO regs */
ram_offset = qemu_ram_alloc(NULL, "android_mips", ram_size);
cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
/* Init internal devices */
cpu_mips_irq_init_cpu(env);
cpu_mips_clock_init(env);
goldfish_pic = goldfish_interrupt_init(GOLDFISH_INTERRUPT,
env->irq[2], env->irq[3]);
goldfish_device_init(goldfish_pic, GOLDFISH_DEVICES, 0x7f0000, 10, 22);
goldfish_device_bus_init(GOLDFISH_DEVICEBUS, 1);
goldfish_timer_and_rtc_init(GOLDFISH_RTC, 3);
goldfish_tty_add(serial_hds[0], 0, GOLDFISH_TTY, 4);
for(i = 1; i < MAX_SERIAL_PORTS; i++) {
if(serial_hds[i]) {
goldfish_tty_add(serial_hds[i], i, 0, 0);
}
}
for(i = 0; i < MAX_NICS; i++) {
if (nd_table[i].vlan) {
if (nd_table[i].model == NULL
|| strcmp(nd_table[i].model, "smc91c111") == 0) {
struct goldfish_device *smc_device;
smc_device = qemu_mallocz(sizeof(*smc_device));
smc_device->name = "smc91x";
smc_device->id = i;
smc_device->size = 0x1000;
smc_device->irq_count = 1;
goldfish_add_device_no_io(smc_device);
smc91c111_init(&nd_table[i], smc_device->base, goldfish_pic[smc_device->irq]);
} else {
fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
exit (1);
}
}
}
goldfish_fb_init(0);
#ifdef HAS_AUDIO
goldfish_audio_init(GOLDFISH_AUDIO, 0, audio_input_source);
#endif
{
DriveInfo* info = drive_get( IF_IDE, 0, 0 );
if (info != NULL) {
goldfish_mmc_init(GOLDFISH_MMC, 0, info->bdrv);
}
}
goldfish_memlog_init(GOLDFISH_MEMLOG);
if (android_hw->hw_battery)
goldfish_battery_init();
goldfish_add_device_no_io(&event0_device);
events_dev_init(event0_device.base, goldfish_pic[event0_device.irq]);
#ifdef CONFIG_NAND
goldfish_add_device_no_io(&nand_device);
nand_dev_init(nand_device.base);
#endif
#ifdef CONFIG_TRACE
extern const char *trace_filename;
/* Init trace device if either tracing, or memory checking is enabled. */
if (trace_filename != NULL
#ifdef CONFIG_MEMCHECK
|| memcheck_enabled
#endif // CONFIG_MEMCHECK
|| 1 /* XXX: ALWAYS AVAILABLE FOR QEMUD PIPES */
) {
trace_dev_init();
}
if (trace_filename != NULL) {
D( "Trace file name is set to %s\n", trace_filename );
} else {
D("Trace file name is not set\n");
}
#endif
pipe_dev_init();
#if TEST_SWITCH
{
void *sw;
sw = goldfish_switch_add("test", NULL, NULL, 0);
goldfish_switch_set_state(sw, 1);
goldfish_switch_add("test2", switch_test_write, sw, 1);
}
#endif
android_load_kernel(env, ram_size, kernel_filename, kernel_cmdline, initrd_filename);
}
static void android_arm_init_(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename,
const char *cpu_model)
{
CPUARMState *env;
qemu_irq *cpu_pic;
qemu_irq *goldfish_pic;
int i;
struct arm_boot_info info;
ram_addr_t ram_offset;
if (!cpu_model)
cpu_model = "arm926";
env = cpu_init(cpu_model);
ram_offset = qemu_ram_alloc(NULL,"android_arm",ram_size);
cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
cpu_pic = arm_pic_init_cpu(env);
goldfish_pic = goldfish_interrupt_init(0xff000000, cpu_pic[ARM_PIC_CPU_IRQ], cpu_pic[ARM_PIC_CPU_FIQ]);
goldfish_device_init(goldfish_pic, 0xff010000, 0x7f0000, 10, 22);
goldfish_device_bus_init(0xff001000, 1);
goldfish_timer_and_rtc_init(0xff003000, 3);
goldfish_tty_add(serial_hds[0], 0, 0xff002000, 4);
for(i = 1; i < MAX_SERIAL_PORTS; i++) {
//printf("android_arm_init serial %d %x\n", i, serial_hds[i]);
if(serial_hds[i]) {
goldfish_tty_add(serial_hds[i], i, 0, 0);
}
}
for(i = 0; i < MAX_NICS; i++) {
if (nd_table[i].vlan) {
if (nd_table[i].model == NULL
|| strcmp(nd_table[i].model, "smc91c111") == 0) {
struct goldfish_device *smc_device;
smc_device = g_malloc0(sizeof(*smc_device));
smc_device->name = "smc91x";
smc_device->id = i;
smc_device->size = 0x1000;
smc_device->irq_count = 1;
goldfish_add_device_no_io(smc_device);
smc91c111_init(&nd_table[i], smc_device->base, goldfish_pic[smc_device->irq]);
} else {
fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
exit (1);
}
}
}
goldfish_fb_init(0);
#ifdef HAS_AUDIO
goldfish_audio_init(0xff004000, 0, audio_input_source);
#endif
{
DriveInfo* info = drive_get( IF_IDE, 0, 0 );
if (info != NULL) {
goldfish_mmc_init(0xff005000, 0, info->bdrv);
}
}
goldfish_battery_init(android_hw->hw_battery);
goldfish_add_device_no_io(&event0_device);
events_dev_init(event0_device.base, goldfish_pic[event0_device.irq]);
#ifdef CONFIG_NAND
goldfish_add_device_no_io(&nand_device);
nand_dev_init(nand_device.base);
#endif
bool newDeviceNaming =
(androidHwConfig_getKernelDeviceNaming(android_hw) >= 1);
pipe_dev_init(newDeviceNaming);
memset(&info, 0, sizeof info);
info.ram_size = ram_size;
info.kernel_filename = kernel_filename;
info.kernel_cmdline = kernel_cmdline;
info.initrd_filename = initrd_filename;
info.nb_cpus = 1;
info.is_linux = 1;
info.board_id = 1441;
arm_load_kernel(env, &info);
}