void pciread(int dmod, int offset, int count) { epicsUInt32 tval; volatile char* dptr; short dbytes; int i; if(!diagbase) { printf("Run pcidiagset first\n"); return; } if(check_args(dmod, offset, count)) return; dbytes=dmod/8; count/=dbytes; if(count==0) count=1; for(i=0, dptr=diagbase+offset; i<count; i++, dptr+=dbytes) { if ((i*dbytes)%16==0) printf("\n0x%08x ",i*dbytes); else if ((i*dbytes)%4==0) printf(" "); switch(dmod){ case 8: tval=ioread8(dptr); printf("%02x",tval);break; case 16: tval=nat_ioread16(dptr);printf("%04x",tval);break; case 32: tval=nat_ioread32(dptr);printf("%08x",tval);break; } } printf("\n"); }
void SFP::updateNow(bool) { /* read I/O 4 bytes at a time to preserve endianness * for both PCI and VME */ epicsUInt32* p32=(epicsUInt32*)&buffer[0]; for(unsigned int i=0; i<SFPMEM_SIZE/4; i++) p32[i] = nat_ioread32(base+ i*4); valid = buffer[0]==3 && buffer[2]==7; }
static void printregisters(volatile epicsUInt8 *evg) { size_t reg; epicsPrintf("\n--- Register Dump @%p ---\n", evg); for(reg=0; reg<NELEMENTS(printreg); reg++){ switch(printreg[reg].rsize){ case 8: epicsPrintf("%16s: %02x\n", printreg[reg].label, ioread8(evg+printreg[reg].offset)); break; case 16: epicsPrintf("%16s: %04x\n", printreg[reg].label, nat_ioread16(evg+printreg[reg].offset)); break; case 32: epicsPrintf("%16s: %08x\n", printreg[reg].label, nat_ioread32(evg+printreg[reg].offset)); break; } } }
// call with interruptLock bool disarm() { // EVG_SEQ_RAM_DISABLE is really "stop" // to avoid aborting a potentially running sequencer, switch the trigger source to disable ctrlreg_hw &= ~(EVG_SEQ_RAM_SRC_MASK); switch(owner->type) { case SeqManager::TypeEVG: ctrlreg_hw |= 31; break; case SeqManager::TypeEVR: ctrlreg_hw |= 63; break; } nat_iowrite32(ctrlreg, ctrlreg_hw); bool isrun = nat_ioread32(ctrlreg) & EVG_SEQ_RAM_RUNNING; return isrun; }
// Called from ISR context void SoftSequence::sync() { DEBUG(3, ("Syncing %c\n", is_insync ? 'Y' : 'N') ); if(is_insync) {DEBUG(3, ("Skip\n")); return;} assert(hw); if(nat_ioread32(hw->ctrlreg)&EVG_SEQ_RAM_RUNNING) { // we may still be _ENABLED at this point, but the trigger source is set to // Disabled, so this makes no difference. epicsInterruptContextMessage("SoftSequence::sync() while running\n"); return; } // At this point the sequencer is not running and effectively disabled. // From paranoia, reset it anyway nat_iowrite32(hw->ctrlreg, hw->ctrlreg_hw | EVG_SEQ_RAM_RESET); hw->ctrlreg_user &= ~(EVG_SEQ_RAM_REPEAT_MASK|EVG_SEQ_RAM_SRC_MASK); switch(committed.mode) { case Single: hw->ctrlreg_user |= EVG_SEQ_RAM_SINGLE; break; case Normal: hw->ctrlreg_user |= EVG_SEQ_RAM_NORMAL; break; } epicsUInt8 src; // default to disabled switch(owner->type) { case SeqManager::TypeEVG: src = 31; break; case SeqManager::TypeEVR: src = 63; break; default: return; } // paranoia: disable any external trigger mappings owner->mapTriggerSrc(hw->idx, 0x02000000); // map trigger source codes // MSB governs the type of mapping switch(committed.src&0xff000000) { case 0x00000000: // raw mapping DEBUG(5, (" Raw mapping %x\n", committed.src)); // LSB is code src = committed.src&0xff; break; case 0x01000000: // software trigger mapping DEBUG(5, (" SW mapping %x\n", committed.src)); // ignore 0x00ffffff switch(owner->type) { case SeqManager::TypeEVG: src = 17+hw->idx; break; case SeqManager::TypeEVR: src = 61; break; } break; case 0x02000000: // external trigger DEBUG(5, (" EXT mapping %x\n", committed.src)); if(owner->type==SeqManager::TypeEVG) { // pass through to sub-class owner->mapTriggerSrc(hw->idx, committed.src); src = 24+hw->idx; } break; case 0x03000000: // disable trigger DEBUG(5, (" NO mapping %x\n", committed.src)); // use default break; default: DEBUG(0, ("unknown sequencer trigger code %08x\n", (unsigned)committed.src)); break; } DEBUG(5, (" Trig Src %x\n", src)); hw->ctrlreg_user |= src; // write out the RAM volatile epicsUInt32 *ram = static_cast<volatile epicsUInt32 *>(hw->rambase); for(size_t i=0, N=committed.codes.size(); i<N; i++) { nat_iowrite32(ram++, committed.times[i]); nat_iowrite32(ram++, committed.codes[i]); if(committed.codes[i]==0x7f) break; } { epicsUInt32 ctrl = hw->ctrlreg_hw = hw->ctrlreg_user; if(is_enabled) ctrl |= EVG_SEQ_RAM_ARM; else ctrl |= EVG_SEQ_RAM_DISABLE; // paranoia DEBUG(3, (" SeqCtrl %x\n", ctrl)); nat_iowrite32(hw->ctrlreg, ctrl); } is_insync = true; DEBUG(3, ("In Sync\n") ); }