void netfpga_wait_reg_ready(netfpga_device_t *nfpga){
uint32_t reg_val=0;
//Wait for the netfpga to be ready
netfpga_read_reg(nfpga, NETFPGA_OF_ACC_RDY_REG,®_val);
while ( !reg_val&0x01 ){
//Not ready loop
usleep(NETFPGA_READY_WAIT_TIME_US);
netfpga_read_reg(nfpga, NETFPGA_OF_ACC_RDY_REG,®_val);
}
}
rofl_result_t netfpga_update_entry_stats(of1x_flow_entry_t* entry){
uint32_t* aux;
netfpga_device_t* nfpga= netfpga_get();
netfpga_flow_entry_t* hw_entry;
netfpga_flow_entry_stats_t stats;
if(!entry)
return ROFL_FAILURE;
//Recover the hw entry
hw_entry = (netfpga_flow_entry_t*) entry->platform_state;
if(!hw_entry)
return ROFL_FAILURE;
//Wait for the netfpga to be ready
netfpga_wait_reg_ready(nfpga);
//Clear stats -> Really necessary?
memset(&stats,0,sizeof(stats));
//Write command
if( hw_entry->type == NETFPGA_FE_WILDCARDED )
netfpga_write_reg(nfpga, NETFPGA_OF_BASE_ADDR_REG, NETFPGA_WILDCARD_BASE + hw_entry->hw_pos);
else
netfpga_write_reg(nfpga, NETFPGA_OF_BASE_ADDR_REG, NETFPGA_EXACT_BASE + hw_entry->hw_pos);
//Write whatever => Trigger command
netfpga_write_reg(nfpga, NETFPGA_OF_READ_ORDER_REG, 0x1); // Write whatever the value
//Wait for the netfpga to be ready (again!)
netfpga_wait_reg_ready(nfpga);
//Now read and fill
aux = (uint32_t*)&stats;
netfpga_read_reg(nfpga, NETFPGA_OF_STATS_BASE_REG,aux);
netfpga_read_reg(nfpga, NETFPGA_OF_STATS_BASE_REG+1,(aux+1));
//Update main entry and return
entry->stats.s.counters.packet_count = stats.pkt_counter;
entry->stats.s.counters.byte_count = stats.byte_counter;
//ROFL_DEBUG("\n entry stats: %x, %x",stats.pkt_counter,stats.byte_counter );
//TODO time?? last-seen 7 bit??
return ROFL_SUCCESS;
}
rofl_result_t netfpga_read_misc_stats(uint32_t misc_stats[]){
unsigned int i;
netfpga_device_t* nfpga= netfpga_get();
for (i=0;i<NETFPGA_NUMBER_OF_MISC_STATS;i++)
{
netfpga_read_reg(nfpga, NETFPGA_OF_BASE_ADDR+i,&(misc_stats[i]));
//ROFL_DEBUG("\n stat: %x",misc_stats[i]);
}
return ROFL_SUCCESS;
}
