/* }}} */
Time_t StridePrefetcher::nextInvalidateSlot( const MemRequest *mreq)
/* calculate next free time {{{1 */
{
if (nextBuffSlot() > nextTableSlot())
return nextBuffSlot();
return nextTableSlot();
}
/* }}} */
Time_t StridePrefetcher::nextBusReadSlot( const MemRequest *mreq)
/* calculate next free time {{{1 */
{
return globalClock;
if (nextBuffSlot() > nextTableSlot())
return nextBuffSlot();
return nextTableSlot();
}
void TaggedPrefetcher::processAck(PAddr addr)
{
uint paddr = addr & defaultMask;
penFetchSet::iterator itF = pendingFetches.find(paddr);
if(itF == pendingFetches.end())
return;
bLine *l = buff->fillLine(paddr);
penReqMapper::iterator it = pendingRequests.find(paddr);
if(it != pendingRequests.end()) {
LOG("NLAP: returnAccess [%08lx]", paddr);
std::queue<MemRequest *> *tmpReqQueue;
tmpReqQueue = (*it).second;
while (tmpReqQueue->size()) {
tmpReqQueue->front()->goUpAbs(nextBuffSlot());
tmpReqQueue->pop();
}
pendingRequests.erase(paddr);
activeMemReqPool.in(tmpReqQueue);
}
pendingFetches.erase(paddr);
}
void MarkovPrefetcher::read(MemRequest *mreq)
{
uint32_t paddr = mreq->getPAddr() & defaultMask;
bLine *l = buff->readLine(paddr);
if(l) { //hit
LOG("GHBP: hit on [%08lx]", paddr);
hit.inc();
mreq->goUpAbs(nextBuffSlot());
return;
}
penFetchSet::iterator it = pendingFetches.find(paddr);
if(it != pendingFetches.end()) { // half-miss
//LOG("GHBP: half-miss on %08lx", paddr);
halfMiss.inc();
penReqMapper::iterator itR = pendingRequests.find(paddr);
if (itR == pendingRequests.end()) {
pendingRequests[paddr] = activeMemReqPool.out();
itR = pendingRequests.find(paddr);
}
I(itR != pendingRequests.end());
(*itR).second->push(mreq);
return;
}
//LOG("GHBP: miss on [%08lx]", paddr);
miss.inc();
mreq->goDown(0, lowerLevel[0]);
}
void TaggedPrefetcher::invalidate(PAddr addr,ushort size,MemObj *oc)
{
uint paddr = addr & defaultMask;
nextBuffSlot();
bLine *l = buff->readLine(paddr);
if(l)
l->invalidate();
}
void StridePrefetcher::invalidate(PAddr addr,ushort size,MemObj *oc)
{
uint paddr = addr & defaultMask;
nextBuffSlot();
bLine *l = buff->readLine(paddr);
if(l)
l->invalidate();
//invUpperLevel(addr,size,cb);
}
void AlwaysPrefetch::access(MemRequest *mreq)
{
// TODO: should i really consider all these read types?
if (mreq->getMemOperation() == MemRead
|| mreq->getMemOperation() == MemReadW) {
read(mreq);
} else {
nextBuffSlot();
mreq->goDown(0, lowerLevel[0]);
}
accesses.inc();
}
void StridePrefetcher::invalidate(MemRequest *mreq)
/* forward invalidate to the higher levels {{{1 */
{
uint32_t paddr = mreq->getAddr() & defaultMask; // FIXME: Maybe delete the defaultMask
nextBuffSlot();
bLine *l = buff->readLine(paddr);
if(l)
l->invalidate();
// broadcast the invalidate through the upper nodes
router->sendInvalidateAll(mreq->getLineSize(), mreq, mreq->getAddr(),hitDelay /*delay*/);
}
void StridePrefetcher::read(MemRequest *mreq)
{
uint paddr = mreq->getPAddr() & defaultMask;
bLine *l = buff->readLine(paddr);
if(l) { //hit
LOG("SP: hit on %08lx", paddr);
hit.inc();
mreq->goUpAbs(nextBuffSlot() + hitDelay);
learnHit(paddr);
return;
}
penFetchSet::iterator it = pendingFetches.find(paddr);
if(it != pendingFetches.end()) { // half-miss
LOG("SP: half-miss on %08lx", paddr);
halfMiss.inc();
penReqMapper::iterator itR = pendingRequests.find(paddr);
if (itR == pendingRequests.end()) {
pendingRequests[paddr] = activeMemReqPool.out();
itR = pendingRequests.find(paddr);
}
I(itR != pendingRequests.end());
(*itR).second->push(mreq);
learnHit(paddr); // half-miss is a hit from the learning point of view
return;
}
LOG("SP:miss on %08lx", paddr);
miss.inc();
learnMiss(paddr);
mreq->goDownAbs(nextBuffSlot() + missDelay, lowerLevel[0]);
}
void StridePrefetcher::access(MemRequest *mreq)
{
uint paddr = mreq->getPAddr() & defaultMask;
LOG("SP:access addr=%08lx", paddr);
// TODO: should i really consider all these read types?
if (mreq->getMemOperation() == MemRead
|| mreq->getMemOperation() == MemReadW) {
read(mreq);
} else {
LOG("SP:ignoring access addr=%08lx type=%d", paddr, mreq->getMemOperation());
nextBuffSlot();
bLine *l = buff->readLine(paddr);
if(l)
l->invalidate();
mreq->goDown(0, lowerLevel[0]);
}
accesses.inc();
}
void AlwaysPrefetch::read(MemRequest *mreq)
{
uint32_t paddr = mreq->getPAddr() & defaultMask;
bLine *l = buff->readLine(paddr);
if(l) { //hit
LOG("NLAP: hit on [%08lx]", (long unsigned int) paddr);
hit.inc();
mreq->goUpAbs(nextBuffSlot());
return;
}
penFetchSet::iterator it = pendingFetches.find(paddr);
if(it != pendingFetches.end()) { // half-miss
LOG("NLAP: half-miss on %08lx",(long unsigned int) paddr);
penReqMapper::iterator itR = pendingRequests.find(paddr);
halfMiss.inc();
if (itR == pendingRequests.end()) {
pendingRequests[paddr] = activeMemReqPool.out();
itR = pendingRequests.find(paddr);
}
I(itR != pendingRequests.end());
(*itR).second->push(mreq);
//prefetch(paddr+lineSize, 0);
//prefetch( paddr + buff->getLineSize(), 0 );
return;
}
LOG("NLAP: miss on [%08lx]", (long unsigned int) paddr);
miss.inc();
Time_t lat = nextTableSlot() - globalClock;
prefetch(paddr+(buff->getLineSize()), lat);
lat = nextTableSlot() - globalClock;
prefetch(paddr+(2*buff->getLineSize()), lat);
mreq->goDown(0, lowerLevel[0]);
}
