static void mipi_initialize(void)
{
int clkid = DISP_CLOCK_MIPI;
int index = 0;
NX_TIEOFF_Set(TIEOFFINDEX_OF_MIPI0_NX_DPSRAM_1R1W_EMAA, 3);
NX_TIEOFF_Set(TIEOFFINDEX_OF_MIPI0_NX_DPSRAM_1R1W_EMAB, 3);
if (! nxp_soc_peri_reset_status(NX_MIPI_GetResetNumber(index, NX_MIPI_RST))) {
nxp_soc_peri_reset_enter(NX_MIPI_GetResetNumber(index, NX_MIPI_RST));
nxp_soc_peri_reset_enter(NX_MIPI_GetResetNumber(index, NX_MIPI_RST_DSI_I));
nxp_soc_peri_reset_enter(NX_MIPI_GetResetNumber(index, NX_MIPI_RST_PHY_S));
nxp_soc_peri_reset_enter(NX_MIPI_GetResetNumber(index, NX_MIPI_RST_PHY_M));
nxp_soc_peri_reset_exit (NX_MIPI_GetResetNumber(index, NX_MIPI_RST));
nxp_soc_peri_reset_exit (NX_MIPI_GetResetNumber(index, NX_MIPI_RST_DSI_I));
nxp_soc_peri_reset_exit (NX_MIPI_GetResetNumber(index, NX_MIPI_RST_PHY_S));
nxp_soc_peri_reset_exit (NX_MIPI_GetResetNumber(index, NX_MIPI_RST_PHY_M));
}
/* BASE : CLKGEN, MIPI */
NX_DISPTOP_CLKGEN_SetBaseAddress(clkid, (U32)IO_ADDRESS(NX_DISPTOP_CLKGEN_GetPhysicalAddress(clkid)));
NX_DISPTOP_CLKGEN_SetClockPClkMode(clkid, NX_PCLKMODE_ALWAYS);
/* BASE : MIPI */
NX_MIPI_Initialize();
NX_MIPI_SetBaseAddress(0, IO_ADDRESS(NX_MIPI_GetPhysicalAddress(0)));
NX_MIPI_OpenModule(0);
}
void lltime_start(void)
{
int ch = CFG_TIMER_DBG_TICK_CH;
ulong count = (-1UL), val;
int mux = __timer_sys_mux_val;
int scl = __timer_sys_scl_val;
if (true == __dbg_timer_run)
return;
if (!nxp_soc_peri_reset_status(RESET_ID_TIMER))
nxp_soc_peri_reset_set(RESET_ID_TIMER);
/* clock gen : enable */
if (5 == mux) {
uint clr = __timer_sys_clk_clr;
uint enb = readl(TIMER_SYS_CLKGEN + CLKGEN_ENB);
writel(clr , TIMER_DBG_CLKGEN + CLKGEN_CLR);
writel((enb | 1<<2), TIMER_DBG_CLKGEN + CLKGEN_ENB);
}
/* Timer : stop */
val = readl(TIMER_BASE + TIMER_TCON);
val &= ~(TCON_RUN << TCON_CH(ch));
writel(val, TIMER_BASE + TIMER_TCON);
/* Timer : prescaler (clock) */
val = readl(TIMER_BASE + TIMER_CFG0);
val &= ~(0xFF << CFG0_CH(ch));
val |= ((scl-1)<< CFG0_CH(ch));
writel(val, (TIMER_BASE + TIMER_CFG0));
/* Timer : mux (clock) */
val = readl(TIMER_BASE + TIMER_CFG1);
val &= ~(0xF << CFG1_CH(ch));
val |= (mux << CFG1_CH(ch));
writel(val, (TIMER_BASE + TIMER_CFG1));
/* Timer : count */
writel(count, TIMER_BASE + TIMER_CNTB + (TIMER_CH_OFFS * ch));
writel(count, TIMER_BASE + TIMER_CMPB + (TIMER_CH_OFFS * ch));
/* Timer : start */
val = readl(TIMER_BASE + TIMER_STAT);
val &= ~(TINT_CS_MASK<<5 | 0x1 << TINT_CH(ch));
val |= (0x1 << TINT_CS_CH(ch) | 0 << TINT_CH(ch));
writel(val, TIMER_BASE + TIMER_STAT);
val = readl(TIMER_BASE + TIMER_TCON);
val &= ~(0xE << TCON_CH(ch));
val |= (TCON_UP << TCON_CH(ch));
writel(val, TIMER_BASE + TIMER_TCON);
val &= ~(TCON_UP << TCON_CH(ch));
val |= ((TCON_AUTO | TCON_RUN) << TCON_CH(ch));
writel(val, TIMER_BASE + TIMER_TCON);
__dbg_timer_run = true;
}
static void mipi_resume(struct disp_process_dev *pdev)
{
int index = 0;
PM_DBGOUT("%s\n", __func__);
NX_TIEOFF_Set(TIEOFFINDEX_OF_MIPI0_NX_DPSRAM_1R1W_EMAA, 3);
NX_TIEOFF_Set(TIEOFFINDEX_OF_MIPI0_NX_DPSRAM_1R1W_EMAB, 3);
if (! nxp_soc_peri_reset_status(NX_MIPI_GetResetNumber(index, NX_MIPI_RST))) {
nxp_soc_peri_reset_enter(NX_MIPI_GetResetNumber(index, NX_MIPI_RST));
nxp_soc_peri_reset_enter(NX_MIPI_GetResetNumber(index, NX_MIPI_RST_DSI_I));
nxp_soc_peri_reset_enter(NX_MIPI_GetResetNumber(index, NX_MIPI_RST_PHY_S));
nxp_soc_peri_reset_enter(NX_MIPI_GetResetNumber(index, NX_MIPI_RST_PHY_M));
nxp_soc_peri_reset_exit (NX_MIPI_GetResetNumber(index, NX_MIPI_RST));
nxp_soc_peri_reset_exit (NX_MIPI_GetResetNumber(index, NX_MIPI_RST_DSI_I));
nxp_soc_peri_reset_exit (NX_MIPI_GetResetNumber(index, NX_MIPI_RST_PHY_S));
nxp_soc_peri_reset_exit (NX_MIPI_GetResetNumber(index, NX_MIPI_RST_PHY_M));
}
mipi_enable(pdev, 1);
}
inline static void uart_init(void)
{
U32 CLKENB = UART_CLKG_BASE;
U32 CLKGEN = UART_CLKG_BASE + 0x04;
struct uart_data *pdat = &udata;
struct s5p_uart *uart = (struct s5p_uart *)UART_PHYS_BASE;
unsigned int baudrate = UART_DEBUG_BAUDRATE;
unsigned int clkval;
/* Clock Generotor & reset */
if (0 == pdat->rate) {
u32 val = UART_DEBUG_HZ / baudrate;
pdat->rate = calc_uart_clock(UART_DEBUG_HZ, &pdat->pll, &pdat->div);
pdat->ubrdiv = (val/16) - 1;
pdat->udivslot = udivslot[val % 16];
/* NORMAL | No parity | 1 stop | 8bit */
pdat->ulcon = (((0 & 0x1)<<6) | ((0 & 0x3)<<3) | ((0 & 0x1)<<2) | ((3 & 0x3)<<0));
/* Tx FIFO clr | Rx FIFO clr | FIFOs EN */
pdat->ufcon = (((1 & 0x1)<<1) | ((1 & 0x1)<<0));
}
/* check reset */
if (!nxp_soc_peri_reset_status(RESET_UART_ID)) {
NX_TIEOFF_Set(TIEOFF_USESMC , 0);
NX_TIEOFF_Set(TIEOFF_SMCTXENB, 0);
NX_TIEOFF_Set(TIEOFF_SMCRXENB, 0);
nxp_soc_peri_reset_set(RESET_UART_ID);
}
/* check pll : alaway enable clkgen */
clkval = readl(CLKGEN) & ~(0x07<<2) & ~(0xFF<<5);
writel((clkval|(pdat->pll<<2)|((pdat->div-1)<<5)), CLKGEN);
writel((readl(CLKENB)|(1<<2)), CLKENB);
/* Uart Register */
writel(pdat->ufcon, &uart->ufcon);
writel(pdat->ulcon, &uart->ulcon);
writel(pdat->ubrdiv, &uart->ubrdiv);
writew(pdat->udivslot, &uart->rest.slot);
}
static inline void timer_reset(int ch)
{
if (!nxp_soc_peri_reset_status(RESET_ID_TIMER))
nxp_soc_peri_reset_set(RESET_ID_TIMER);
}
