static void omap_usb_dpll_lock(struct omap_usb3_phy *phy_regs) { u32 clk_index = get_sys_clk_index(); u32 val; val = readl(&phy_regs->pll_config_1); val &= ~PLL_REGN_MASK; val |= omap_usb3_dpll_params[clk_index].n << PLL_REGN_SHIFT; writel(val, &phy_regs->pll_config_1); val = readl(&phy_regs->pll_config_2); val &= ~PLL_SELFREQDCO_MASK; val |= omap_usb3_dpll_params[clk_index].freq << PLL_SELFREQDCO_SHIFT; writel(val, &phy_regs->pll_config_2); val = readl(&phy_regs->pll_config_1); val &= ~PLL_REGM_MASK; val |= omap_usb3_dpll_params[clk_index].m << PLL_REGM_SHIFT; writel(val, &phy_regs->pll_config_1); val = readl(&phy_regs->pll_config_4); val &= ~PLL_REGM_F_MASK; val |= omap_usb3_dpll_params[clk_index].mf << PLL_REGM_F_SHIFT; writel(val, &phy_regs->pll_config_4); val = readl(&phy_regs->pll_config_3); val &= ~PLL_SD_MASK; val |= omap_usb3_dpll_params[clk_index].sd << PLL_SD_SHIFT; writel(val, &phy_regs->pll_config_3); omap_usb_dpll_relock(phy_regs); }
static int omap_usb_dpll_lock(struct omap_usb *phy) { u32 val; unsigned long rate; enum sys_clk_rate clk_index; rate = clk_get_rate(phy->sys_clk); clk_index = __get_sys_clk_index(rate); if (clk_index == CLK_RATE_UNDEFINED) { pr_err("dpll cannot be locked for sys clk freq:%luHz\n", rate); return -EINVAL; } val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); val &= ~PLL_REGN_MASK; val |= omap_usb3_dpll_params[clk_index].n << PLL_REGN_SHIFT; omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); val &= ~PLL_SELFREQDCO_MASK; val |= omap_usb3_dpll_params[clk_index].freq << PLL_SELFREQDCO_SHIFT; omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); val &= ~PLL_REGM_MASK; val |= omap_usb3_dpll_params[clk_index].m << PLL_REGM_SHIFT; omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4); val &= ~PLL_REGM_F_MASK; val |= omap_usb3_dpll_params[clk_index].mf << PLL_REGM_F_SHIFT; omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val); val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3); val &= ~PLL_SD_MASK; val |= omap_usb3_dpll_params[clk_index].sd << PLL_SD_SHIFT; omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val); omap_usb_dpll_relock(phy); return 0; }