static void omap_kp_scan_keypad(struct omap_kp *omap_kp, unsigned char *state)
{
int col = 0;
/* read the keypad status */
if (cpu_is_omap24xx()) {
/* read the keypad status */
for (col = 0; col < omap_kp->cols; col++) {
set_col_gpio_val(omap_kp, ~(1 << col));
state[col] = ~(get_row_gpio_val(omap_kp)) & 0xff;
}
set_col_gpio_val(omap_kp, 0);
} else {
/* disable keyboard interrupt and schedule for handling */
omap_writew(1, OMAP1_MPUIO_BASE + OMAP_MPUIO_KBD_MASKIT);
/* read the keypad status */
omap_writew(0xff, OMAP1_MPUIO_BASE + OMAP_MPUIO_KBC);
for (col = 0; col < omap_kp->cols; col++) {
omap_writew(~(1 << col) & 0xff,
OMAP1_MPUIO_BASE + OMAP_MPUIO_KBC);
udelay(omap_kp->delay);
state[col] = ~omap_readw(OMAP1_MPUIO_BASE +
OMAP_MPUIO_KBR_LATCH) & 0xff;
}
omap_writew(0x00, OMAP1_MPUIO_BASE + OMAP_MPUIO_KBC);
udelay(2);
}
}
int
ck_set_input(ck_t ck, ck_t input)
{
int ret = 0, shift;
unsigned short reg;
unsigned long flags;
if (!CK_IN_RANGE(ck) || !CK_CAN_SWITCH(ck)) {
ret = -EINVAL;
goto exit;
}
reg = omap_readw(CK_SELECT_REG(ck));
shift = CK_SELECT_SHIFT(ck);
spin_lock_irqsave(&clock_lock, flags);
if (input == OMAP_CLKIN) {
reg &= ~(1 << shift);
omap_writew(reg, CK_SELECT_REG(ck));
goto exit;
} else if (input == CK_PARENT(ck)) {
reg |= (1 << shift);
omap_writew(reg, CK_SELECT_REG(ck));
goto exit;
}
ret = -EINVAL;
exit:
spin_unlock_irqrestore(&clock_lock, flags);
return ret;
}
static void __init htcherald_lcd_init(void)
{
u32 reg;
unsigned int tries = 200;
/* disable controller if active */
reg = omap_readl(OMAP_LCDC_CONTROL);
if (reg & OMAP_LCDC_CTRL_LCD_EN) {
reg &= ~OMAP_LCDC_CTRL_LCD_EN;
omap_writel(reg, OMAP_LCDC_CONTROL);
/* wait for end of frame */
while (!(omap_readl(OMAP_LCDC_STATUS) & OMAP_LCDC_STAT_DONE)) {
tries--;
if (!tries)
break;
}
if (!tries)
printk(KERN_WARNING "Timeout waiting for end of frame "
"-- LCD may not be available\n");
/* turn off DMA */
reg = omap_readw(OMAP_DMA_LCD_CCR);
reg &= ~(1 << 7);
omap_writew(reg, OMAP_DMA_LCD_CCR);
reg = omap_readw(OMAP_DMA_LCD_CTRL);
reg &= ~(1 << 8);
omap_writew(reg, OMAP_DMA_LCD_CTRL);
}
}
void omap_setup_lcd_dma(void)
{
BUG_ON(lcd_dma.active);
if (!cpu_is_omap15xx()) {
/* Set some reasonable defaults */
omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
}
set_b1_regs();
if (!cpu_is_omap15xx()) {
u16 w;
w = omap_readw(OMAP1610_DMA_LCD_CCR);
/*
* If DMA was already active set the end_prog bit to have
* the programmed register set loaded into the active
* register set.
*/
w |= 1 << 11; /* End_prog */
if (!lcd_dma.single_transfer)
w |= (3 << 8); /* Auto_init, repeat */
omap_writew(w, OMAP1610_DMA_LCD_CCR);
}
}
static void __init omap_mpu_wdt_mode(int mode) {
if (mode)
omap_writew(0x8000, OMAP_WDT_TIMER_MODE);
else {
omap_writew(0x00f5, OMAP_WDT_TIMER_MODE);
omap_writew(0x00a0, OMAP_WDT_TIMER_MODE);
}
}
static int __init omap_kp_probe(struct device *dev)
{
int i;
/* Disable the interrupt for the MPUIO keyboard */
omap_writew(1, OMAP_MPUIO_BASE + OMAP_MPUIO_KBD_MASKIT);
if (machine_is_omap_h2() || machine_is_omap_h3()) {
keymap = h2_keymap;
set_bit(EV_REP, omap_kp_dev.evbit);
} else if (machine_is_omap_innovator()) {
keymap = innovator_keymap;
} else if (machine_is_omap_osk()) {
keymap = osk_keymap;
} else {
keymap = test_keymap;
}
init_timer(&kp_timer);
kp_timer.function = omap_kp_timer;
/* get the irq and init timer*/
tasklet_enable(&kp_tasklet);
if (request_irq(INT_KEYBOARD, omap_kp_interrupt, 0,
"omap-keypad", 0) < 0)
return -EINVAL;
/* setup input device */
set_bit(EV_KEY, omap_kp_dev.evbit);
for (i = 0; keymap[i] != 0; i++)
set_bit(keymap[i] & 0x00ffffff, omap_kp_dev.keybit);
omap_kp_dev.name = "omap-keypad";
input_register_device(&omap_kp_dev);
if (machine_is_omap_h2() || machine_is_omap_h3()) {
omap_cfg_reg(F18_1610_KBC0);
omap_cfg_reg(D20_1610_KBC1);
omap_cfg_reg(D19_1610_KBC2);
omap_cfg_reg(E18_1610_KBC3);
omap_cfg_reg(C21_1610_KBC4);
omap_cfg_reg(G18_1610_KBR0);
omap_cfg_reg(F19_1610_KBR1);
omap_cfg_reg(H14_1610_KBR2);
omap_cfg_reg(E20_1610_KBR3);
omap_cfg_reg(E19_1610_KBR4);
omap_cfg_reg(N19_1610_KBR5);
omap_writew(0xff, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_DEBOUNCING);
}
/* scan current status and enable interrupt */
omap_kp_scan_keypad(keypad_state);
omap_writew(0, OMAP_MPUIO_BASE + OMAP_MPUIO_KBD_MASKIT);
return 0;
}
static void ams_delta_write_byte(struct mtd_info *mtd, u_char byte)
{
struct nand_chip *this = mtd->priv;
omap_writew(0, (OMAP_MPUIO_BASE + OMAP_MPUIO_IO_CNTL));
omap_writew(byte, this->IO_ADDR_W);
ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_NWE, 0);
ndelay(40);
ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_NWE,
AMS_DELTA_LATCH2_NAND_NWE);
}
void __init omap1_init_early(void)
{
omap_check_revision();
omap_writew(0x0, MPU_PUBLIC_TIPB_CNTL);
omap_writew(0x0, MPU_PRIVATE_TIPB_CNTL);
omap1_clk_init();
omap1_mux_init();
omap_init_consistent_dma_size();
}
void hard_debug2(u16 i)
{
for (; i; i--) {
omap_writew(0x8000,
OMAP1610_GPIO1_BASE + OMAP1610_GPIO_CLEAR_DATAOUT);
udelay(HDBG_DELAY);
omap_writew(0x8000,
OMAP1610_GPIO1_BASE + OMAP1610_GPIO_SET_DATAOUT);
udelay(HDBG_DELAY);
}
}
void omap1_restart(enum reboot_mode mode, const char *cmd)
{
/*
* Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
* "Global Software Reset Affects Traffic Controller Frequency".
*/
if (cpu_is_omap5912()) {
omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4), DPLL_CTL);
omap_writew(0x8, ARM_RSTCT1);
}
omap_writew(1, ARM_RSTCT1);
}
static void __init omap_nokia770_init_irq(void)
{
/* On Nokia 770, the SleepX signal is masked with an
* MPUIO line by default. It has to be unmasked for it
* to become functional */
/* SleepX mask direction */
omap_writew((omap_readw(0xfffb5008) & ~2), 0xfffb5008);
/* Unmask SleepX signal */
omap_writew((omap_readw(0xfffb5004) & ~2), 0xfffb5004);
omap1_init_common_hw();
omap1_init_irq();
}
/*
* Common low-level hardware init for omap1. This should only get called from
* board specific init.
*/
void __init omap1_init_common_hw(void)
{
/* REVISIT: Refer to OMAP5910 Errata, Advisory SYS_1: "Timeout Abort
* on a Posted Write in the TIPB Bridge".
*/
omap_writew(0x0, MPU_PUBLIC_TIPB_CNTL);
omap_writew(0x0, MPU_PRIVATE_TIPB_CNTL);
/* Must init clocks early to assure that timer interrupt works
*/
omap1_clk_init();
omap1_mux_init();
}
void omap_stop_lcd_dma(void)
{
u16 w;
lcd_dma.active = 0;
if (cpu_is_omap15xx() || !lcd_dma.ext_ctrl)
return;
w = omap_readw(OMAP1610_DMA_LCD_CCR);
w &= ~(1 << 7);
omap_writew(w, OMAP1610_DMA_LCD_CCR);
w = omap_readw(OMAP1610_DMA_LCD_CTRL);
w &= ~(1 << 8);
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
}
static irqreturn_t omap_kp_interrupt(int irq, void *dev_id)
{
struct omap_kp *omap_kp = dev_id;
/* */
if (cpu_is_omap24xx()) {
int i;
for (i = 0; i < omap_kp->rows; i++) {
int gpio_irq = gpio_to_irq(row_gpios[i]);
/*
*/
if (gpio_irq == irq)
disable_irq_nosync(gpio_irq);
else
disable_irq(gpio_irq);
}
} else
/* */
omap_writew(1, OMAP1_MPUIO_BASE + OMAP_MPUIO_KBD_MASKIT);
tasklet_schedule(&kp_tasklet);
return IRQ_HANDLED;
}
static void tahvo_usb_power_off(struct tahvo_usb *tu)
{
u32 l;
int id;
/* Disable gadget controller if any */
if (tu->otg.gadget)
usb_gadget_vbus_disconnect(tu->otg.gadget);
/* Disable OTG and interrupts */
if (TAHVO_MODE(tu) == TAHVO_MODE_PERIPHERAL)
id = OTG_ID;
else
id = 0;
l = omap_readl(OTG_CTRL);
l &= ~(OTG_CTRL_XCVR_MASK | OTG_CTRL_SYS_MASK | OTG_BSESSVLD);
l |= id | OTG_BSESSEND;
omap_writel(l, OTG_CTRL);
omap_writew(0, OTG_IRQ_EN);
l = omap_readl(OTG_SYSCON_2);
l &= ~OTG_EN;
omap_writel(l, OTG_SYSCON_2);
l = omap_readl(OTG_SYSCON_1);
l |= OTG_IDLE_EN;
omap_writel(l, OTG_SYSCON_1);
/* Power off transceiver */
tahvo_write_reg(tu->dev, TAHVO_REG_USBR, 0);
tu->otg.state = OTG_STATE_UNDEFINED;
}
static void sdi_pad_config(struct omap_display *display, bool enable)
{
int data_pairs;
bool pad_off_pe, pad_off_pu;
unsigned req_map;
int i;
data_pairs = display->hw_config.u.sdi.datapairs;
pad_off_pe = display->hw_config.u.sdi.pad_off_pe;
pad_off_pu = display->hw_config.u.sdi.pad_off_pu;
req_map = (1 << (data_pairs * 2)) - 1; /* data lanes */
req_map |= 3 << 6; /* clk lane */
for (i = 0; i < ARRAY_SIZE(sdi_pads); i++) {
u32 reg;
u16 val;
if (!((1 << i) & req_map))
continue;
if (enable)
val = OMAP_SDI_PAD_EN;
else
val = OMAP_SDI_PAD_DIS(pad_off_pe, pad_off_pu);
reg = CONTROL_PADCONF_BASE + sdi_pads[i];
omap_writew(val, reg);
}
}
/*
* Common low-level hardware init for omap1.
*/
void omap1_init_early(void)
{
omap_check_revision();
/* REVISIT: Refer to OMAP5910 Errata, Advisory SYS_1: "Timeout Abort
* on a Posted Write in the TIPB Bridge".
*/
omap_writew(0x0, MPU_PUBLIC_TIPB_CNTL);
omap_writew(0x0, MPU_PRIVATE_TIPB_CNTL);
/* Must init clocks early to assure that timer interrupt works
*/
omap1_clk_init();
omap1_mux_init();
omap_init_consistent_dma_size();
}
static irqreturn_t omap_kp_interrupt(int irq, void *dev_id)
{
struct omap_kp *omap_kp = dev_id;
unsigned long flags;
spin_lock_irqsave(&omap_kp->suspend_lock, flags);
if (omap_kp->suspended) {
spin_unlock_irqrestore(&omap_kp->suspend_lock, flags);
return IRQ_HANDLED;
}
spin_unlock_irqrestore(&omap_kp->suspend_lock, flags);
/* disable keyboard interrupt and schedule for handling */
if (cpu_is_omap24xx()) {
int i;
for (i = 0; i < omap_kp->rows; i++)
disable_irq(OMAP_GPIO_IRQ(row_gpios[i]));
} else
/* disable keyboard interrupt and schedule for handling */
omap_writew(1, OMAP_MPUIO_BASE + OMAP_MPUIO_KBD_MASKIT);
tasklet_schedule(&kp_tasklet);
return IRQ_HANDLED;
}
static int __init omap_init_lcd_dma(void)
{
int r;
if (!cpu_class_is_omap1())
return -ENODEV;
if (cpu_is_omap16xx()) {
u16 w;
/* this would prevent OMAP sleep */
w = omap_readw(OMAP1610_DMA_LCD_CTRL);
w &= ~(1 << 8);
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
}
spin_lock_init(&lcd_dma.lock);
r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
"LCD DMA", NULL);
if (r != 0)
printk(KERN_ERR "unable to request IRQ for LCD DMA "
"(error %d)\n", r);
return r;
}
static irqreturn_t omap_kp_interrupt(int irq, void *dev_id)
{
struct omap_kp *omap_kp = dev_id;
/* disable keyboard interrupt and schedule for handling */
if (cpu_is_omap24xx()) {
int i;
for (i = 0; i < omap_kp->rows; i++) {
int gpio_irq = gpio_to_irq(row_gpios[i]);
/*
* The interrupt which we're currently handling should
* be disabled _nosync() to avoid deadlocks waiting
* for this handler to complete. All others should
* be disabled the regular way for SMP safety.
*/
if (gpio_irq == irq)
disable_irq_nosync(gpio_irq);
else
disable_irq(gpio_irq);
}
} else
/* disable keyboard interrupt and schedule for handling */
omap_writew(1, OMAP1_MPUIO_BASE + OMAP_MPUIO_KBD_MASKIT);
tasklet_schedule(&kp_tasklet);
return IRQ_HANDLED;
}
static int
__ck_set_pll_rate(ck_t ck, int rate)
{
unsigned short pll;
unsigned long flags;
if ((rate < 0) || (rate > CK_MAX_PLL_FREQ))
return -EINVAL;
/* Scan downward for the closest matching frequency */
while (rate && !test_bit(rate, (unsigned long *)&ck_valid_table))
rate--;
if (!rate) {
printk(KERN_ERR "%s: couldn't find a matching rate\n",
__FUNCTION__);
return -EINVAL;
}
spin_lock_irqsave(&clock_lock, flags);
pll = omap_readw(CK_RATE_REG(ck));
/* Clear the rate bits */
pll &= ~(0x1f << 5);
/* Set the rate bits */
pll |= (ck_lookup_table[rate - 1] << 5);
omap_writew(pll, CK_RATE_REG(ck));
spin_unlock_irqrestore(&clock_lock, flags);
return 0;
}
int
ck_disable(ck_t ck)
{
unsigned short reg;
int ret = -EINVAL, shift;
unsigned long flags;
if (!CK_IN_RANGE(ck))
goto exit;
if (ck_debug)
printk(KERN_DEBUG "%s: %s\n", __FUNCTION__, CK_NAME(ck));
if (!CK_CAN_DISABLE(ck))
goto exit;
ret = 0;
if (ck == OMAP_CLKIN)
return -EINVAL;
spin_lock_irqsave(&clock_lock, flags);
reg = omap_readw(CK_ENABLE_REG(ck));
shift = CK_ENABLE_SHIFT(ck);
reg &= ~(1 << shift);
omap_writew(reg, CK_ENABLE_REG(ck));
spin_unlock_irqrestore(&clock_lock, flags);
exit:
return ret;
}
static int __devexit omap_kp_remove(struct platform_device *pdev)
{
struct omap_kp *omap_kp = platform_get_drvdata(pdev);
/* disable keypad interrupt handling */
tasklet_disable(&kp_tasklet);
if (cpu_is_omap24xx()) {
int i;
for (i = 0; i < omap_kp->cols; i++)
gpio_free(col_gpios[i]);
for (i = 0; i < omap_kp->rows; i++) {
gpio_free(row_gpios[i]);
free_irq(gpio_to_irq(row_gpios[i]), omap_kp);
}
} else {
omap_writew(1, OMAP1_MPUIO_BASE + OMAP_MPUIO_KBD_MASKIT);
free_irq(omap_kp->irq, omap_kp);
}
del_timer_sync(&omap_kp->timer);
tasklet_kill(&kp_tasklet);
/* unregister everything */
input_unregister_device(omap_kp->input);
kfree(omap_kp);
return 0;
}
static int twl4030_set_host(struct otg_transceiver *x, struct usb_bus *host)
{
struct twl4030_usb *twl;
if (!x)
return -ENODEV;
twl = xceiv_to_twl(x);
if (!host) {
omap_writew(0, OTG_IRQ_EN);
twl4030_phy_suspend(twl, 1);
twl->otg.host = NULL;
return -ENODEV;
}
twl->otg.host = host;
twl4030_phy_resume(twl);
twl4030_usb_set_bits(twl, TWL4030_OTG_CTRL,
TWL4030_OTG_CTRL_DMPULLDOWN
| TWL4030_OTG_CTRL_DPPULLDOWN);
twl4030_usb_set_bits(twl, FUNC_CTRL, FUNC_CTRL_SUSPENDM);
twl4030_usb_set_bits(twl, TWL4030_OTG_CTRL, TWL4030_OTG_CTRL_DRVVBUS);
return 0;
}
static int twl4030_set_peripheral(struct otg_transceiver *x,
struct usb_gadget *gadget)
{
struct twl4030_usb *twl;
u32 l;
if (!x)
return -ENODEV;
twl = xceiv_to_twl(x);
if (!gadget) {
omap_writew(0, OTG_IRQ_EN);
twl4030_phy_suspend(twl, 1);
twl->otg.gadget = NULL;
return -ENODEV;
}
twl->otg.gadget = gadget;
twl4030_phy_resume(twl);
l = omap_readl(OTG_CTRL) & OTG_CTRL_MASK;
l &= ~(OTG_XCEIV_OUTPUTS|OTG_CTRL_BITS);
l |= OTG_ID;
omap_writel(l, OTG_CTRL);
twl->otg.state = OTG_STATE_B_IDLE;
return 0;
}
static void __init htcoxygen_spi_mux(void)
{
/* Setup MUX config for SPI */
omap_writel(omap_readl(OMAP850_IO_CONF_6) | 0x00088880, OMAP850_IO_CONF_6);
omap_writel(omap_readl(OMAP850_IO_CONF_6) & ~0x00077770, OMAP850_IO_CONF_6);
omap_writel(omap_readl(OMAP850_IO_CONF_8) | 0x01000000, OMAP850_IO_CONF_8);
omap_writel(omap_readl(OMAP850_IO_CONF_8) & ~0x10110000, OMAP850_IO_CONF_8);
omap_writel(omap_readl(OMAP850_IO_CONF_9) | 0x00000010, OMAP850_IO_CONF_9);
omap_writel(omap_readl(OMAP850_IO_CONF_9) & ~0x00000001, OMAP850_IO_CONF_9);
/* configure spi setup registers */
omap_writew(0xfffe, OMAP850_SPI2_BASE + 0x02);
omap_writew(0x0000, OMAP850_SPI2_BASE + 0x08);
omap_writew(0x7ff8, OMAP850_SPI2_BASE + 0x0e);
}
static int omap_mux_disable_wakeup(const char *muxname)
{
u16 val = 0;
val = omap_readw(CA_WAKE_MUX_REG);
val &= ~OMAP44XX_PADCONF_WAKEUPENABLE0;
omap_writew(val, CA_WAKE_MUX_REG);
return 0;
}
void __init mapphone_padconf_init(void)
{
int i;
#ifdef CONFIG_ARM_OF
mux_setting_init();
#endif
touch_int_fix();
for (i = 0; i < ARRAY_SIZE(padconf_settings); i++) {
if (is_omap343x_padconf_register(padconf_settings[i].offset)) {
unsigned long addr = padconf_settings[i].offset
+ OMAP343X_CTRL_BASE;
/*
despite the w, omap_readw actual reads a short which
is a half word on this architecture
*/
unsigned short val = omap_readw(addr);
#ifdef CONFIG_EMU_UART_DEBUG
if (is_emu_uart_iomux_reg(padconf_settings[i].offset)) {
printk(KERN_ERR "padconf ignored, offset = 0x%04x\n",
padconf_settings[i].offset);
continue;
}
#endif
val &= ~(OMAP343X_PADCONF_SETTING_MASK);
val |= padconf_settings[i].setting;
/* the SIM mux settings are for OMAP3430 */
if ((padconf_settings[i].offset == 0x150) ||
(padconf_settings[i].offset == 0x152) ||
(padconf_settings[i].offset == 0x154) ||
(padconf_settings[i].offset == 0x156)) {
if (cpu_is_omap3630())
continue;
}
/* the SIM mux settings are for OMAP3630 */
if ((padconf_settings[i].offset == 0xa54) ||
(padconf_settings[i].offset == 0xa56) ||
(padconf_settings[i].offset == 0xa58) ||
(padconf_settings[i].offset == 0xa5a)) {
if (cpu_is_omap3430())
continue;
}
omap_writew(val, addr);
} else {
printk(KERN_ERR "padconf check failed, offset = 0x%04x\n",
padconf_settings[i].offset);
}
}
return;
}
static int aat2862_suspend(struct i2c_client *client, pm_message_t state)
{
//printk(KERN_INFO"%s: new state: %d\n",__func__, state.event);
// 20100630 [email protected] Hub touchscreen power sequence [START_LGE]
aat2862_touch_ldo_enable(client, 0);
// 20100630 [email protected] Hub touchscreen power sequence [END_LGE]
// 20101016 [email protected] Turn off unnecessary modules upon BL off [START_LGE]
#if 0 // Followings reduces around 20uA.
gpio_direction_output(MY_HDMI_REG_EN, 0);
gpio_set_value(MY_HDMI_REG_EN, 0);
gpio_direction_output(MY_CAM_SUBPM_EN, 0);
gpio_set_value(MY_CAM_SUBPM_EN, 0);
gpio_direction_output(MY_CAM_VCM_EN, 0);
gpio_set_value(MY_CAM_VCM_EN, 0);
gpio_direction_output(MY_DMB_EN, 0);
gpio_set_value(MY_DMB_EN, 0);
gpio_direction_output(MY_MOTION_INT, 0);
gpio_direction_output(MY_COM_INT, 0);
#endif
#if 0 // Followings reduces around 60uA.
i2c3_scl = omap_readw(0x480021C2); // sookyoung.kim
i2c3_sda = omap_readw(0x480021C4); // sookyoung.kim
omap_writew(0x0000, 0x480021C2); // sookyoung.kim
omap_writew(0x0000, 0x480021C4); // sookyoung.kim
#endif
#if 0 // Followings, coupled with memory refresh rate control, reduces around 600uA.
i2c4_scl = omap_readw(0x48002A00); // sookyoung.kim
i2c4_sda = omap_readw(0x48002A02); // sookyoung.kim
omap_writew(0x0000, 0x48002A00); // sookyoung.kim
omap_writew(0x0000, 0x48002A02); // sookyoung.kim
#endif
// 20101016 [email protected] Turn off unnecessary modules upon BL off [END_LGE]
client->dev.power.power_state = state;
aat2862_write_reg(client, 0x02, 0x00);
gpio_direction_output(MY_LCD_CP_EN, 0);
gpio_set_value(MY_LCD_CP_EN, 0);
return 0;
}
static irqreturn_t omap_otg_irq(int irq, void *arg)
{
u16 otg_irq;
otg_irq = omap_readw(OTG_IRQ_SRC);
if (otg_irq & OPRT_CHG) {
omap_writew(OPRT_CHG, OTG_IRQ_SRC);
} else if (otg_irq & B_SRP_TMROUT) {
omap_writew(B_SRP_TMROUT, OTG_IRQ_SRC);
} else if (otg_irq & B_HNP_FAIL) {
omap_writew(B_HNP_FAIL, OTG_IRQ_SRC);
} else if (otg_irq & A_SRP_DETECT) {
omap_writew(A_SRP_DETECT, OTG_IRQ_SRC);
} else if (otg_irq & A_REQ_TMROUT) {
omap_writew(A_REQ_TMROUT, OTG_IRQ_SRC);
} else if (otg_irq & A_VBUS_ERR) {
omap_writew(A_VBUS_ERR, OTG_IRQ_SRC);
} else if (otg_irq & DRIVER_SWITCH) {
#ifdef CONFIG_USB_OTG
if ((!(omap_readl(OTG_CTRL) & OTG_DRIVER_SEL)) &&
tu->otg.host && tu->otg.state == OTG_STATE_A_HOST) {
/* role is host */
usb_bus_start_enum(tu->otg.host,
tu->otg.host->otg_port);
}
#endif
omap_writew(DRIVER_SWITCH, OTG_IRQ_SRC);
} else
return IRQ_NONE;
return IRQ_HANDLED;
}
