INT32 _stp_trigger_firmware_assert_via_emi(VOID)
{
UINT8 * p_virtual_addr = NULL;
INT32 status = -1;
INT32 i = 0, j = 0;
do {
STP_BTM_INFO_FUNC("[Force Assert] stp_trigger_firmware_assert_via_emi -->\n");
p_virtual_addr = wmt_plat_get_emi_virt_add(EXP_APMEM_CTRL_HOST_OUTBAND_ASSERT_W1);
if(!p_virtual_addr)
{
STP_BTM_ERR_FUNC("get virtual address fail\n");
return -1;
}
CONSYS_REG_WRITE(p_virtual_addr, EXP_APMEM_HOST_OUTBAND_ASSERT_MAGIC_W1);
STP_BTM_INFO_FUNC("[Force Assert] stp_trigger_firmware_assert_via_emi <--\n");
#if 1
//wait for firmware assert
osal_msleep(50);
//if firmware is not assert self, host driver helps it.
do
{
if(0 != mtk_wcn_stp_coredump_start_get()){
status = 0;
break;
}
mtk_wcn_stp_wakeup_consys();
STP_BTM_INFO_FUNC("[Force Assert] wakeup consys (%d)\n", i);
stp_dbg_poll_cpupcr(5 , 1 , 1);
osal_msleep(5);
i++;
if(i > 20){
i = 0;
break;
}
} while(1);
#endif
if(0 != mtk_wcn_stp_coredump_start_get()){
status = 0;
break;
}
j++;
if(j > 8) {
j = 0;
break;
}
} while(1);
return status;
}
HI_S32 HAL_Efuse_WaitReady(HI_VOID)
{
U_CIPHER_KD_STA efuse_sta;
HI_U32 ulStartTime = 0;
HI_U32 ulLastTime = 0;
HI_U32 ulDuraTime = 0;
ulStartTime = osal_get_tickcount();
while(1)
{
efuse_sta.u32 = EFUSE_REG(CIPHER_KD_STA);
if(efuse_sta.bits.ctrl_rdy && (!efuse_sta.bits.ctrl_busy1) && (!efuse_sta.bits.ctrl_busy0))
{
break;
}
ulLastTime = osal_get_tickcount();
ulDuraTime = (ulLastTime - ulStartTime);
if (ulDuraTime >= 50000 )
{
HI_ERR_CIPHER("Error! efuse load key out!\n");
return HI_FAILURE;
}
osal_msleep(1);
}
return HI_SUCCESS;
}
HI_S32 HAL_Efuse_WaitWriteKey(HI_VOID)
{
U_CIPHER_KD_STA efuse_sta;
HI_U32 ulStartTime = 0;
HI_U32 ulLastTime = 0;
HI_U32 ulDuraTime = 0;
/* wait for hash_rdy */
ulStartTime = osal_get_tickcount();
while(1)
{
efuse_sta.u32 = EFUSE_REG(CIPHER_KD_STA);
if(efuse_sta.bits.key_wt_finish == 1)
{
break;
}
ulLastTime = osal_get_tickcount();
ulDuraTime = ulLastTime - ulStartTime;
if (ulDuraTime >= 50000 )
{
HI_ERR_CIPHER("Error! efuse write key time out!\n");
return HI_FAILURE;
}
osal_msleep(1);
}
return HI_SUCCESS;
}
INT32 _stp_trigger_firmware_assert_via_emi(VOID)
{
INT32 status = -1;
INT32 j = 0;
CONSYS_REG_WRITE(CONSYS_AP2CONN_OSC_EN_REG,CONSYS_REG_READ(CONSYS_AP2CONN_OSC_EN_REG) & ~CONSYS_AP2CONN_WAKEUP_BIT);
STP_BTM_INFO_FUNC("enable:dump CONSYS_AP2CONN_OSC_EN_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_AP2CONN_OSC_EN_REG));
usleep_range(64, 96);
CONSYS_REG_WRITE(CONSYS_AP2CONN_OSC_EN_REG,CONSYS_REG_READ(CONSYS_AP2CONN_OSC_EN_REG) | CONSYS_AP2CONN_WAKEUP_BIT);
STP_BTM_INFO_FUNC("disable:dump CONSYS_AP2CONN_OSC_EN_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_AP2CONN_OSC_EN_REG));
do {
if(0 != mtk_wcn_stp_coredump_start_get()){
status = 0;
break;
}
stp_dbg_poll_cpupcr(5 , 1 , 1);
j++;
STP_BTM_INFO_FUNC("Wait for assert message (%d)\n", j);
osal_msleep(20);
if(j > 8)
break;
} while(1);
return status;
}
static int hif_sdio_proc(void *pvData)
{
while (!kthread_should_stop()) {
/* HIF_SDIO_INFO_FUNC("enter sleep.\n"); */
osal_msleep(10000);
/* HIF_SDIO_INFO_FUNC("wakeup\n"); */
}
HIF_SDIO_INFO_FUNC("hifsdiod exit.\n");
return 0;
}
INT32
mtk_wcn_cmb_hw_rst (VOID)
{
INT32 iRet = 0;
WMT_INFO_FUNC("CMB-HW, hw_rst start, eirq should be disabled before this step\n");
/*1. PMU->output low, RST->output low, sleep off stable time*/
iRet += wmt_plat_gpio_ctrl(PIN_PMU, PIN_STA_OUT_L);
iRet += wmt_plat_gpio_ctrl(PIN_RST, PIN_STA_OUT_L);
osal_msleep(gPwrSeqTime.offStableTime);
/*2. PMU->output high, sleep rst stable time*/
iRet += wmt_plat_gpio_ctrl(PIN_PMU, PIN_STA_OUT_H);
osal_msleep(gPwrSeqTime.rstStableTime);
/*3. RST->output high, sleep on stable time*/
iRet += wmt_plat_gpio_ctrl(PIN_RST, PIN_STA_OUT_H);
osal_msleep(gPwrSeqTime.onStableTime);
WMT_INFO_FUNC("CMB-HW, hw_rst finish, eirq should be enabled after this step\n");
return 0;
}
static INT32 _stp_btm_put_dump_to_aee(void)
{
static UINT8 buf[2048];
static UINT8 tmp[2048];
UINT32 buf_len;
STP_PACKET_T *pkt;
STP_DBG_HDR_T *hdr;
INT32 remain = 0;
INT32 retry = 0;
INT32 ret = 0;
STP_BTM_INFO_FUNC("Enter..\n");
do {
remain = stp_dbg_dmp_out_ex(&buf[0], &buf_len);
if (buf_len > 0) {
pkt = (STP_PACKET_T*)buf;
hdr = &pkt->hdr;
if (hdr->dbg_type == STP_DBG_FW_DMP) {
osal_memcpy(&tmp[0], pkt->raw, pkt->hdr.len);
if (pkt->hdr.len <= 1500) {
tmp[pkt->hdr.len] = '\n';
tmp[pkt->hdr.len + 1] = '\0';
ret = stp_dbg_aee_send(tmp, pkt->hdr.len, 0);
} else {
STP_BTM_INFO_FUNC("dump entry length is over long\n");
osal_bug_on(0);
}
retry = 0;
}
} else {
retry ++;
osal_msleep(100);
}
}while ((remain > 0) || (retry < 2));
STP_BTM_INFO_FUNC("Exit..\n");
return ret;
}
INT32 wmt_dbg_assert_test(INT32 par1, INT32 par2, INT32 par3)
{
if (0 == par3)
{
//par2 = 0: send assert command
//par2 != 0: send exception command
return wmt_dbg_cmd_test_api(0 == par2 ? 0 : 1);
}
else
{
INT32 sec = 8;
INT32 times = 0;
times = par3;
do{
WMT_INFO_FUNC("Send Assert Command per 8 secs!!\n");
wmt_dbg_cmd_test_api(0);
osal_msleep(sec * 1000);
}while(--times);
}
return 0;
}
INT32 mtk_wcn_hif_sdio_query_chipid(INT32 waitFlag)
{
UINT32 timeSlotMs = 200;
UINT32 maxTimeSlot = 15;
UINT32 counter = 0;
/* gComboChipId = 0x6628; */
if (0 == waitFlag)
return gComboChipId;
if (0 <= hif_sdio_is_chipid_valid(gComboChipId))
return gComboChipId;
wmt_plat_pwr_ctrl(FUNC_ON);
wmt_plat_sdio_ctrl(WMT_SDIO_SLOT_SDIO1, FUNC_ON);
while (counter < maxTimeSlot) {
if (0 <= hif_sdio_is_chipid_valid(gComboChipId))
break;
osal_msleep(timeSlotMs);
counter++;
}
wmt_plat_sdio_ctrl(WMT_SDIO_SLOT_SDIO1, FUNC_OFF);
wmt_plat_pwr_ctrl(FUNC_OFF);
return gComboChipId;
}
INT32 _stp_trigger_firmware_assert_via_emi(VOID)
{
INT32 status = -1;
INT32 j = 0;
wmt_plat_force_trigger_assert(STP_FORCE_TRG_ASSERT_DEBUG_PIN);
do {
if(0 != mtk_wcn_stp_coredump_start_get()){
status = 0;
break;
}
stp_dbg_poll_cpupcr(5 , 1 , 1);
j++;
STP_BTM_INFO_FUNC("Wait for assert message (%d)\n", j);
osal_msleep(20);
if(j > 24)
break;
} while(1);
return status;
}
INT32
mtk_wcn_cmb_hw_pwr_on (VOID)
{
static UINT32 _pwr_first_time = 1;
INT32 iRet = 0;
WMT_INFO_FUNC("CMB-HW, hw_pwr_on start\n");
#if 0 //IRQ should in inact state before power on, so this step is not needed
/* disable interrupt firstly */
iRet += wmt_plat_eirq_ctrl(PIN_BGF_EINT, PIN_STA_EINT_DIS);
iRet += wmt_plat_eirq_ctrl(PIN_ALL_EINT, PIN_STA_EINT_DIS);
#endif
/*set all control and eint gpio to init state, namely input low mode*/
iRet += wmt_plat_gpio_ctrl(PIN_LDO, PIN_STA_INIT);
iRet += wmt_plat_gpio_ctrl(PIN_PMU, PIN_STA_INIT);
iRet += wmt_plat_gpio_ctrl(PIN_RST, PIN_STA_INIT);
iRet += wmt_plat_gpio_ctrl(PIN_SDIO_GRP, PIN_STA_INIT);
iRet += wmt_plat_gpio_ctrl(PIN_BGF_EINT, PIN_STA_INIT);
iRet += wmt_plat_gpio_ctrl(PIN_ALL_EINT, PIN_STA_INIT);
iRet += wmt_plat_gpio_ctrl(PIN_GPS_SYNC, PIN_STA_INIT);
iRet += wmt_plat_gpio_ctrl(PIN_GPS_LNA, PIN_STA_INIT);
// wmt_plat_gpio_ctrl(PIN_WIFI_EINT, PIN_STA_INIT); /* WIFI_EINT is controlled by SDIO host driver */
// TODO: [FixMe][George]:WIFI_EINT is used in common SDIO
/*1. pull high LDO to supply power to chip*/
iRet += wmt_plat_gpio_ctrl(PIN_LDO, PIN_STA_OUT_H);
osal_msleep(gPwrSeqTime.ldoStableTime);
/* 2. export RTC clock to chip*/
if (_pwr_first_time) {
/* rtc clock should be output all the time, so no need to enable output again*/
iRet += wmt_plat_gpio_ctrl(PIN_RTC, PIN_STA_INIT);
osal_msleep(gPwrSeqTime.rtcStableTime);
WMT_INFO_FUNC("CMB-HW, rtc clock exported\n");
}
/*3. set UART Tx/Rx to UART mode*/
iRet += wmt_plat_gpio_ctrl(PIN_UART_GRP, PIN_STA_INIT);
/*4. PMU->output low, RST->output low, sleep off stable time*/
iRet += wmt_plat_gpio_ctrl(PIN_PMU, PIN_STA_OUT_L);
iRet += wmt_plat_gpio_ctrl(PIN_RST, PIN_STA_OUT_L);
osal_msleep(gPwrSeqTime.offStableTime);
/*5. PMU->output high, sleep rst stable time*/
iRet += wmt_plat_gpio_ctrl(PIN_PMU, PIN_STA_OUT_H);
osal_msleep(gPwrSeqTime.rstStableTime);
/*6. RST->output high, sleep on stable time*/
iRet += wmt_plat_gpio_ctrl(PIN_RST, PIN_STA_OUT_H);
osal_msleep(gPwrSeqTime.onStableTime);
/*7. set audio interface to CMB_STUB_AIF_1, BT PCM ON, I2S OFF*/
/* BT PCM bus default mode. Real control is done by audio */
iRet += wmt_plat_audio_ctrl(CMB_STUB_AIF_1, CMB_STUB_AIF_CTRL_DIS);
/*8. set EINT< -ommited-> move this to WMT-IC module, where common sdio interface will be identified and do proper operation*/
// TODO: [FixMe][GeorgeKuo] double check if BGF_INT is implemented ok
iRet += wmt_plat_gpio_ctrl(PIN_BGF_EINT, PIN_STA_MUX);
iRet += wmt_plat_eirq_ctrl(PIN_BGF_EINT, PIN_STA_INIT);
iRet += wmt_plat_eirq_ctrl(PIN_BGF_EINT, PIN_STA_EINT_DIS);
WMT_INFO_FUNC("CMB-HW, BGF_EINT IRQ registered and disabled \n");
/* 8.1 set ALL_EINT pin to correct state even it is not used currently */
iRet += wmt_plat_gpio_ctrl(PIN_ALL_EINT, PIN_STA_MUX);
iRet += wmt_plat_eirq_ctrl(PIN_ALL_EINT, PIN_STA_INIT);
iRet += wmt_plat_eirq_ctrl(PIN_ALL_EINT, PIN_STA_EINT_DIS);
WMT_INFO_FUNC("CMB-HW, hw_pwr_on finish (%d)\n", iRet);
_pwr_first_time = 0;
return iRet;
}
INT32 wmt_ctrl_sdio_func(P_WMT_CTRL_DATA pWmtCtrlData)
{
INT32 iRet = -1;
UINT32 statBit = WMT_STAT_SDIO_WIFI_ON;
INT32 retry = 10;
P_DEV_WMT pDev = &gDevWmt; /* single instance */
WMT_SDIO_FUNC_TYPE sdioFuncType = pWmtCtrlData->au4CtrlData[0];
UINT32 u4On = pWmtCtrlData->au4CtrlData[1];
if (WMT_SDIO_FUNC_MAX <= sdioFuncType) {
WMT_ERR_FUNC("CTRL_SDIO_FUNC, invalid func type (%d) \n", sdioFuncType);
return -1;
}
if (WMT_SDIO_FUNC_STP == sdioFuncType) {
statBit = WMT_STAT_SDIO_STP_ON;
}
if (u4On) {
if (osal_test_bit(statBit, &pDev->state)) {
WMT_WARN_FUNC("CTRL_SDIO_FUNC(%d) but already ON \n", sdioFuncType);
iRet = 0;
}
else {
while (retry-- > 0 && iRet != 0) {
if (iRet) {
/* sleep 150ms before sdio slot ON ready */
osal_msleep(150);
}
iRet = mtk_wcn_hif_sdio_wmt_control(sdioFuncType, MTK_WCN_BOOL_TRUE);
if (HIF_SDIO_ERR_NOT_PROBED == iRet) {
/* not probed case, retry */
continue;
}
else if (HIF_SDIO_ERR_CLT_NOT_REG == iRet){
/* For WiFi, client not reg yet, no need to retry, WiFi function can work any time when wlan.ko is insert into system*/
iRet = 0;
}
else
{
/* other fail cases, stop */
break;
}
}
if (!retry || iRet) {
WMT_ERR_FUNC("mtk_wcn_hif_sdio_wmt_control(%d, TRUE) fail(%d) retry(%d)\n", sdioFuncType, iRet, retry);
}
else
{
osal_set_bit(statBit, &pDev->state);
}
}
}
else {
if (osal_test_bit(statBit, &pDev->state)) {
iRet = mtk_wcn_hif_sdio_wmt_control(sdioFuncType, MTK_WCN_BOOL_FALSE);
if (iRet) {
WMT_ERR_FUNC("mtk_wcn_hif_sdio_wmt_control(%d, FALSE) fail(%d)\n", sdioFuncType, iRet);
}
/*any way, set to OFF state*/
osal_clear_bit(statBit, &pDev->state);
}
else {
WMT_WARN_FUNC("CTRL_SDIO_FUNC(%d) but already OFF \n", sdioFuncType);
iRet = 0;
}
}
return iRet;
}
static INT32 _stp_btm_put_dump_to_nl(void)
{
#define NUM_FETCH_ENTRY 8
static UINT8 buf[2048];
static UINT8 tmp[2048];
UINT32 buf_len;
STP_PACKET_T *pkt;
STP_DBG_HDR_T *hdr;
INT32 remain=0, index =0;
INT32 retry = 0, rc = 0, nl_retry = 0;
STP_BTM_INFO_FUNC("Enter..\n");
index = 0;
tmp[index++]='[';
tmp[index++]='M';
tmp[index++]=']';
do
{
index = 3;
remain = stp_dbg_dmp_out_ex(&buf[0], &buf_len);
if (buf_len > 0)
{
pkt = (STP_PACKET_T *)buf;
hdr = &pkt->hdr;
if (hdr->dbg_type == STP_DBG_FW_DMP){
osal_memcpy(&tmp[index], pkt->raw, pkt->hdr.len);
if(pkt->hdr.len <= 1500)
{
tmp[index + pkt->hdr.len] = '\n';
tmp[index + pkt->hdr.len + 1] = '\0';
//printk("\n%s\n+++\n", tmp);
rc = stp_dbg_nl_send((PCHAR)&tmp, 2);
while(rc){
nl_retry++;
if(nl_retry > 1000){
break;
}
STP_BTM_WARN_FUNC("**dump send fails, and retry again.**\n");
osal_msleep(3);
rc = stp_dbg_nl_send((PCHAR)&tmp, 2);
if(!rc){
STP_BTM_WARN_FUNC("****retry again ok!**\n");
}
}
//schedule();
} else {
STP_BTM_INFO_FUNC("dump entry length is over long\n");
osal_bug_on(0);
}
retry = 0;
}
}else
{
retry ++;
osal_msleep(100);
}
}while((remain > 0) || (retry < 2));
STP_BTM_INFO_FUNC("Exit..\n");
return 0;
}
static INT32 _stp_btm_handler(MTKSTP_BTM_T *stp_btm, P_STP_BTM_OP pStpOp)
{
INT32 ret = -1;
INT32 dump_sink = 1; //core dump target, 0: aee; 1: netlink
static UINT32 counter = 0;
UINT32 full_dump_left = STP_FULL_DUMP_TIME;
UINT32 page_counter = 0;
ENUM_STP_FW_ISSUE_TYPE issue_type;
if (NULL == pStpOp)
{
return -1;
}
switch(pStpOp->opId)
{
case STP_OPID_BTM_EXIT:
// TODO: clean all up?
ret = 0;
break;
/*tx timeout retry*/
case STP_OPID_BTM_RETRY:
stp_do_tx_timeout();
ret = 0;
break;
/*whole chip reset*/
case STP_OPID_BTM_RST:
STP_BTM_INFO_FUNC("whole chip reset start!\n");
STP_BTM_INFO_FUNC("....+\n");
if(stp_btm->wmt_notify)
{
stp_btm->wmt_notify(BTM_RST_OP);
ret = 0;
}
else
{
STP_BTM_ERR_FUNC("stp_btm->wmt_notify is NULL.");
ret = -1;
}
STP_BTM_INFO_FUNC("whole chip reset end!\n");
break;
case STP_OPID_BTM_DBG_DUMP:
/*Notify the wmt to get dump data*/
STP_BTM_DBG_FUNC("wmt dmp notification\n");
dump_sink = ((stp_btm->wmt_notify(BTM_GET_AEE_SUPPORT_FLAG) == MTK_WCN_BOOL_TRUE) ? 0 : 1);
if (dump_sink == 0) {
_stp_btm_put_dump_to_aee();
} else if (dump_sink == 1) {
_stp_btm_put_dump_to_nl();
} else {
STP_BTM_ERR_FUNC("unknown sink %d\n", dump_sink);
}
break;
case STP_OPID_BTM_DUMP_TIMEOUT:
// Flush dump data, and reset compressor
STP_BTM_INFO_FUNC("Flush dump data\n");
wcn_core_dump_flush(0);
break;
case STP_OPID_BTM_POLL_CPUPCR:
do{
UINT32 times;
UINT32 sleep;
times = pStpOp->au4OpData[0];
sleep = pStpOp->au4OpData[1];
ret = stp_dbg_poll_cpupcr(times, sleep,0);
}while(0);
break;
case STP_OPID_BTM_PAGED_DUMP:
g_paged_dump_len = 0;
issue_type = STP_FW_ASSERT_ISSUE;
wmt_plat_set_host_dump_state(STP_HOST_DUMP_NOT_START);
page_counter = 0;
do{
UINT32 loop_cnt1 = 0;
UINT32 loop_cnt2 = 0;
ENUM_HOST_DUMP_STATE host_state;
ENUM_CHIP_DUMP_STATE chip_state;
UINT32 dump_phy_addr = 0;
UINT8 *dump_vir_addr = NULL;
UINT32 dump_len = 0;
UINT32 isEnd = 0;
P_CONSYS_EMI_ADDR_INFO p_emi_ctrl_state_info;
p_emi_ctrl_state_info = wmt_plat_get_emi_phy_add();
osal_assert(p_emi_ctrl_state_info);
host_state = (ENUM_HOST_DUMP_STATE)wmt_plat_get_dump_info(p_emi_ctrl_state_info->p_emi_ctrl_state_offset->emi_apmem_ctrl_host_sync_state);
if(STP_HOST_DUMP_NOT_START == host_state)
{
counter++;
STP_BTM_INFO_FUNC("counter(%d)\n",counter);
osal_msleep(100);
}
else
{
counter = 0;
}
while(1)
{
chip_state = (ENUM_CHIP_DUMP_STATE)wmt_plat_get_dump_info(p_emi_ctrl_state_info->p_emi_ctrl_state_offset->emi_apmem_ctrl_chip_sync_state);
if(STP_CHIP_DUMP_PUT_DONE == chip_state){
STP_BTM_INFO_FUNC("chip put done\n");
break;
}
else
{
STP_BTM_INFO_FUNC("waiting chip put done\n");
loop_cnt1 ++;
osal_msleep(5);
}
if(loop_cnt1 > 10)
goto paged_dump_end;
}
wmt_plat_set_host_dump_state(STP_HOST_DUMP_GET);
dump_phy_addr = wmt_plat_get_dump_info(p_emi_ctrl_state_info->p_emi_ctrl_state_offset->emi_apmem_ctrl_chip_sync_addr);
if(!dump_phy_addr)
{
STP_BTM_ERR_FUNC("get paged dump phy address fail\n");
ret = -1;
break;
}
dump_vir_addr = wmt_plat_get_emi_virt_add(dump_phy_addr - p_emi_ctrl_state_info->emi_phy_addr);
if(!dump_vir_addr)
{
STP_BTM_ERR_FUNC("get paged dump phy address fail\n");
ret = -2;
break;
}
dump_len = wmt_plat_get_dump_info(p_emi_ctrl_state_info->p_emi_ctrl_state_offset->emi_apmem_ctrl_chip_sync_len);
STP_BTM_INFO_FUNC("dump_phy_ddr(%08x),dump_vir_add(0x%p),dump_len(%d)\n",dump_phy_addr,dump_vir_addr,dump_len);
/*move dump info according to dump_addr & dump_len*/
#if 1
osal_memcpy(&g_paged_dump_buffer[0],dump_vir_addr,dump_len);
_stp_dump_emi_dump_buffer(&g_paged_dump_buffer[0],dump_len);
if(0 == page_counter)//do fw assert infor paser in first paged dump
{
if(1 == stp_dbg_get_host_trigger_assert())
{
issue_type = STP_HOST_TRIGGER_FW_ASSERT;
}
ret = stp_dbg_set_fw_info(&g_paged_dump_buffer[0],512,issue_type);
if(ret)
{
STP_BTM_ERR_FUNC("set fw issue infor fail(%d),maybe fw warm reset...\n",ret);
stp_dbg_set_fw_info("Fw Warm reset",osal_strlen("Fw Warm reset"),STP_FW_WARM_RST_ISSUE);
}
}
if(dump_len <= 32*1024){
ret = stp_dbg_aee_send(&g_paged_dump_buffer[0],dump_len, 0);
if(ret == 0){
STP_BTM_INFO_FUNC("aee send ok!\n");
} else if (ret == 1) {
STP_BTM_INFO_FUNC("aee send fisish!\n");
} else {
STP_BTM_ERR_FUNC("aee send error!\n");
}
} else {
STP_BTM_ERR_FUNC("dump len is over than 32K(%d)\n",dump_len);
}
g_paged_dump_len += dump_len;
STP_BTM_INFO_FUNC("dump len update(%d)\n",g_paged_dump_len);
#endif
wmt_plat_update_host_sync_num();
wmt_plat_set_host_dump_state(STP_HOST_DUMP_GET_DONE);
STP_BTM_INFO_FUNC("host sync num(%d),chip sync num(%d)\n",
wmt_plat_get_dump_info(p_emi_ctrl_state_info->p_emi_ctrl_state_offset->emi_apmem_ctrl_host_sync_num),
wmt_plat_get_dump_info(p_emi_ctrl_state_info->p_emi_ctrl_state_offset->emi_apmem_ctrl_chip_sync_num));
page_counter++;
STP_BTM_INFO_FUNC("\n\n++ paged dump counter(%d) ++\n\n\n",page_counter);
while(1)
{
chip_state = (ENUM_CHIP_DUMP_STATE)wmt_plat_get_dump_info(p_emi_ctrl_state_info->p_emi_ctrl_state_offset->emi_apmem_ctrl_chip_sync_state);
if(STP_CHIP_DUMP_END == chip_state)
{
STP_BTM_INFO_FUNC("chip put end\n");
wmt_plat_set_host_dump_state(STP_HOST_DUMP_END);
break;
}
else
{
STP_BTM_INFO_FUNC("waiting chip put end\n");
loop_cnt2++;
osal_msleep(10);
}
if(loop_cnt2 > 10)
goto paged_dump_end;
}
paged_dump_end:
wmt_plat_set_host_dump_state(STP_HOST_DUMP_NOT_START);
if(counter * 100 > STP_PAGED_DUMP_TIME_LIMIT)
{
isEnd = wmt_plat_get_dump_info(p_emi_ctrl_state_info->p_emi_ctrl_state_offset->emi_apmem_ctrl_chip_paded_dump_end);
if(isEnd)
{
STP_BTM_INFO_FUNC("paged dump end\n");
STP_BTM_INFO_FUNC("\n\n paged dump print ++ \n\n");
_stp_dump_emi_dump_buffer(&g_paged_dump_buffer[0],g_paged_dump_len);
STP_BTM_INFO_FUNC("\n\n paged dump print -- \n\n");
STP_BTM_INFO_FUNC("\n\n paged dump size = %d, paged dump page number = %d \n\n", g_paged_dump_len, page_counter);
counter = 0;
ret = 0;
break;
}
else
{
STP_BTM_ERR_FUNC("paged dump fail\n");
wmt_plat_set_host_dump_state(STP_HOST_DUMP_NOT_START);
stp_dbg_poll_cpupcr(5,5,0);
counter = 0;
ret = -1;
break;
}
}
}while(1);
break;
case STP_OPID_BTM_FULL_DUMP:
wmt_plat_set_host_dump_state(STP_HOST_DUMP_NOT_START);
do{
UINT32 loop_cnt1 = 0;
UINT32 loop_cnt2 = 0;
ENUM_CHIP_DUMP_STATE chip_state;
UINT32 dump_phy_addr = 0;
UINT8 *dump_vir_addr = NULL;
UINT32 dump_len = 0;
UINT32 isFail = 0;
P_CONSYS_EMI_ADDR_INFO p_emi_ctrl_state_info;
p_emi_ctrl_state_info = wmt_plat_get_emi_phy_add();
osal_assert(p_emi_ctrl_state_info);
while(1)
{
chip_state = (ENUM_CHIP_DUMP_STATE)wmt_plat_get_dump_info(p_emi_ctrl_state_info->p_emi_ctrl_state_offset->emi_apmem_ctrl_chip_sync_state);
if(STP_CHIP_DUMP_PUT_DONE == chip_state)
break;
else
{
loop_cnt1 ++;
osal_msleep(10);
}
if(loop_cnt1 > 10)
{
isFail = 1;
goto full_dump_end;
}
}
wmt_plat_set_host_dump_state(STP_HOST_DUMP_GET);
dump_phy_addr = wmt_plat_get_dump_info(p_emi_ctrl_state_info->p_emi_ctrl_state_offset->emi_apmem_ctrl_chip_sync_addr);
if(!dump_phy_addr)
{
STP_BTM_ERR_FUNC("get phy dump address fail\n");
ret = -1;
break;
}
dump_vir_addr = wmt_plat_get_emi_virt_add(dump_phy_addr - p_emi_ctrl_state_info->emi_phy_addr);
if(!dump_vir_addr)
{
STP_BTM_ERR_FUNC("get vir dump address fail\n");
ret = -2;
break;
}
dump_len = wmt_plat_get_dump_info(p_emi_ctrl_state_info->p_emi_ctrl_state_offset->emi_apmem_ctrl_chip_sync_len);
/*move dump info according to dump_addr & dump_len*/
wmt_plat_update_host_sync_num();
wmt_plat_set_host_dump_state(STP_HOST_DUMP_GET_DONE);
STP_BTM_INFO_FUNC("host sync num(%d),chip sync num(%d)\n",
wmt_plat_get_dump_info(p_emi_ctrl_state_info->p_emi_ctrl_state_offset->emi_apmem_ctrl_host_sync_num),
wmt_plat_get_dump_info(p_emi_ctrl_state_info->p_emi_ctrl_state_offset->emi_apmem_ctrl_chip_sync_num));
while(1)
{
chip_state = (ENUM_CHIP_DUMP_STATE)wmt_plat_get_dump_info(p_emi_ctrl_state_info->p_emi_ctrl_state_offset->emi_apmem_ctrl_chip_sync_state);
if(STP_CHIP_DUMP_END == chip_state)
{
wmt_plat_set_host_dump_state(STP_HOST_DUMP_END);
break;
}
else
{
loop_cnt2++;
osal_msleep(10);
}
if(loop_cnt2 > 10)
{
isFail = 1;
goto full_dump_end;
}
}
wmt_plat_set_host_dump_state(STP_HOST_DUMP_NOT_START);
full_dump_end:
if(isFail)
{
STP_BTM_ERR_FUNC("full dump fail\n");
wmt_plat_set_host_dump_state(STP_HOST_DUMP_NOT_START);
ret = -1;
break;
}
}while(--full_dump_left > 0);
if(0 == full_dump_left)
{
STP_BTM_INFO_FUNC("full dump end\n");
ret = 0;
}
break;
case STP_OPID_BTM_PAGED_TRACE:
g_paged_trace_len = 0;
do{
UINT32 ctrl_val = 0;
UINT32 loop_cnt1 = 0;
UINT32 buffer_start = 0;
UINT32 buffer_idx = 0;
UINT8 *dump_vir_addr = NULL;
P_CONSYS_EMI_ADDR_INFO p_emi_ctrl_state_info;
p_emi_ctrl_state_info = wmt_plat_get_emi_phy_add();
osal_assert(p_emi_ctrl_state_info);
while(loop_cnt1 < 10)
{
ctrl_val = wmt_plat_get_dump_info(p_emi_ctrl_state_info->p_emi_ctrl_state_offset->emi_apmem_ctrl_state);
if(0x8 == ctrl_val)
break;
else
{
osal_msleep(10);
loop_cnt1++;
}
}
if(loop_cnt1 >= 10)
{
STP_BTM_ERR_FUNC("polling CTRL STATE fail\n");
ret = -1;
break;
}
buffer_start = wmt_plat_get_dump_info(p_emi_ctrl_state_info->p_emi_ctrl_state_offset->emi_apmem_ctrl_chip_print_buff_start);
buffer_idx = wmt_plat_get_dump_info(p_emi_ctrl_state_info->p_emi_ctrl_state_offset->emi_apmem_ctrl_chip_print_buff_idx);
//buffer_len = buffer_idx - buffer_start;
g_paged_trace_len = buffer_idx;
STP_BTM_INFO_FUNC("paged trace buffer addr(%08x),buffer_len(%d)\n",buffer_start,buffer_idx);
dump_vir_addr = wmt_plat_get_emi_virt_add(buffer_start - p_emi_ctrl_state_info->emi_phy_addr);
if(!dump_vir_addr)
{
STP_BTM_ERR_FUNC("get vir dump address fail\n");
ret = -2;
break;
}
osal_memcpy(&g_paged_trace_buffer[0],dump_vir_addr,buffer_idx < STP_DBG_PAGED_TRACE_SIZE ? buffer_idx : STP_DBG_PAGED_TRACE_SIZE);
/*moving paged trace according to buffer_start & buffer_len*/
do {
int i = 0;
int dump_len = 0;
dump_len = buffer_idx < STP_DBG_PAGED_TRACE_SIZE ? buffer_idx : STP_DBG_PAGED_TRACE_SIZE;
printk("\n\n -- paged trace hex output --\n\n");
for(i = 0;i < dump_len; i++)
{
if(i%16 == 0){
printk("\n");
}
printk("%02x ",g_paged_trace_buffer[i]);
}
printk("\n\n -- paged trace ascii output --\n\n");
for(i = 0;i < dump_len; i++)
{
if(i%64 == 0)
printk("\n");
printk("%c",g_paged_trace_buffer[i]);
}
}while(0);
/*move parser fw assert infor to paged dump in the one paged dump*/
//ret = stp_dbg_set_fw_info(&g_paged_trace_buffer[0],g_paged_trace_len,issue_type);
ret = 0;
}while(0);
mtk_wcn_stp_ctx_restore();
break;
default:
ret = -1;
break;
}
return ret;
}
INT32 mtk_wcn_consys_hw_reg_ctrl(UINT32 on,UINT32 co_clock_en)
{
INT32 iRet = -1;
UINT32 retry = 10;
WMT_INFO_FUNC("CONSYS-HW-REG-CTRL(0x%08x),start\n",on);
if(on)
{
#if CONSYS_PMIC_CTRL_ENABLE
/*need PMIC driver provide new API protocol before 1/18/2013*/
/*1.Power on MT6323 VCN_1V8 LDO<--<VCN_1V8>-->write 0 to 0x512[1], write 1 to 0x512[14]*/
upmu_set_vcn_1v8_lp_mode_set(0);
//upmu_set_rg_vcn_1v8_en(1);
/*will be replaced by hwpoweron just as below*/
hwPowerOn(MT6323_POWER_LDO_VCN_1V8,VOL_DEFAULT,"MOD_WMT");
if(co_clock_en)
{
/*2.set VCN_28 to SW control mode<--<VCN28_ON_CTRL>-->write 0 to 0x41C[14]*/
upmu_set_vcn28_on_ctrl(0);
}
else
{
/*2.1.switch VCN28 to HW control mode<--<VCN28_ON_CTRL>-->write 1 to 0x41C[14]*/
upmu_set_vcn28_on_ctrl(1);
/*2.2.turn on VCN28LDO<--<RG_VCN28_EN>-->write 1 to 0x41C[12]*/
//upmu_set_rg_vcn28_en(1);
/*will be replaced by hwpoweron just as below*/
hwPowerOn(MT6323_POWER_LDO_VCN28,VOL_DEFAULT,"MOD_WMT");
}
#endif
/*mask this action and put it into FW patch for resolve ALPS00544691*/
#if 0
/*1.assert CONSYS CPU SW reset, <CONSYS_CPU_SW_RST_REG>, [12] = 1'b1, [31:24]=8'h88(key)--> CONSYS_CPU_SW_RST_BIT | CONSYS_CPU_SW_RST_CTRL_KEY*/
CONSYS_SET_BIT(CONSYS_CPU_SW_RST_REG, CONSYS_CPU_SW_RST_BIT | CONSYS_CPU_SW_RST_CTRL_KEY);
#endif
#if (MT6572_PLATFORM)
/*turn on top clock gating enable*/
CONSYS_REG_WRITE(CONSYS_TOP_CLKCG_CLR_REG,CONSYS_REG_READ(CONSYS_TOP_CLKCG_CLR_REG) | CONSYS_TOP_CLKCG_BIT);
/*turn on SPM clock gating enable*/
CONSYS_REG_WRITE(CONSYS_PWRON_CONFG_EN_REG, CONSYS_PWRON_CONFG_EN_VALUE);
#endif
conn_power_on(SYS_CON);
WMT_INFO_FUNC("reg dump:CONSYS_PWR_CONN_ACK_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_REG));
WMT_INFO_FUNC("reg dump:CONSYS_PWR_CONN_ACK_S_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_PWR_CONN_ACK_S_REG));
WMT_INFO_FUNC("reg dump:CONSYS_TOP1_PWR_CTRL_REG(0x%x)\n",CONSYS_REG_READ(CONSYS_TOP1_PWR_CTRL_REG));
/*11.delay 10us, 26M is ready*/
osal_udelay(10);
/*12.poll CONSYS CHIP until MT6582/MT6572 is returned, <CONSYS_CHIP_ID_REG>, 32'h6582/32'h6572 */
/*what does HW do, why we need to polling this register?*/
while (retry-- > 0)
{
gConsysHwChipId = CONSYS_REG_READ(CONSYS_CHIP_ID_REG);
if((gConsysHwChipId == 0x6582) || (gConsysHwChipId == 0x6572))
{
WMT_INFO_FUNC("retry(%d)consys chipId(0x%08x)\n", retry,gConsysHwChipId);
break;
}
osal_msleep(20);
}
/*mask this action and put it into FW patch for resolve ALPS00544691*/
#if 0
/*13.{default no need}update ROMDEL/PATCH RAM DELSEL if needed, <CONSYS_ROM_RAM_DELSEL_REG>*/
/*14.write 1 to conn_mcu_config ACR[1] if real speed MBIST (default write "1"), <CONSYS_MCU_CFG_ACR_REG>,[18]1'b1-->CONSYS_MCU_CFG_ACR_MBIST_BIT*/
/*if this bit is 0, HW will do memory auto test under low CPU frequence (26M Hz)*/
/*if this bit is 0, HW will do memory auto test under high CPU frequence(138M Hz) inclulding low CPU frequence*/
CONSYS_SET_BIT(CONSYS_MCU_CFG_ACR_REG, CONSYS_MCU_CFG_ACR_MBIST_BIT);
/*15.{default no need, Analog HW will inform if this need to be update or not 1 week after IC sample back}
update ANA_WBG(AFE) CR if needed, CONSYS_AFE_REG */
CONSYS_REG_WRITE(CONSYS_AFE_REG_DIG_RCK_01,CONSYS_AFE_REG_DIG_RCK_01_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_PLL_02,CONSYS_AFE_REG_WBG_PLL_02_VALUE);
CONSYS_REG_WRITE(CONSYS_AFE_REG_WBG_WB_TX_01,CONSYS_AFE_REG_WBG_WB_TX_01_VALUE);
/*16.deassert CONSYS CPU SW reset, <CONSYS_CPU_SW_RST_REG>, [12] = 1'b0, [31:24]=8'h88(key)*/
CONSYS_CLR_BIT_WITH_KEY(CONSYS_CPU_SW_RST_REG, CONSYS_CPU_SW_RST_BIT , CONSYS_CPU_SW_RST_CTRL_KEY);
#endif
osal_msleep(5);
iRet = 0;
}else{
conn_power_off(SYS_CON,1000);
#if CONSYS_PMIC_CTRL_ENABLE
/*power off MT6627 VWCN_1V8 LDO*/
upmu_set_vcn_1v8_lp_mode_set(0);
//upmu_set_rg_vcn_1v8_en(0);
/*will be replaced by hwPowerOff*/
hwPowerDown(MT6323_POWER_LDO_VCN_1V8,"MOD_WMT");
if(0 == co_clock_en)
{
/*set VCN_28 to SW control mode*/
upmu_set_vcn28_on_ctrl(0);
/*turn off VCN28 LDO*/
//upmu_set_rg_vcn28_en(0);
/*will be replaced by hwPowerOff*/
hwPowerDown(MT6323_POWER_LDO_VCN28,"MOD_WMT");
}
#endif
iRet = 0;
}
WMT_INFO_FUNC("CONSYS-HW-REG-CTRL(0x%08x),finish\n",on);
return iRet;
}
/**************************************************************************
* SEC DRIVER IOCTL
**************************************************************************/
long sec_core_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
{
int err = 0;
int ret = 0;
unsigned int cipher_len = 0;
unsigned int rid[4];
unsigned char part_name[10];
META_CONTEXT meta_ctx;
/* ---------------------------------- */
/* IOCTL */
/* ---------------------------------- */
if (_IOC_TYPE(cmd) != SEC_IOC_MAGIC)
return -ENOTTY;
if (_IOC_NR(cmd) > SEC_IOC_MAXNR)
return -ENOTTY;
if (_IOC_DIR(cmd) & _IOC_READ)
err = !access_ok(VERIFY_WRITE, (void __user *)arg, _IOC_SIZE(cmd));
if (_IOC_DIR(cmd) & _IOC_WRITE)
err = !access_ok(VERIFY_READ, (void __user *)arg, _IOC_SIZE(cmd));
if (err) return -EFAULT;
switch (cmd) {
/* ---------------------------------- */
/* get random id */
/* ---------------------------------- */
case SEC_GET_RANDOM_ID:
SMSG(bMsg,"[%s] CMD - SEC_GET_RANDOM_ID\n",MOD);
sec_get_random_id(&rid[0]);
ret = osal_copy_to_user((void __user *)arg, (void *)&rid[0], sizeof(unsigned int) * 4);
break;
/* ---------------------------------- */
/* init boot info */
/* ---------------------------------- */
case SEC_BOOT_INIT:
SMSG(bMsg,"[%s] CMD - SEC_BOOT_INIT\n",MOD);
ret = sec_boot_init();
ret = osal_copy_to_user((void __user *)arg, (void *)&ret, sizeof(int));
break;
/* ---------------------------------- */
/* check if secure boot is enbaled */
/* ---------------------------------- */
case SEC_BOOT_IS_ENABLED:
SMSG(bMsg,"[%s] CMD - SEC_BOOT_IS_ENABLED\n",MOD);
ret = sec_boot_enabled();
ret = osal_copy_to_user((void __user *)arg, (void *)&ret, sizeof(int));
break;
/* ---------------------------------- */
/* encrypt sec cfg */
/* ---------------------------------- */
case SEC_SECCFG_ENCRYPT:
SMSG(bMsg,"[%s] CMD - SEC_SECCFG_ENCRYPT\n",MOD);
if(copy_from_user((void *)&seccfg, (void __user *)arg, sizeof(SECCFG_U)))
{
return -EFAULT;
}
/* specify encrpytion length */
SMSG(true,"[%s] SECCFG v%d\n",MOD,get_seccfg_ver());
if (SEC_CFG_END_PATTERN == seccfg.v1.end_pattern)
{
if((SECCFG_V1 != get_seccfg_ver()) && (SECCFG_V1_2 != get_seccfg_ver()))
{
SMSG(true,"[%s] mismatch seccfg version v%d\n",MOD,get_seccfg_ver());
SEC_ASSERT(0);
}
cipher_len = get_seccfg_cipher_len();
sp_hacc_enc((unsigned char*)&seccfg.v1.image_info,cipher_len,rom_info.m_SEC_CTRL.m_seccfg_ac_en,HACC_USER1,FALSE);
}
else if (SEC_CFG_END_PATTERN == seccfg.v3.end_pattern)
{
if(SECCFG_V3 != get_seccfg_ver())
{
SMSG(true,"[%s] mismatch seccfg version v%d\n",MOD,get_seccfg_ver());
SEC_ASSERT(0);
}
cipher_len = get_seccfg_cipher_len();
sp_hacc_enc((unsigned char*)&seccfg.v3.image_info,cipher_len,rom_info.m_SEC_CTRL.m_seccfg_ac_en,HACC_USER1,FALSE);
}
else
{
SMSG(true,"[%s] wrong seccfg version v%d\n",MOD,seccfg.v3.seccfg_ver)
SEC_ASSERT(0);
}
ret = osal_copy_to_user((void __user *)arg, (void *)&seccfg, sizeof(SECCFG_U));
break;
/* ---------------------------------- */
/* decrypt sec cfg */
/* ---------------------------------- */
case SEC_SECCFG_DECRYPT:
SMSG(bMsg,"[%s] CMD - SEC_SECCFG_DECRYPT\n",MOD);
if(copy_from_user((void *)&seccfg, (void __user *)arg, sizeof(SECCFG_U)))
{
return -EFAULT;
}
/* specify decrpytion length */
if (SEC_CFG_END_PATTERN == seccfg.v1.end_pattern)
{
/* seccfg version should be corrected by caller */
set_seccfg_ver(SECCFG_V1);
cipher_len = get_seccfg_cipher_len();
sp_hacc_dec((unsigned char*)&seccfg.v1.image_info,cipher_len,rom_info.m_SEC_CTRL.m_seccfg_ac_en,HACC_USER1,FALSE);
}
else if (SEC_CFG_END_PATTERN == seccfg.v3.end_pattern)
{
/* seccfg version should be corrected by caller */
set_seccfg_ver(SECCFG_V3);
cipher_len = get_seccfg_cipher_len();
sp_hacc_dec((unsigned char*)&seccfg.v3.image_info,cipher_len,rom_info.m_SEC_CTRL.m_seccfg_ac_en,HACC_USER1,FALSE);
}
else
{
SMSG(true,"[%s] wrong seccfg version v%d\n",MOD,seccfg.v3.seccfg_ver)
SEC_ASSERT(0);
}
SMSG(bMsg,"[%s] SECCFG v%d\n",MOD,get_seccfg_ver());
ret = osal_copy_to_user((void __user *)arg, (void *)&seccfg, sizeof(SECCFG_U));
break;
/* ---------------------------------- */
/* NVRAM HW encryption */
/* ---------------------------------- */
case SEC_NVRAM_HW_ENCRYPT:
SMSG(bMsg,"[%s] CMD - SEC_NVRAM_HW_ENCRYPT\n",MOD);
if(osal_copy_from_user((void *)&meta_ctx, (void __user *)arg, sizeof(meta_ctx)))
{
return -EFAULT;
}
/* TODO : double check if META register is correct ? */
sp_hacc_enc((unsigned char*)&(meta_ctx.data),NVRAM_CIPHER_LEN,TRUE,HACC_USER2,FALSE);
meta_ctx.ret = SEC_OK;
ret = osal_copy_to_user((void __user *)arg, (void *)&meta_ctx, sizeof(meta_ctx));
break;
/* ---------------------------------- */
/* NVRAM HW decryption */
/* ---------------------------------- */
case SEC_NVRAM_HW_DECRYPT:
SMSG(bMsg,"[%s] CMD - SEC_NVRAM_HW_DECRYPT\n",MOD);
if(osal_copy_from_user((void *)&meta_ctx, (void __user *)arg, sizeof(meta_ctx)))
{
return -EFAULT;
}
sp_hacc_dec((unsigned char*)&(meta_ctx.data),NVRAM_CIPHER_LEN,TRUE,HACC_USER2,FALSE);
meta_ctx.ret = SEC_OK;
ret = osal_copy_to_user((void __user *)arg, (void *)&meta_ctx, sizeof(meta_ctx));
break;
/* ---------------------------------- */
/* check if secure usbdl is enbaled */
/* ---------------------------------- */
case SEC_USBDL_IS_ENABLED:
SMSG(bMsg,"[%s] CMD - SEC_USBDL_IS_ENABLED\n",MOD);
ret = sec_usbdl_enabled();
ret = osal_copy_to_user((void __user *)arg, (void *)&ret, sizeof(int));
break;
/* ---------------------------------- */
/* configure HACC HW (include SW KEY) */
/* ---------------------------------- */
case SEC_HACC_CONFIG:
SMSG(bMsg,"[%s] CMD - SEC_HACC_CONFIG\n",MOD);
ret = sec_boot_hacc_init();
ret = osal_copy_to_user((void __user *)arg, (void *)&ret, sizeof(int));
break;
/* ---------------------------------- */
/* enable HACC HW clock */
/* ---------------------------------- */
case SEC_HACC_ENABLE_CLK:
SMSG(bMsg,"[%s] CMD - SEC_HACC_ENABLE_CLK\n",MOD);
ret = osal_copy_to_user((void __user *)arg, (void *)&ret, sizeof(int));
break;
/* ---------------------------------- */
/* lock hacc function */
/* ---------------------------------- */
case SEC_HACC_LOCK:
SMSG(bMsg,"[%s] CMD - SEC_HACC_LOCK\n",MOD);
SMSG(bMsg,"[%s] lock\n",MOD);
/* If the semaphore is successfully acquired, this function returns 0.*/
ret = osal_hacc_lock();
if(ret)
{
SMSG(true,"[%s] ERESTARTSYS\n",MOD);
return -ERESTARTSYS;
}
return ret;
/* ---------------------------------- */
/* unlock hacc function */
/* ---------------------------------- */
case SEC_HACC_UNLOCK:
SMSG(bMsg,"[%s] CMD - SEC_HACC_UNLOCK\n",MOD);
SMSG(bMsg,"[%s] unlock\n",MOD);
osal_hacc_unlock();
break;
/* ---------------------------------- */
/* check if secure boot check enabled */
/* ---------------------------------- */
case SEC_BOOT_PART_CHECK_ENABLE:
SMSG(bMsg,"[%s] CMD -SEC_BOOT_PART_CHECK_ENABLE\n",MOD);
if(copy_from_user((void *)part_name, (void __user *)arg, sizeof(part_name)))
{
return -EFAULT;
}
ret = sec_boot_check_part_enabled (part_name);
SMSG(bMsg,"[%s] result '0x%x'\n",MOD,ret);
return ret;
/* ---------------------------------- */
/* notify mark incomplete */
/* ---------------------------------- */
case SEC_BOOT_NOTIFY_MARK_STATUS:
SMSG(true,"[%s] mark status\n",MOD);
/* may do some post process here ... */
break;
/* ---------------------------------- */
/* notify check pass */
/* ---------------------------------- */
case SEC_BOOT_NOTIFY_PASS:
SMSG(true,"[%s] sbchk pass\n",MOD);
SMSG(true,"[%s] sbchk pass\n",MOD);
SMSG(true,"[%s] sbchk pass\n",MOD);
SMSG(true,"[%s] sbchk pass\n",MOD);
SMSG(true,"[%s] sbchk pass\n",MOD);
/* may do some post process here ... */
break;
/* ---------------------------------- */
/* notify check fail */
/* ---------------------------------- */
case SEC_BOOT_NOTIFY_FAIL:
if(osal_copy_from_user((void *)part_name, (void __user *)arg, sizeof(part_name)))
{
return -EFAULT;
}
SMSG(true,"[%s] sbchk fail '%s'\n",MOD,part_name);
SMSG(true,"[%s] sbchk fail '%s'\n",MOD,part_name);
SMSG(true,"[%s] sbchk fail '%s'\n",MOD,part_name);
SMSG(true,"[%s] sbchk fail '%s'\n",MOD,part_name);
SMSG(true,"[%s] sbchk fail '%s'\n",MOD,part_name);
osal_msleep(3000);
/* punishment ... */
SEC_ASSERT(0);
break;
/* ---------------------------------- */
/* notify recovery mode done */
/* ---------------------------------- */
case SEC_BOOT_NOTIFY_RMSDUP_DONE:
SMSG(true,"[%s] recovery mode done\n",MOD);
/* may do some post process here ... */
break;
/* ---------------------------------- */
/* read rom info */
/* ---------------------------------- */
case SEC_READ_ROM_INFO:
SMSG(bMsg,"[%s] read rom info\n",MOD);
ret = osal_copy_to_user((void __user *)arg, (void *)&rom_info, sizeof(AND_ROMINFO_T));
break;
}
return 0;
}
