void rtc_init () {
register u08_t r ;
i386_pushfl () ;
i386_cli () ;
outpb (0x70,0x8B) ;
r = inpb (0x71) ;
outpb (0x70,0x8B) ;
outpb (0x71,0x40|r) ;
rtc_timestamp = 0LL ;
i386_popfl () ;
}
FloppyController::
FloppyController(es::Dmac* dmac, u16 base, u8 irq) :
base(base),
current(0),
dmac(dmac)
{
monitor = es::Monitor::createInstance();
// motor off
for (int i = 3; 0 <= i; --i)
{
outpb(base + DOR, 0x0c | i);
}
motor = 0;
outpb(base + DSR, 0);
Core::registerInterruptHandler(irq, this);
}
trap_retval ReqWrite_io( void )
{
write_io_req *acc;
write_io_ret *ret;
void *data;
trap_elen len;
/* Perform I/O on the target machine on behalf of the debugger.
* Since there are no kernel APIs in Linux to do this, we just
* enable IOPL and use regular I/O. We will bail if we can't get
* IOPL=3, so the debugger trap file will need to be run as root
* before it can be used for I/O access.
*/
acc = GetInPtr( 0 );
data = GetInPtr( sizeof( *acc ) );
len = GetTotalSize() - sizeof( *acc );
ret = GetOutPtr( 0 );
#ifdef __WATCOMC__
if( iopl( 3 ) == 0 ) {
ret->len = len;
switch( len ) {
case 1:
outpb( acc->IO_offset, *((unsigned_8*)data) );
break;
case 2:
outpw( acc->IO_offset, *((unsigned_16*)data) );
break;
case 4:
outpd( acc->IO_offset, *((unsigned_32*)data) );
break;
}
} else {
ret->len = 0;
}
#else
ret->len = 0;
#endif
return( sizeof( *ret ) );
}
void FloppyController::
issue(FloppyDrive* drive, u8 cmd, void* param)
{
done = false;
commandLength = 0;
switch (cmd)
{
case SENSE:
command[commandLength++] = cmd;
done = true;
break;
case RECALIBRATE:
command[commandLength++] = cmd;
command[commandLength++] = drive->drive;
break;
case SEEK:
command[commandLength++] = cmd;
command[commandLength++] = (drive->head << 2) | drive->drive;
command[commandLength++] = drive->cylinder;
break;
case READ:
case WRITE:
command[commandLength++] = cmd;
command[commandLength++] = (drive->head << 2) | drive->drive;
command[commandLength++] = drive->cylinder;
command[commandLength++] = drive->head;
command[commandLength++] = drive->record;
command[commandLength++] = drive->recordLength;
command[commandLength++] = drive->eot;
command[commandLength++] = drive->gpl;
command[commandLength++] = 0xFF;
break;
case FORMAT:
command[commandLength++] = cmd;
command[commandLength++] = (drive->head << 2) | drive->drive;
command[commandLength++] = drive->recordLength;
command[commandLength++] = drive->eot;
command[commandLength++] = drive->fgpl;
command[commandLength++] = 0x00;
break;
default:
esReport("FloppyController: unsupported command %0x2\n", cmd);
break;
}
current = drive;
statusLength = 0;
for (int i = 0; i < commandLength; i++)
{
u8 msr;
do
{
msr = inpb(base + MSR);
} while (!(msr & 0x80));
if (msr & 0x40)
{
result();
done = true;
break;
}
outpb(base + FIFO, command[i]);
}
while (!done)
{
monitor->wait();
}
}
void rtc_isr () {
outpb (0x70,0x0C) ;
inpb (0x71) ;
++rtc_timestamp ;
}
/* vid_set_256_palette()
* port_io = use port I/O
*
* this sets the 256 bpp mode palette
* if the card isn't VGA compatible, we have
* to use the VESA BIOS to set the palette
*
* The RGB components can be 0 - 63 each, with 256 entries
* within the table to choose from.
*/
void vid_set_256_palette(const bool port_io) {
int i;
//bit8u palette256_info[256 * 4], *p;
//struct REGS regs;
// some controllers are not VGA compatible
//if (port_io) {
// wait for the retrace to start (older video cards require this)
vsync();
// mode is VGA compatible, so use the VGA regs
for (i=0; i<255; i++) {
outpb(0x3C8, (bit8u) i);
outpb(0x3C9, (bit8u) (i & 0xE0) >> 2);
outpb(0x3C9, (bit8u) (i & 0x1C) << 1);
outpb(0x3C9, (bit8u) (i & 0x03) << 4);
}
// white
outpb(0x3C8, (bit8u) 255);
outpb(0x3C9, 0xFF);
outpb(0x3C9, 0xFF);
outpb(0x3C9, 0xFF);
//} else {
/*
// must use VBE to set the DAC (palette)
// ax = 0x4F09
// bl = 0x80 set palette info while vertical retrace
// cx = number of registers (256)
// dx = start (0)
// es:di -> address to buffer
// buffer is:
// {
// db blue
// db green
// db red
// db resv
// } [256];
p = palette256_info;
for (i=0; i<255; i++) {
*p++ = (bit8u) (i & 0xE0) >> 2;
*p++ = (bit8u) (i & 0x1C) << 1;
*p++ = (bit8u) (i & 0x03) << 4;
*p++ = 0;
}
// white
*p++ = 0xFF;
*p++ = 0xFF;
*p++ = 0xFF;
*p++ = 0;
// call the service
regs.edi = palette256_info;
regs.eax = 0x00004F09;
regs.ebx = 0x00000080;
regs.ecx = 256;
regs.edx = 0;
intx(0x10, ®s);
*/
//}
}