UINT32 md_rom_svp_device::pm_io(int reg, int write, UINT32 d)
{
if (m_emu_status & SSP_PMC_SET)
{
if (write)
m_pmac_write[reg] = m_pmc.d;
else
m_pmac_read[reg] = m_pmc.d;
m_emu_status &= ~SSP_PMC_SET;
return 0;
}
// just in case
if (m_emu_status & SSP_PMC_HAVE_ADDR)
m_emu_status &= ~SSP_PMC_HAVE_ADDR;
if (reg == 4 || (m_svp->state().state_int(SSP_ST) & 0x60))
{
#define CADDR ((((mode<<16)&0x7f0000)|addr)<<1)
UINT16 *dram = (UINT16 *)m_dram;
if (write)
{
int mode = m_pmac_write[reg] >> 16;
int addr = m_pmac_write[reg] & 0xffff;
if ((mode & 0x43ff) == 0x0018) // DRAM
{
int inc = get_inc(mode);
if (mode & 0x0400)
overwrite_write(&dram[addr], d);
else
dram[addr] = d;
m_pmac_write[reg] += inc;
}
else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
{
if (mode & 0x0400)
overwrite_write(&dram[addr], d);
else
dram[addr] = d;
m_pmac_write[reg] += (addr & 1) ? 31 : 1;
}
else if ((mode & 0x47ff) == 0x001c) // IRAM
{
int inc = get_inc(mode);
((UINT16 *)m_iram)[addr & 0x3ff] = d;
m_pmac_write[reg] += inc;
}
else
{
logerror("ssp FIXME: PM%i unhandled write mode %04x, [%06x] %04x\n",
reg, mode, CADDR, d);
}
}
else
{
static UINT32 pm_io(address_space &space, int reg, int write, UINT32 d)
{
mdsvp_state *state = space.machine().driver_data<mdsvp_state>();
if (state->m_emu_status & SSP_PMC_SET)
{
state->m_pmac_read[write ? reg + 6 : reg] = state->m_pmc.d;
state->m_emu_status &= ~SSP_PMC_SET;
return 0;
}
// just in case
if (state->m_emu_status & SSP_PMC_HAVE_ADDR) {
state->m_emu_status &= ~SSP_PMC_HAVE_ADDR;
}
if (reg == 4 || (space.device().state().state_int(SSP_ST) & 0x60))
{
#define CADDR ((((mode<<16)&0x7f0000)|addr)<<1)
UINT16 *dram = (UINT16 *)state->m_dram;
if (write)
{
int mode = state->m_pmac_write[reg]>>16;
int addr = state->m_pmac_write[reg]&0xffff;
if ((mode & 0x43ff) == 0x0018) // DRAM
{
int inc = get_inc(mode);
if (mode & 0x0400) {
overwrite_write(&dram[addr], d);
} else dram[addr] = d;
state->m_pmac_write[reg] += inc;
}
else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
{
if (mode & 0x0400) {
overwrite_write(&dram[addr], d);
} else dram[addr] = d;
state->m_pmac_write[reg] += (addr&1) ? 31 : 1;
}
else if ((mode & 0x47ff) == 0x001c) // IRAM
{
int inc = get_inc(mode);
((UINT16 *)state->m_iram)[addr&0x3ff] = d;
state->m_pmac_write[reg] += inc;
}
else
{
logerror("ssp FIXME: PM%i unhandled write mode %04x, [%06x] %04x\n",
reg, mode, CADDR, d);
}
}
else
{
