/*
* \brief Perform a single ED measurement
*
* \return ed_value Result of the measurement
* If the build switch TRX_REG_RAW_VALUE is defined, the transceiver's
* register value is returned.
*/
uint8_t tfa_ed_sample(void)
{
uint8_t ed_value;
tal_trx_status_t trx_status;
/* Make sure that receiver is switched on. */
do
{
trx_status = set_trx_state(CMD_RX_ON);
}
while (trx_status != RX_ON);
/*
* Disable the transceiver interrupts to prevent frame reception
* while performing ED scan.
*/
pal_trx_irq_dis();
/*
* Initiate ED operation by writing any value into transceiver register
* PHY_ED_LEVEL.
*/
pal_trx_reg_write(RG_PHY_ED_LEVEL, 0x00);
/*
* Start timer for reading ED value from the transceiver after
* 140 microseconds.
*/
pal_timer_delay(TAL_CONVERT_SYMBOLS_TO_US(ED_SAMPLE_DURATION_SYM + 1));
/* Read the ED Value. */
ed_value = pal_trx_reg_read(RG_PHY_ED_LEVEL);
/* Clear IRQ register */
pal_trx_reg_read(RG_IRQ_STATUS);
/* Enable reception agian */
pal_trx_irq_flag_clr();
pal_trx_irq_en();
/* Switch receiver off again */
set_trx_state(CMD_TRX_OFF);
#ifndef TRX_REG_RAW_VALUE
/*
* Scale ED result.
* Clip values to 0xFF if > -35dBm
*/
if (ed_value > CLIP_VALUE_REG)
{
ed_value = 0xFF;
}
else
{
ed_value = (uint8_t)(((uint16_t)ed_value * 0xFF) / CLIP_VALUE_REG);
}
#endif
return ed_value;
}
/**
* @brief Switches the PLL on
*/
static void switch_pll_on(void)
{
uint32_t start_time;
uint32_t current_time;
/* Check if trx is in TRX_OFF; only from PLL_ON the following procedure is applicable */
if (pal_trx_bit_read(SR_TRX_STATUS) != TRX_OFF)
{
ASSERT("Switch PLL_ON failed, because trx is not in TRX_OFF" == 0);
return;
}
/* Clear all pending trx interrupts */
pal_trx_reg_read(RG_IRQ_STATUS);
/* Get current IRQ mask */
uint8_t trx_irq_mask = pal_trx_reg_read(RG_IRQ_MASK);
/* Enable transceiver's PLL lock interrupt */
pal_trx_reg_write(RG_IRQ_MASK, TRX_IRQ_0_PLL_LOCK);
ENTER_TRX_REGION(); // Disable trx interrupt handling
/* Switch PLL on */
pal_trx_reg_write(RG_TRX_STATE, CMD_PLL_ON);
pal_get_current_time(&start_time);
/* Wait for transceiver interrupt: check for IRQ line */
while (PAL_TRX_IRQ_HIGH() == false)
{
/* Handle errata "potential long PLL settling duration". */
pal_get_current_time(¤t_time);
if (pal_sub_time_us(current_time, start_time) > PLL_LOCK_DURATION_MAX_US)
{
uint8_t reg_value;
reg_value = pal_trx_reg_read(RG_PLL_CF);
if (reg_value & 0x01)
{
reg_value &= 0xFE;
}
else
{
reg_value |= 0x01;
}
pal_trx_reg_write(RG_PLL_CF, reg_value);
pal_get_current_time(&start_time);
}
/* Wait until trx line has been raised. */
}
/* Clear PLL lock interrupt at trx */
pal_trx_reg_read(RG_IRQ_STATUS);
/* Clear MCU's interrupt flag */
pal_trx_irq_flag_clr();
LEAVE_TRX_REGION(); // Enable trx interrupt handling again
/* Restore transceiver's interrupt mask. */
pal_trx_reg_write(RG_IRQ_MASK, trx_irq_mask);
}
/**
* @brief Generates a 16-bit random number used as initial seed for srand()
*
* This function generates a 16-bit random number by means of using the
* Random Number Generator from the transceiver.
* The Random Number Generator generates 2-bit random values. These 2-bit
* random values are concatenated to the required 16-bit random seed.
*
* The generated random 16-bit number is feed into function srand()
* as initial seed.
*
* The transceiver state is initally set to RX_ON.
* After the completion of the random seed generation, the
* trancseiver is set to TRX_OFF.
*
* As a prerequisite the preamble detector must not be disabled.
*
* Also in case the function is called from a different state than TRX_OFF,
* additional trx state handling is required, such as reading the original
* value and restoring this state after finishing the sequence.
* Since in our case the function is called from TRX_OFF, this is not required
* here.
*/
void tal_generate_rand_seed(void)
{
uint16_t seed = 0;
uint8_t cur_random_val = 0;
/* RPC could influence the randomness; therefore disable it here. */
uint8_t previous_RPC_value = pal_trx_reg_read(RG_TRX_RPC);
pal_trx_reg_write(RG_TRX_RPC, 0xC1);
/*
* We need to disable TRX IRQs while generating random values in RX_ON,
* we do not want to receive frames at this point of time at all.
*/
ENTER_TRX_REGION();
/* Ensure that PLL has locked and receive mode is reached. */
tal_trx_status_t trx_state;
do
{
trx_state = set_trx_state(CMD_RX_ON);
}
while (trx_state != RX_ON);
/* Ensure that register bit RX_PDT_DIS is set to 0. */
pal_trx_bit_write(SR_RX_PDT_DIS, RX_ENABLE);
/*
* The 16-bit random value is generated from various 2-bit random values.
*/
for (uint8_t i = 0; i < 8; i++)
{
/* Now we can safely read the 2-bit random number. */
cur_random_val = pal_trx_bit_read(SR_RND_VALUE);
seed = seed << 2;
seed |= cur_random_val;
PAL_WAIT_1_US(); // wait that the random value gets updated
}
set_trx_state(CMD_FORCE_TRX_OFF);
/*
* Now we need to clear potential pending TRX IRQs and
* enable the TRX IRQs again.
*/
pal_trx_reg_read(RG_IRQ_STATUS);
pal_trx_irq_flag_clr();
LEAVE_TRX_REGION();
/* Set the seed for the random number generator. */
srand(seed);
/* Restore RPC settings. */
pal_trx_reg_write(RG_TRX_RPC, previous_RPC_value);
}
/**
* @brief Switches the PLL on
*/
static void switch_pll_on(void)
{
trx_irq_reason_t irq_status;
uint32_t start_time, now;
/* Check if trx is in TRX_OFF; only from PLL_ON the following procedure is applicable */
if (pal_trx_bit_read(SR_TRX_STATUS) != TRX_OFF)
{
ASSERT("Switch PLL_ON failed, because trx is not in TRX_OFF" == 0);
return;
}
/* use the IRQ status register checking for the actual PLL status */
pal_trx_irq_dis();
pal_trx_reg_write(RG_IRQ_MASK, TRX_IRQ_PLL_LOCK); /* allow PLL lock IRQ only*/
pal_trx_reg_read(RG_IRQ_STATUS); /* clear PLL lock bit */
/* Switch PLL on */
pal_trx_reg_write(RG_TRX_STATE, CMD_PLL_ON);
/* Check if PLL has been locked. */
pal_get_current_time(&start_time);
while (1)
{
irq_status = (trx_irq_reason_t)pal_trx_reg_read(RG_IRQ_STATUS);
if (irq_status & TRX_IRQ_PLL_LOCK)
{
break; // PLL is locked now
}
/* Check if polling needs too much time. */
pal_get_current_time(&now);
if (pal_sub_time_us(now, start_time) > (10 * PLL_LOCK_TIME_US))
{
/* leave poll loop and throw assertion */
#if (DEBUG > 0)
ASSERT("PLL switch failed" == 0);
#endif
break;
}
}
pal_trx_irq_flag_clr();
pal_trx_reg_write(RG_IRQ_MASK, TRX_IRQ_TRX_END); /* enable TRX_END interrupt */
pal_trx_irq_en();
}
static void switch_rf_to_txprep(trx_id_t trx_id)
{
uint16_t reg_offset = RF_BASE_ADDR_OFFSET * trx_id;
pal_trx_reg_write(RF215_RF, reg_offset + RG_RF09_CMD, RF_TXPREP);
/* Wait for TXPREP */
rf_cmd_state_t state;
do {
state = (rf_cmd_state_t)pal_trx_reg_read(RF215_RF,
reg_offset +
RG_RF09_STATE);
} while (state != RF_TXPREP);
/* Clear TRXRDY interrupt */
uint8_t irqs = pal_trx_reg_read(RF215_RF, trx_id + RG_RF09_IRQS);
tal_rf_irqs[trx_id] |= irqs & ((uint8_t)(~((uint32_t)RF_IRQ_TRXRDY))); /*
* avoid
* Pa091 */
pal_trx_irq_flag_clr(RF215_RF);
}
/**
* @brief Sets transceiver state
*
* @param trx_cmd needs to be one of the trx commands
*
* @return current trx state
*/
tal_trx_status_t set_trx_state(trx_cmd_t trx_cmd)
{
if (tal_trx_status == TRX_SLEEP)
{
/*
* Since the wake-up procedure relies on the Awake IRQ and
* the global interrupts may be disabled at this point of time,
* we need to make sure that the global interrupts are enabled
* during wake-up procedure.
* Once the TRX is awake, the original state of the global interrupts
* will be restored.
*/
/* Reset wake-up interrupt flag. */
tal_awake_end_flag = false;
/* Set callback function for the awake interrupt. */
pal_trx_irq_init(trx_irq_awake_handler_cb);
/* The pending transceiver interrupts on the microcontroller are cleared. */
pal_trx_irq_flag_clr();
pal_trx_irq_en(); /* Enable transceiver main interrupt. */
/* Save current state of global interrupts. */
ENTER_CRITICAL_REGION();
/* Force enabling of global interrupts. */
ENABLE_GLOBAL_IRQ();
/* Leave trx sleep mode. */
PAL_SLP_TR_LOW();
/* Poll wake-up interrupt flag until set within ISR. */
while (!tal_awake_end_flag);
/* Restore original state of global interrupts. */
LEAVE_CRITICAL_REGION();
/* Clear existing interrupts */
pal_trx_reg_read(RG_IRQ_STATUS);
/* Re-install default IRQ handler for main interrupt. */
pal_trx_irq_init(trx_irq_handler_cb);
/* Re-enable TRX_END interrupt */
pal_trx_reg_write(RG_IRQ_MASK, TRX_IRQ_DEFAULT);
#if (ANTENNA_DIVERSITY == 1)
/* Enable antenna diversity. */
pal_trx_bit_write(SR_ANT_EXT_SW_EN, ANT_EXT_SW_ENABLE);
#endif
#ifdef EXT_RF_FRONT_END_CTRL
/* Enable RF front end control */
pal_trx_bit_write(SR_PA_EXT_EN, 1);
#endif
tal_trx_status = TRX_OFF;
if ((trx_cmd == CMD_TRX_OFF) || (trx_cmd == CMD_FORCE_TRX_OFF))
{
return TRX_OFF;
}
}
#ifdef ENABLE_DEEP_SLEEP
else if (tal_trx_status == TRX_DEEP_SLEEP)
{
/* Leave trx sleep mode. */
PAL_SLP_TR_LOW();
/* Check if trx has left deep sleep. */
tal_trx_status_t trx_state;
do
{
trx_state = (tal_trx_status_t)pal_trx_reg_read(RG_TRX_STATUS);
}
while (trx_state != TRX_OFF);
tal_trx_status = TRX_OFF;
/* Using deep sleep, the transceiver's registers need to be restored. */
trx_config();
/*
* Write all PIB values to the transceiver
* that are needed by the transceiver itself.
*/
write_all_tal_pib_to_trx(); /* implementation can be found in 'tal_pib.c' */
if ((trx_cmd == CMD_TRX_OFF) || (trx_cmd == CMD_FORCE_TRX_OFF))
{
return TRX_OFF;
}
}
#endif
switch (trx_cmd) /* requested state */
{
case CMD_SLEEP:
#ifdef ENABLE_DEEP_SLEEP
/* Fall through. */
case CMD_DEEP_SLEEP:
#endif
pal_trx_reg_write(RG_TRX_STATE, CMD_FORCE_TRX_OFF);
#if (ANTENNA_DIVERSITY == 1)
/*
* Disable antenna diversity: to reduce the power consumption or
* avoid leakage current of an external RF switch during SLEEP.
*/
pal_trx_bit_write(SR_ANT_EXT_SW_EN, ANT_EXT_SW_DISABLE);
#endif
#ifdef EXT_RF_FRONT_END_CTRL
/* Disable RF front end control */
pal_trx_bit_write(SR_PA_EXT_EN, 0);
#endif
/* Clear existing interrupts */
pal_trx_reg_read(RG_IRQ_STATUS);
/*
* Enable Awake_end interrupt.
* This is used for save wake-up from sleep later.
*/
pal_trx_bit_write(SR_IRQ_MASK, TRX_IRQ_4_CCA_ED_DONE);
#ifdef ENABLE_DEEP_SLEEP
if (trx_cmd == CMD_DEEP_SLEEP)
{
pal_trx_reg_write(RG_TRX_STATE, CMD_PREP_DEEP_SLEEP);
tal_trx_status = TRX_DEEP_SLEEP;
}
else
{
/*
* Enable Awake_end interrupt.
* This is used for save wake-up from sleep later.
*/
pal_trx_bit_write(SR_IRQ_MASK, TRX_IRQ_4_CCA_ED_DONE);
tal_trx_status = TRX_SLEEP;
}
#else
/*
* Enable Awake_end interrupt.
* This is used for save wake-up from sleep later.
*/
pal_trx_bit_write(SR_IRQ_MASK, TRX_IRQ_4_CCA_ED_DONE);
tal_trx_status = TRX_SLEEP;
#endif
PAL_WAIT_1_US();
PAL_SLP_TR_HIGH();
pal_timer_delay(TRX_OFF_TO_SLEEP_TIME_CLKM_CYCLES);
/* Transceiver register cannot be read during TRX_SLEEP or DEEP_SLEEP. */
return tal_trx_status;
case CMD_TRX_OFF:
switch (tal_trx_status)
{
case TRX_OFF:
break;
default:
pal_trx_reg_write(RG_TRX_STATE, CMD_TRX_OFF);
PAL_WAIT_1_US();
break;
}
break;
case CMD_FORCE_TRX_OFF:
switch (tal_trx_status)
{
case TRX_OFF:
break;
default:
pal_trx_reg_write(RG_TRX_STATE, CMD_FORCE_TRX_OFF);
PAL_WAIT_1_US();
break;
}
break;
case CMD_PLL_ON:
switch (tal_trx_status)
{
case PLL_ON:
break;
case TRX_OFF:
switch_pll_on();
break;
case RX_ON:
case RX_AACK_ON:
case TX_ARET_ON:
pal_trx_reg_write(RG_TRX_STATE, CMD_PLL_ON);
PAL_WAIT_1_US();
break;
case BUSY_RX:
case BUSY_TX:
case BUSY_RX_AACK:
case BUSY_TX_ARET:
/* do nothing if trx is busy */
break;
default:
ASSERT("state transition not handled" == 0);
break;
}
break;
case CMD_FORCE_PLL_ON:
switch (tal_trx_status)
{
case TRX_OFF:
switch_pll_on();
break;
case PLL_ON:
break;
default:
pal_trx_reg_write(RG_TRX_STATE, CMD_FORCE_PLL_ON);
break;
}
break;
case CMD_RX_ON:
switch (tal_trx_status)
{
case RX_ON:
break;
case PLL_ON:
case RX_AACK_ON:
case TX_ARET_ON:
pal_trx_reg_write(RG_TRX_STATE, CMD_RX_ON);
PAL_WAIT_1_US();
break;
case TRX_OFF:
switch_pll_on();
pal_trx_reg_write(RG_TRX_STATE, CMD_RX_ON);
PAL_WAIT_1_US();
break;
case BUSY_RX:
case BUSY_TX:
case BUSY_RX_AACK:
case BUSY_TX_ARET:
/* do nothing if trx is busy */
break;
default:
ASSERT("state transition not handled" == 0);
break;
}
break;
case CMD_RX_AACK_ON:
switch (tal_trx_status)
{
case RX_AACK_ON:
break;
case TX_ARET_ON:
case PLL_ON:
case RX_ON:
pal_trx_reg_write(RG_TRX_STATE, CMD_RX_AACK_ON);
PAL_WAIT_1_US();
break;
case TRX_OFF:
switch_pll_on(); // state change from TRX_OFF to RX_AACK_ON can be done directly, too
pal_trx_reg_write(RG_TRX_STATE, CMD_RX_AACK_ON);
PAL_WAIT_1_US();
break;
case BUSY_RX:
case BUSY_TX:
case BUSY_RX_AACK:
case BUSY_TX_ARET:
/* do nothing if trx is busy */
break;
default:
ASSERT("state transition not handled" == 0);
break;
}
break;
case CMD_TX_ARET_ON:
switch (tal_trx_status)
{
case TX_ARET_ON:
break;
case PLL_ON:
case RX_ON:
case RX_AACK_ON:
pal_trx_reg_write(RG_TRX_STATE, CMD_TX_ARET_ON);
PAL_WAIT_1_US();
break;
case TRX_OFF:
switch_pll_on(); // state change from TRX_OFF to TX_ARET_ON can be done directly, too
pal_trx_reg_write(RG_TRX_STATE, CMD_TX_ARET_ON);
PAL_WAIT_1_US();
break;
case BUSY_RX:
case BUSY_TX:
case BUSY_RX_AACK:
case BUSY_TX_ARET:
/* do nothing if trx is busy */
break;
default:
ASSERT("state transition not handled" == 0);
break;
}
break;
default:
/* CMD_NOP, CMD_TX_START */
ASSERT("trx command not handled" == 0);
break;
}
do
{
tal_trx_status = (tal_trx_status_t)pal_trx_bit_read(SR_TRX_STATUS);
}
while (tal_trx_status == STATE_TRANSITION_IN_PROGRESS);
return tal_trx_status;
} /* set_trx_state() */
/*
* \brief Resets TAL state machine and sets the default PIB values if requested
*
* \param set_default_pib Defines whether PIB values need to be set
* to its default values
*
* \return MAC_SUCCESS if the transceiver state is changed to TRX_OFF
* FAILURE otherwise
*/
retval_t tal_reset(bool set_default_pib)
{
/*
* Do the reset stuff.
* Set the default PIBs depending on the given parameter
* set_default_pib.
* Do NOT generate random seed again.
*/
if (internal_tal_reset(set_default_pib) != MAC_SUCCESS) {
return FAILURE;
}
ENTER_CRITICAL_REGION();
tal_timers_stop();
LEAVE_CRITICAL_REGION();
/* Clear TAL Incoming Frame queue and free used buffers. */
while (tal_incoming_frame_queue.size > 0) {
buffer_t *frame = qmm_queue_remove(&tal_incoming_frame_queue,
NULL);
if (NULL != frame) {
bmm_buffer_free(frame);
}
}
#ifdef ENABLE_TFA
tfa_reset(set_default_pib);
#endif
/*
* Configure interrupt handling.
* Install a handler for the transceiver interrupt.
*/
trx_irq_init((FUNC_PTR)trx_irq_handler_cb);
/* The pending transceiver interrupts on the microcontroller are
* cleared. */
pal_trx_irq_flag_clr();
pal_trx_irq_en(); /* Enable transceiver main interrupt. */
#ifdef ENABLE_FTN_PLL_CALIBRATION
{
/* Handle PLL calibration and filter tuning. */
retval_t timer_status;
/* Calibration timer has already been stopped within this
* function. */
/* Start periodic calibration timer.*/
timer_status = pal_timer_start(TAL_CALIBRATION,
TAL_CALIBRATION_TIMEOUT_US,
TIMEOUT_RELATIVE,
(FUNC_PTR)calibration_timer_handler_cb,
NULL);
if (timer_status != MAC_SUCCESS) {
Assert("PLL calibration timer start problem" == 0);
}
}
#endif /* ENABLE_FTN_PLL_CALIBRATION */
return MAC_SUCCESS;
}
/*
* \brief Sets transceiver state
*
* \param trx_cmd needs to be one of the trx commands
*
* \return current trx state
*/
tal_trx_status_t set_trx_state(trx_cmd_t trx_cmd)
{
if (tal_trx_status == TRX_SLEEP) {
/*
* Since the wake-up procedure relies on the Awake IRQ and
* the global interrupts may be disabled at this point of time,
* we need to make sure that the global interrupts are enabled
* during wake-up procedure.
* Once the TRX is awake, the original state of the global
* interrupts
* will be restored.
*/
/* Reset wake-up interrupt flag. */
if (CMD_SLEEP == trx_cmd) {
return TRX_SLEEP;
}
tal_awake_end_flag = false;
/* Set callback function for the awake interrupt. */
trx_irq_init((FUNC_PTR)trx_irq_awake_handler_cb);
/* The pending transceiver interrupts on the microcontroller are
* cleared. */
pal_trx_irq_flag_clr();
pal_trx_irq_en(); /* Enable transceiver main interrupt. */
/* Save current state of global interrupts. */
ENTER_CRITICAL_REGION();
/* Force enabling of global interrupts. */
ENABLE_GLOBAL_IRQ();
/* Leave trx sleep mode. */
TRX_SLP_TR_LOW();
/* Poll wake-up interrupt flag until set within ISR. */
while (!tal_awake_end_flag) {
}
/* Restore original state of global interrupts. */
LEAVE_CRITICAL_REGION();
/* Clear existing interrupts */
trx_reg_read(RG_IRQ_STATUS);
/* Re-install default IRQ handler for main interrupt. */
trx_irq_init((FUNC_PTR)trx_irq_handler_cb);
/* Re-enable TRX_END interrupt */
trx_reg_write(RG_IRQ_MASK, TRX_IRQ_DEFAULT);
#if (ANTENNA_DIVERSITY == 1)
/* Enable antenna diversity. */
trx_bit_write(SR_ANT_EXT_SW_EN, ANT_EXT_SW_ENABLE);
#endif
if ((trx_cmd == CMD_TRX_OFF) ||
(trx_cmd == CMD_FORCE_TRX_OFF)) {
tal_trx_status = TRX_OFF;
return TRX_OFF;
}
}
switch (trx_cmd) { /* requested state */
case CMD_SLEEP:
trx_reg_write(RG_TRX_STATE, CMD_FORCE_TRX_OFF);
#if (ANTENNA_DIVERSITY == 1)
/* Disable antenna diversity: sets pulls */
trx_bit_write(SR_ANT_EXT_SW_EN, ANT_EXT_SW_DISABLE);
#endif
#ifndef SW_CONTROLLED_CSMA
{
uint16_t rand_value;
/*
* Init the SEED value of the CSMA backoff algorithm.
*/
rand_value = (uint16_t)rand();
trx_reg_write(RG_CSMA_SEED_0, (uint8_t)rand_value);
trx_bit_write(SR_CSMA_SEED_1,
(uint8_t)(rand_value >> 8));
}
#endif
/* Clear existing interrupts */
trx_reg_read(RG_IRQ_STATUS);
/*
* Enable Awake_end interrupt.
* This is used for save wake-up from sleep later.
*/
trx_bit_write(SR_IRQ_MASK, TRX_IRQ_4_CCA_ED_DONE);
PAL_WAIT_1_US();
TRX_SLP_TR_HIGH();
pal_timer_delay(TRX_OFF_TO_SLEEP_TIME_CLKM_CYCLES);
tal_trx_status = TRX_SLEEP;
return TRX_SLEEP; /* transceiver register cannot be read during
* TRX_SLEEP */
case CMD_TRX_OFF:
switch (tal_trx_status) {
case TRX_OFF:
break;
default:
trx_reg_write(RG_TRX_STATE, CMD_TRX_OFF);
PAL_WAIT_1_US();
break;
}
break;
case CMD_FORCE_TRX_OFF:
switch (tal_trx_status) {
case TRX_OFF:
break;
default:
trx_reg_write(RG_TRX_STATE, CMD_FORCE_TRX_OFF);
PAL_WAIT_1_US();
break;
}
break;
case CMD_PLL_ON:
switch (tal_trx_status) {
case PLL_ON:
break;
case TRX_OFF:
switch_pll_on();
break;
case RX_ON:
case RX_AACK_ON:
case TX_ARET_ON:
trx_reg_write(RG_TRX_STATE, CMD_PLL_ON);
PAL_WAIT_1_US();
break;
case BUSY_RX:
case BUSY_TX:
case BUSY_RX_AACK:
case BUSY_TX_ARET:
/* do nothing if trx is busy */
break;
default:
Assert("state transition not handled" == 0);
break;
}
break;
case CMD_FORCE_PLL_ON:
switch (tal_trx_status) {
case TRX_OFF:
switch_pll_on();
break;
case PLL_ON:
break;
default:
trx_reg_write(RG_TRX_STATE, CMD_FORCE_PLL_ON);
break;
}
break;
case CMD_RX_ON:
switch (tal_trx_status) {
case RX_ON:
break;
case PLL_ON:
case RX_AACK_ON:
case TX_ARET_ON:
trx_reg_write(RG_TRX_STATE, CMD_RX_ON);
PAL_WAIT_1_US();
break;
case TRX_OFF:
switch_pll_on();
trx_reg_write(RG_TRX_STATE, CMD_RX_ON);
PAL_WAIT_1_US();
break;
case BUSY_RX:
case BUSY_TX:
case BUSY_RX_AACK:
case BUSY_TX_ARET:
/* do nothing if trx is busy */
break;
default:
Assert("state transition not handled" == 0);
break;
}
break;
case CMD_RX_AACK_ON:
switch (tal_trx_status) {
case RX_AACK_ON:
break;
case TX_ARET_ON:
case PLL_ON:
trx_reg_write(RG_TRX_STATE, CMD_RX_AACK_ON);
PAL_WAIT_1_US();
break;
case TRX_OFF:
switch_pll_on(); /* state change from TRX_OFF to
* RX_AACK_ON can be done directly, too
**/
trx_reg_write(RG_TRX_STATE, CMD_RX_AACK_ON);
PAL_WAIT_1_US();
break;
case RX_ON:
trx_reg_write(RG_TRX_STATE, CMD_PLL_ON);
PAL_WAIT_1_US();
/* check if state change could be applied */
tal_trx_status = (tal_trx_status_t)trx_bit_read(
SR_TRX_STATUS);
if (tal_trx_status != PLL_ON) {
return tal_trx_status;
}
trx_reg_write(RG_TRX_STATE, CMD_RX_AACK_ON);
PAL_WAIT_1_US();
break;
case BUSY_RX:
case BUSY_TX:
case BUSY_RX_AACK:
case BUSY_TX_ARET:
/* do nothing if trx is busy */
break;
default:
Assert("state transition not handled" == 0);
break;
}
break;
case CMD_TX_ARET_ON:
switch (tal_trx_status) {
case TX_ARET_ON:
break;
case PLL_ON:
trx_reg_write(RG_TRX_STATE, CMD_TX_ARET_ON);
PAL_WAIT_1_US();
break;
case RX_ON:
case RX_AACK_ON:
trx_reg_write(RG_TRX_STATE, CMD_PLL_ON);
PAL_WAIT_1_US();
/* check if state change could be applied */
tal_trx_status = (tal_trx_status_t)trx_bit_read(
SR_TRX_STATUS);
if (tal_trx_status != PLL_ON) {
return tal_trx_status;
}
trx_reg_write(RG_TRX_STATE, CMD_TX_ARET_ON);
PAL_WAIT_1_US();
break;
case TRX_OFF:
switch_pll_on(); /* state change from TRX_OFF to
* TX_ARET_ON can be done directly, too
**/
trx_reg_write(RG_TRX_STATE, CMD_TX_ARET_ON);
PAL_WAIT_1_US();
break;
case BUSY_RX:
case BUSY_TX:
case BUSY_RX_AACK:
case BUSY_TX_ARET:
/* do nothing if trx is busy */
break;
default:
Assert("state transition not handled" == 0);
break;
}
break;
default:
/* CMD_NOP, CMD_TX_START */
Assert("trx command not handled" == 0);
break;
}
do {
tal_trx_status = (tal_trx_status_t)trx_bit_read(
SR_TRX_STATUS);
} while (tal_trx_status == STATE_TRANSITION_IN_PROGRESS);
return tal_trx_status;
} /* set_trx_state() */
/**
* @brief Sets transceiver state
*
* @param trx_cmd needs to be one of the trx commands
*
* @return current trx state
*/
tal_trx_status_t set_trx_state(trx_cmd_t trx_cmd)
{
if (tal_trx_status == TRX_SLEEP)
{
uint8_t bit_status;
PAL_SLP_TR_LOW();
do
{
bit_status = pal_trx_bit_read(SR_TRX_STATUS);
} while (bit_status != TRX_OFF);
if ((trx_cmd == CMD_TRX_OFF) || (trx_cmd == CMD_FORCE_TRX_OFF))
{
tal_trx_status = TRX_OFF;
return TRX_OFF;
}
}
tal_trx_status = (tal_trx_status_t)pal_trx_bit_read(SR_TRX_STATUS);
switch (trx_cmd) /* new state */
{
case CMD_TRX_SLEEP:
pal_trx_reg_write(RG_TRX_STATE, CMD_FORCE_TRX_OFF);
{
uint16_t rand_value;
/*
* Init the SEED value of the CSMA backoff algorithm.
*/
rand_value = (uint16_t)rand();
pal_trx_reg_write(RG_CSMA_SEED_0, (uint8_t)rand_value);
pal_trx_bit_write(SR_CSMA_SEED_1, (uint8_t)(rand_value >> 8));
}
PAL_WAIT_1_US();
PAL_SLP_TR_HIGH();
pal_timer_delay(TRX_OFF_TO_SLEEP_TIME);
tal_trx_status = TRX_SLEEP;
return TRX_SLEEP; /* transceiver register cannot be read during TRX_SLEEP */
//break; // do not use break, since it is unreachable
case CMD_TRX_OFF:
switch (tal_trx_status)
{
case TRX_OFF:
break;
default:
pal_trx_reg_write(RG_TRX_STATE, CMD_TRX_OFF);
PAL_WAIT_1_US();
break;
}
break;
case CMD_FORCE_TRX_OFF:
switch (tal_trx_status)
{
case TRX_OFF:
break;
case TX_ARET_ON:
pal_trx_reg_write(RG_TRX_STATE, CMD_FORCE_TRX_OFF);
PAL_SLP_TR_HIGH();
pal_timer_delay(2);
PAL_SLP_TR_LOW();
break;
default:
pal_trx_reg_write(RG_TRX_STATE, CMD_FORCE_TRX_OFF);
PAL_WAIT_1_US();
break;
}
break;
case CMD_PLL_ON:
switch (tal_trx_status)
{
case PLL_ON:
break;
case TRX_OFF:
switch_pll_on();
break;
case RX_ON:
case RX_AACK_ON:
case TX_ARET_ON:
pal_trx_reg_write(RG_TRX_STATE, CMD_PLL_ON);
PAL_WAIT_1_US();
break;
case BUSY_RX:
case BUSY_TX:
case BUSY_RX_AACK:
case BUSY_TX_ARET:
/* do nothing if trx is busy */
break;
default:
ASSERT("state transition not handled" == 0);
break;
}
break;
case CMD_FORCE_PLL_ON: /* software state */
switch (tal_trx_status)
{
case RX_ON:
case BUSY_RX:
case RX_AACK_ON:
case BUSY_RX_AACK:
ENTER_TRX_REGION();
pal_trx_reg_write(RG_TRX_STATE, CMD_FORCE_TRX_OFF);
pal_trx_reg_write(RG_TRX_STATE, CMD_PLL_ON);
// clear trx irq in case a frame is received meanwhile
pal_trx_reg_read(RG_IRQ_STATUS);
pal_trx_irq_flag_clr();
LEAVE_TRX_REGION();
PAL_WAIT_1_US();
break;
case BUSY_TX:
ENTER_TRX_REGION();
pal_trx_reg_write(RG_TRX_STATE, CMD_FORCE_TRX_OFF);
pal_trx_reg_write(RG_TRX_STATE, CMD_PLL_ON);
LEAVE_TRX_REGION();
PAL_WAIT_1_US();
break;
case BUSY_TX_ARET:
ENTER_TRX_REGION();
pal_trx_reg_write(RG_TRX_STATE, CMD_FORCE_TRX_OFF);
PAL_SLP_TR_LOW();
pal_timer_delay(SLP_TR_TOGGLE_US);
PAL_SLP_TR_HIGH();
pal_trx_reg_write(RG_TRX_STATE, CMD_PLL_ON);
LEAVE_TRX_REGION();
PAL_WAIT_1_US();
break;
case TRX_OFF:
switch_pll_on();
break;
case PLL_ON:
break;
default:
ASSERT("state transition not handled" == 0);
break;
}
break;
case CMD_RX_ON:
switch (tal_trx_status)
{
case RX_ON:
break;
case PLL_ON:
pal_trx_reg_write(RG_TRX_STATE, CMD_RX_ON);
PAL_WAIT_1_US();
break;
case TRX_OFF:
switch_pll_on();
pal_trx_reg_write(RG_TRX_STATE, CMD_RX_ON);
PAL_WAIT_1_US();
break;
case RX_AACK_ON:
case TX_ARET_ON:
pal_trx_reg_write(RG_TRX_STATE, CMD_PLL_ON);
PAL_WAIT_1_US();
// check if state change could be applied
tal_trx_status = (tal_trx_status_t)pal_trx_bit_read(SR_TRX_STATUS);
if (tal_trx_status != PLL_ON)
{
return tal_trx_status;
}
pal_trx_reg_write(RG_TRX_STATE, CMD_RX_ON);
PAL_WAIT_1_US();
break;
case BUSY_RX:
case BUSY_TX:
case BUSY_RX_AACK:
case BUSY_TX_ARET:
/* do nothing if trx is busy */
break;
default:
ASSERT("state transition not handled" == 0);
break;
}
break;
case CMD_RX_AACK_ON:
switch (tal_trx_status)
{
case RX_AACK_ON:
break;
case PLL_ON:
pal_trx_reg_write(RG_TRX_STATE, CMD_RX_AACK_ON);
PAL_WAIT_1_US();
break;
case TRX_OFF:
switch_pll_on();// state change from TRX_OFF to RX_AACK_ON can be done directly, too
pal_trx_reg_write(RG_TRX_STATE, CMD_RX_AACK_ON);
PAL_WAIT_1_US();
break;
case TX_ARET_ON:
case RX_ON:
pal_trx_reg_write(RG_TRX_STATE, CMD_PLL_ON);
PAL_WAIT_1_US();
// check if state change could be applied
tal_trx_status = (tal_trx_status_t)pal_trx_bit_read(SR_TRX_STATUS);
if (tal_trx_status != PLL_ON)
{
return tal_trx_status;
}
pal_trx_reg_write(RG_TRX_STATE, CMD_RX_AACK_ON);
PAL_WAIT_1_US();
break;
case BUSY_RX:
case BUSY_TX:
case BUSY_RX_AACK:
case BUSY_TX_ARET:
/* do nothing if trx is busy */
break;
default:
ASSERT("state transition not handled" == 0);
break;
}
break;
case CMD_TX_ARET_ON:
switch (tal_trx_status)
{
case TX_ARET_ON:
break;
case PLL_ON:
pal_trx_reg_write(RG_TRX_STATE, CMD_TX_ARET_ON);
PAL_WAIT_1_US();
break;
case RX_ON:
case RX_AACK_ON:
pal_trx_reg_write(RG_TRX_STATE, CMD_PLL_ON);
PAL_WAIT_1_US();
// check if state change could be applied
tal_trx_status = (tal_trx_status_t)pal_trx_bit_read(SR_TRX_STATUS);
if (tal_trx_status != PLL_ON)
{
return tal_trx_status;
}
pal_trx_reg_write(RG_TRX_STATE, CMD_TX_ARET_ON);
PAL_WAIT_1_US();
break;
case TRX_OFF:
switch_pll_on();// state change from TRX_OFF to TX_ARET_ON can be done directly, too
pal_trx_reg_write(RG_TRX_STATE, CMD_TX_ARET_ON);
PAL_WAIT_1_US();
break;
case BUSY_RX:
case BUSY_TX:
case BUSY_RX_AACK:
case BUSY_TX_ARET:
/* do nothing if trx is busy */
break;
default:
ASSERT("state transition not handled" == 0);
break;
}
break;
default:
/* CMD_NOP, CMD_TX_START */
ASSERT("trx command not handled" == 0);
break;
}
do
{
tal_trx_status = (tal_trx_status_t)pal_trx_bit_read(SR_TRX_STATUS);
} while (tal_trx_status == STATE_TRANSITION_IN_PROGRESS);
return tal_trx_status;
} /* set_trx_state() */
/**
* \brief Performs CCA twice
*/
static uint8_t perform_cca_twice(void)
{
tal_trx_status_t trx_status;
uint8_t cca_status;
uint8_t CW = 2;
uint32_t now_time_us;
do {
pal_get_current_time(&now_time_us);
} while (pal_add_time_us(now_time_us,
(SLEEP_TO_TRX_OFF_US + CCA_PREPARATION_DURATION_US)) <
cca_starttime_us);
/* Ensure that trx is at least in TRX_OFF mode at this time. */
if (tal_trx_status == TRX_SLEEP) {
set_trx_state(CMD_TRX_OFF);
}
do {
pal_get_current_time(&now_time_us);
} while (pal_add_time_us(now_time_us,
(PLL_LOCK_TIME_US + CCA_PREPARATION_DURATION_US)) <
cca_starttime_us);
/*
* Set trx to PLL_ON.
* If trx is busy and trx cannot be set to PLL_ON, assess channel as
*busy.
*/
if (set_trx_state(CMD_PLL_ON) != PLL_ON) {
return PHY_BUSY;
}
/* no interest in trx interrupts while doing CCA */
pal_trx_irq_dis();
/* do CCA twice */
do {
/* wait here until 16us before backoff boundary */
/* assume TRX is in PLL_ON */
do {
pal_get_current_time(&now_time_us);
} while (pal_add_time_us(now_time_us,
CCA_PRE_START_DURATION_US) <
cca_starttime_us);
set_trx_state(CMD_RX_ON);
/* debug pin to switch on: define ENABLE_DEBUG_PINS,
*pal_config.h */
PIN_CCA_START();
/* Start CCA by writing any dummy value to this register */
pal_trx_bit_write(SR_CCA_REQUEST, 1);
/* wait until CCA is done and get status */
pal_timer_delay(TAL_CONVERT_SYMBOLS_TO_US(CCA_DURATION_SYM));
do {
/* poll until CCA is really done; */
trx_status = (tal_trx_status_t)pal_trx_reg_read(
RG_TRX_STATUS);
} while ((trx_status & CCA_DONE_BIT) != CCA_DONE_BIT);
/* between both CCA switch trx to PLL_ON to reduce power
*consumption */
set_trx_state(CMD_PLL_ON);
/* debug pin to switch on: define ENABLE_DEBUG_PINS,
*pal_config.h */
PIN_CCA_END();
/* check if channel was idle or busy */
if (trx_status & CCA_STATUS_BIT) {
/* do next CCA at next backoff boundary */
cca_starttime_us = pal_add_time_us(cca_starttime_us,
TAL_CONVERT_SYMBOLS_TO_US(
aUnitBackoffPeriod));
CW--;
cca_status = PHY_IDLE;
} else { /* PHY busy */
cca_status = PHY_BUSY;
set_trx_state(CMD_RX_AACK_ON);
break; /* if channel is busy do no do CCA for the second
* time */
}
} while (CW > 0);
/*
* Keep trx ready for transmission if channel is idle.
* The transceiver is still in PLL_ON.
* If the channel is not idle, the trx handling is done in
*csma_backoff().
*/
/*
* Since we are not interested in any frames that might be received
* during CCA, reject any information that indicates a previous frame
* reception.
*/
pal_trx_reg_read(RG_IRQ_STATUS);
pal_trx_irq_flag_clr();
pal_trx_irq_en();
return cca_status;
}
/*
* \brief Perform a CCA
*
* This function performs a CCA request.
*
* \return phy_enum_t PHY_IDLE or PHY_BUSY
*/
phy_enum_t tfa_cca_perform(void)
{
tal_trx_status_t trx_status;
uint8_t cca_status;
/* Ensure that trx is not in SLEEP for register access */
do
{
trx_status = set_trx_state(CMD_TRX_OFF);
}
while (trx_status != TRX_OFF);
// no interest in trx interrupts while doing CCA
pal_trx_irq_dis();
/* Set trx to rx mode. */
do
{
trx_status = set_trx_state(CMD_RX_ON);
}
while (trx_status != RX_ON);
/* Start CCA by writing any dummy value to this register */
pal_trx_bit_write(SR_CCA_REQUEST, 1);
/* wait until CCA is done */
pal_timer_delay(TAL_CONVERT_SYMBOLS_TO_US(CCA_DURATION_SYM));
do
{
/*
* Poll until CCA is really done.
* Do NOT use bit read here!
*/
trx_status = (tal_trx_status_t)pal_trx_reg_read(RG_TRX_STATUS);
}
while ((trx_status & CCA_DONE_BIT) != CCA_DONE_BIT);
set_trx_state(CMD_TRX_OFF);
/* Check if channel was idle or busy. */
if (trx_status & CCA_STATUS_BIT)
{
cca_status = PHY_IDLE;
}
else
{
cca_status = PHY_BUSY;
}
/*
* Since we are not interested in any frames that might be received
* during CCA, reject any information that indicates a previous frame
* reception.
*/
pal_trx_reg_read(RG_IRQ_STATUS);
pal_trx_irq_flag_clr();
pal_trx_irq_en();
return (phy_enum_t)cca_status;
}
/**
* @brief Resets transceiver(s)
*
* @param trx_id Transceiver identifier
*
* @return MAC_SUCCESS if the transceiver returns TRX_OFF
* FAILURE otherwise
*/
retval_t trx_reset(trx_id_t trx_id)
{
ENTER_TRX_REGION();
uint32_t start_time;
uint32_t current_time;
pal_get_current_time(&start_time);
if (trx_id == RFBOTH) {
TAL_RF_IRQ_CLR_ALL(RF09);
TAL_RF_IRQ_CLR_ALL(RF24);
tal_state[RF09] = TAL_RESET;
tal_state[RF24] = TAL_RESET;
/* Apply reset pulse; low active */
#ifdef IQ_RADIO
RST_LOW();
PAL_WAIT_1_US();
PAL_WAIT_1_US();
RST_HIGH();
#if (BOARD_TYPE == EVAL215_FPGA)
pal_timer_delay(10000);
#endif
RST_LOW();
PAL_WAIT_1_US();
RST_HIGH();
#else
RST_LOW();
PAL_WAIT_1_US();
RST_HIGH();
#endif
/* Wait for IRQ line */
while (1) {
/*
* @ToDo: Use a different macro for IRQ line; the
*polarity might be
* different after reset
*/
#ifdef IQ_RADIO
if ((PAL_DEV_IRQ_GET(RF215_BB) == HIGH) &&
(PAL_DEV_IRQ_GET(RF215_RF) == HIGH)) {
break;
}
#else
if (TRX_IRQ_GET() == HIGH) {
break;
}
#endif
/* Handle timeout */
pal_get_current_time(¤t_time);
/* @ToDo: Remove magic number */
if (pal_sub_time_us(current_time, start_time) > 1000) {
return FAILURE;
}
}
#ifdef IQ_RADIO
trx_state[RF09] = (rf_cmd_state_t)pal_dev_reg_read(RF215_RF,
RG_RF09_STATE);
trx_state[RF24] = (rf_cmd_state_t)pal_dev_reg_read(RF215_RF,
RG_RF24_STATE);
rf_cmd_state_t bb_trx_state[NUM_TRX];
bb_trx_state[RF09] = (rf_cmd_state_t)pal_dev_reg_read(RF215_BB,
RG_RF09_STATE);
bb_trx_state[RF24] = (rf_cmd_state_t)pal_dev_reg_read(RF215_BB,
RG_RF24_STATE);
if ((bb_trx_state[RF09] != RF_TRXOFF) ||
(bb_trx_state[RF24] != RF_TRXOFF)) {
return FAILURE;
}
#else
trx_state[RF09] = trx_reg_read(RG_RF09_STATE);
trx_state[RF24] = trx_reg_read(RG_RF24_STATE);
#endif
if ((trx_state[RF09] != RF_TRXOFF) ||
(trx_state[RF24] != RF_TRXOFF)) {
return FAILURE;
}
/* Get all IRQ status information */
#ifdef IQ_RADIO
bb_irq_handler_cb();
rf_irq_handler_cb();
#else
trx_irq_handler_cb();
#endif
TAL_RF_IRQ_CLR(RF09, RF_IRQ_WAKEUP);
TAL_RF_IRQ_CLR(RF24, RF_IRQ_WAKEUP);
} else {
TAL_RF_IRQ_CLR_ALL(trx_id);
tal_state[trx_id] = TAL_RESET;
/* Trigger reset of device */
uint16_t reg_offset = RF_BASE_ADDR_OFFSET * trx_id;
#ifdef IQ_RADIO
pal_trx_reg_write(RF215_RF, reg_offset + RG_RF09_CMD, RF_RESET);
pal_trx_reg_write(RF215_BB, reg_offset + RG_RF09_CMD, RF_RESET);
#else
trx_reg_write(reg_offset + RG_RF09_CMD, RF_RESET);
#endif
/* Wait for IRQ line */
while (1) {
#ifdef IQ_RADIO
if ((PAL_DEV_IRQ_GET(RF215_BB) == HIGH) &&
(PAL_DEV_IRQ_GET(RF215_RF) == HIGH)) {
break;
}
#else
if (TRX_IRQ_GET() == HIGH) {
break;
}
#endif
/* Handle timeout */
pal_get_current_time(¤t_time);
/* @ToDo: Remove magic number */
if (pal_sub_time_us(current_time, start_time) > 1000) {
return FAILURE;
}
}
trx_state[trx_id] = RF_TRXOFF;
/* Get all IRQ status information */
#ifdef IQ_RADIO
bb_irq_handler_cb();
rf_irq_handler_cb();
#else
trx_irq_handler_cb();
#endif
TAL_RF_IRQ_CLR(trx_id, RF_IRQ_WAKEUP);
}
#ifdef IQ_RADIO
pal_trx_irq_flag_clr(RF215_BB);
pal_trx_irq_flag_clr(RF215_RF);
#else
pal_trx_irq_flag_clr();
#endif
LEAVE_TRX_REGION();
return MAC_SUCCESS;
}
/**
* @brief Initializes the TAL
*
* This function is called to initialize the TAL. The transceiver is
* initialized, the TAL PIBs are set to their default values, and the TAL state
* machine is set to TAL_IDLE state.
*
* @return MAC_SUCCESS if the transceiver state is changed to TRX_OFF and the
* current device part number and version number are correct;
* FAILURE otherwise
*/
retval_t tal_init(void)
{
/* Init the PAL and by this means also the transceiver interface */
if (pal_init() != MAC_SUCCESS) {
return FAILURE;
}
/* Reset trx */
if (trx_reset(RFBOTH) != MAC_SUCCESS) {
return FAILURE;
}
/* Check if RF215 is connected */
if ((trx_reg_read( RG_RF_PN) != 0x34) ||
(trx_reg_read( RG_RF_VN) != 0x01)) {
return FAILURE;
}
/* Initialize trx */
trx_init();
if (tal_timer_init() != MAC_SUCCESS) {
return FAILURE;
}
/* Initialize the buffer management */
bmm_buffer_init();
/* Configure both trx and set default PIB values */
for (uint8_t trx_id = 0; trx_id < NUM_TRX; trx_id++) {
/* Configure transceiver */
trx_config((trx_id_t)trx_id);
#ifdef RF215V1
/* Calibrate LO */
calibrate_LO((trx_id_t)trx_id);
#endif
/* Set the default PIB values */
init_tal_pib((trx_id_t)trx_id); /* see 'tal_pib.c' */
calculate_pib_values((trx_id_t)trx_id);
/*
* Write all PIB values to the transceiver
* that are needed by the transceiver itself.
*/
write_all_tal_pib_to_trx((trx_id_t)trx_id); /* see 'tal_pib.c'
**/
config_phy((trx_id_t)trx_id);
tal_rx_buffer[trx_id] = bmm_buffer_alloc(LARGE_BUFFER_SIZE);
if (tal_rx_buffer[trx_id] == NULL) {
return FAILURE;
}
/* Init incoming frame queue */
qmm_queue_init(&tal_incoming_frame_queue[trx_id]);
tal_state[trx_id] = TAL_IDLE;
tx_state[trx_id] = TX_IDLE;
}
/* Init seed of rand() */
tal_generate_rand_seed();
#ifndef DISABLE_IEEE_ADDR_CHECK
for (uint8_t trx_id = 0; trx_id < 2; trx_id++) {
/* Check if a valid IEEE address is available. */
/*
* This while loop is on purpose, since just in the
* rare case that such an address is randomly
* generated again, we must repeat this.
*/
while ((tal_pib[trx_id].IeeeAddress == 0x0000000000000000) ||
(tal_pib[trx_id].IeeeAddress ==
((uint64_t)-1))) {
/*
* In case no valid IEEE address is available, a random
* IEEE address will be generated to be able to run the
* applications for demonstration purposes.
* In production code this can be omitted.
*/
/*
* The proper seed for function rand() has already been
*generated
* in function tal_generate_rand_seed().
*/
uint8_t *ptr_pib
= (uint8_t *)&tal_pib[trx_id].IeeeAddress;
for (uint8_t i = 0; i < 8; i++) {
*ptr_pib++ = (uint8_t)rand();
/*
* Note:
* Even if casting the 16 bit rand value back to
*8 bit,
* and running the loop 8 timers (instead of
*only 4 times)
* may look cumbersome, it turns out that the
*code gets
* smaller using 8-bit here.
* And timing is not an issue at this place...
*/
}
}
}
#endif
#ifdef IQ_RADIO
/* Init BB IRQ handler */
pal_trx_irq_flag_clr(RF215_BB);
trx_irq_init(RF215_BB, bb_irq_handler_cb);
pal_trx_irq_en(RF215_BB);
/* Init RF IRQ handler */
pal_trx_irq_flag_clr(RF215_RF);
trx_irq_init(RF215_RF, rf_irq_handler_cb);
pal_trx_irq_en(RF215_RF);
#else
/*
* Configure interrupt handling.
* Install a handler for the radio and the baseband interrupt.
*/
pal_trx_irq_flag_clr();
trx_irq_init((FUNC_PTR)trx_irq_handler_cb);
pal_trx_irq_en(); /* Enable transceiver main interrupt. */
#endif
#if ((defined SUPPORT_FSK) && (defined SUPPORT_MODE_SWITCH))
init_mode_switch();
#endif
return MAC_SUCCESS;
} /* tal_init() */
