LOCAL STATUS sysPciAutoconfigInclude
(
PCI_SYSTEM *pSys, /* PCI_SYSTEM structure pointer */
PCI_LOC *pLoc, /* pointer to function in question */
UINT devVend /* deviceID/vendorID of device */
)
{
/* Never configure the PCI host bridge. */
if (devVend == SIBYTE_DEVICE(BCM1250_PCI_HOST_BRIDGE))
return ERROR;
/* In PCI Device Mode, skip all other bus 0 devices except
the LDT host bridge, which the hardware defines to be device 1. */
if (pciDeviceMode && (pLoc->bus == 0 && pLoc->device != 1))
return ERROR;
/* In a double-hosted system, never configure the LDT host bridge
at the far end of the chain, which will have its DBL_ENDED bit
set by sizing.. */
if (devVend == SIBYTE_DEVICE(BCM1250_LDT_HOST_BRIDGE))
{
UINT32 cpr, lr;
UINT32 offset;
pciConfigInLong (pLoc->bus, pLoc->device, 0, PCI_CFG_CAP_PTR, &cpr);
offset = cpr & 0xFC;
pciConfigInLong (pLoc->bus, pLoc->device, 0, offset, &lr);
if ((lr & 0x00020000 /*LDTCAP_CMD_DBL_ENDED*/) != 0)
return ERROR;
}
return OK; /* Autoconfigure all other devices */
}
uint32 pci_config_getw(pci_dev_t *dev, uint32 addr)
{
UINT32 inWord = 0;
STATUS requestStatus;
assert(! (addr & 3));
debugk(DK_PCI, "PCI(%d,%d,%d) configR(0x%x)=",
dev->busNo, dev->devNo, dev->funcNo, addr);
requestStatus = pciConfigInLong(dev->busNo,
dev->devNo,
dev->funcNo,
addr,
(UINT32*) &inWord);
if (requestStatus != OK) {
printk("ERROR: PCI configuration read bus=%d dev=%d func=%d "
"(0x%x=0x%x) -READ ERROR(%d)\n",
dev->busNo, dev->devNo, dev->funcNo, addr, inWord,
requestStatus);
return -1;
} else {
debugk(DK_PCI, "0x%x\n", inWord);
return inWord;
}
}
uint32
osl_pci_read_config(pciinfo_t *pciinfo, uint offset, uint size)
{
uint32 val;
ASSERT(size == 4);
pciConfigInLong(pciinfo->bus, pciinfo->dev, pciinfo->func, offset, &val);
return(val);
}
/*
* Temp - display raw PCI header
*/
void
read_pci_conf(int bus, int dev, int func, int begin, int end)
{
int i;
unsigned int pdata;
printf("bus %d dev %d func %d\n", bus, dev, func);
for(i = begin; i <= end; i += 4) {
pciConfigInLong(bus, dev, func, i, &pdata);
printf("REG%02x = 0x%08x\n", i, pdata);
}
return;
}
LOCAL void sysPciAutoconfigPostEnumBridgeInit
(
PCI_SYSTEM *pSys, /* PCI_SYSTEM structure pointer */
PCI_LOC *pLoc, /* pointer to function in question */
UINT devVend /* deviceID/vendorID of device */
)
{
if (devVend == API_DEVICE(API_STURGEON))
{
UINT32 readParams;
UINT32 intMap;
UINT32 t, offset;
/* set up READ register: Prefetch enable, 2 lines of fetch ahead */
readParams = (2 << 5) | (2 << 2) | 0x3;
pciConfigOutLong (pLoc->bus, pLoc->device, pLoc->function,
LPB_CFG_READ, readParams);
/* Setup interrupt mapping for Block 1:
Enabled, Dest=Logical (CPU 0), Type=Fixed, Trigger=Edge */
intMap = (LPB_INT_CTRL_ENABLE |
LPB_INT_CTRL_DESTMODE | /* Logical */
(0x1 << LPB_INT_CTRL_DEST_SHIFT) | /* CPU 0 */
(0x0 << LPB_INT_CTRL_MSGTYPE_SHIFT)); /* Fixed */
/* For the SWARM and CSWARMs, the LDT Host Bridge is assumed to
have the base interrupt mapping (by convention) and the
LDT device number is the effective "slot" number. */
offset = pLoc->device;
t = (intMap + offset);
offset = (offset+1) % 4;
t |= (intMap + offset) << 16;
pciConfigOutLong (pLoc->bus, pLoc->device, pLoc->function,
LPB_CFG_INT_CTRL_BASE + 8, t);
offset = (offset+1) % 4;
t = (intMap + offset);
offset = (offset+1) % 4;
t |= (intMap + offset) << 16;
pciConfigOutLong (pLoc->bus, pLoc->device, pLoc->function,
LPB_CFG_INT_CTRL_BASE + 12, t);
pciConfigInLong (pLoc->bus, pLoc->device, pLoc->function,
LPB_CFG_INT_BLOCK1, &t);
t &= 0xFFFFFF00;
t |= (0x40 | (BCM1250_PCI_LDT_INT_MAP(BCM1250_PCI_INT_BASE) >> 2));
pciConfigOutLong (pLoc->bus, pLoc->device, pLoc->function,
LPB_CFG_INT_BLOCK1, t);
}
VOID sysPciIoApicEnable
(
BOOL enable /* TRUE to enable, FALSE to disable */
)
{
#if defined (INCLUDE_ICH2) || defined (INCLUDE_ICH3)
INT32 pciBusLpc = ICH2_LPC_PCI_BUSNO; /* bus# of ICH2/3 LPC */
INT32 pciDevLpc = ICH2_LPC_PCI_DEVNO; /* dev# of ICH2/3 LPC */
INT32 pciFuncLpc = ICH2_LPC_PCI_FUNCNO; /* func# of ICH2/3 LPC */
INT32 value; /* PCI config reg value */
UINT16 vendorId;
UINT16 deviceId;
/* is there ICH2 or ICH3? */
pciConfigInWord (pciBusLpc, pciDevLpc, pciFuncLpc,
PCI_CFG_VENDOR_ID, &vendorId);
pciConfigInWord (pciBusLpc, pciDevLpc, pciFuncLpc,
PCI_CFG_DEVICE_ID, &deviceId);
if (!(((vendorId == ICH2_LPC_VID) &&
((deviceId == ICH2_LPC_DID_S) || (deviceId == ICH2_LPC_DID_M))) ||
((vendorId == ICH3_LPC_VID) &&
((deviceId == ICH3_LPC_DID_S) || (deviceId == ICH3_LPC_DID_M)))))
return;
/* enables or disables 1) IOAPIC address decode 2) IO XAPIC extensions */
pciConfigInLong (pciBusLpc, pciDevLpc, pciFuncLpc,
ICH2_LPC_GEN_CNTL, &value);
if (enable)
value |= (ICH2_APICEN | ICH2_XAPIC_EN);
else
value &= ~(ICH2_APICEN | ICH2_XAPIC_EN);
pciConfigOutLong (pciBusLpc, pciDevLpc, pciFuncLpc,
ICH2_LPC_GEN_CNTL, value);
#endif /* defined (INCLUDE_ICH2) || defined (INCLUDE_ICH3) */
}
uint32
osl_pci_read_config(osl_t *osh, unsigned int offset, unsigned int size)
{
uint32 val;
uint retry = PCI_CFG_RETRY; /* PR15065: faulty cardbus controller bug */
pciinfo_t *pciinfo = (pciinfo_t *)(osh->devinfo);
ASSERT(size == 4);
do {
pciConfigInLong(pciinfo->bus, pciinfo->dev, pciinfo->func, offset, &val);
if (val != 0xffffffff)
break;
} while (retry--);
#ifdef BCMDBG
if (retry < PCI_CFG_RETRY)
printf("PCI CONFIG READ access to %d required %d retries\n", offset,
(PCI_CFG_RETRY - retry));
#endif /* BCMDBG */
return (val);
}
END_OBJ *sysDec21x40EndLoad
(
char *pParamStr, /* ptr to initialization parameter string */
void *hwUnit /* Tulip unit number */
)
{
/*
* The format of the parameter string should be:
* "<unit number>:<device addr>:<PCI addr>:"
* "<ivec>:<ilevel>:<numRds>:<numTds>:<mem base>:<mem size>:"
* "<user flags>:<phyAddr>:<pPhyTbl>:<phyFlags>:<offset>"
*/
int unit = (int) hwUnit;
char *cp;
char paramStr [END_INIT_STR_MAX]; /* from end.h */
static char dec21x40ParamTemplate [] =
"%#x:0:%#x:0:-1:-1:-1:0:%#x::::2";
int busNo, deviceNo, funcNo;
UINT32 flags;
UINT32 csrAdrs;
UINT8 intLine;
UINT32 cfdd;
END_OBJ *pEnd;
if (strlen (pParamStr) == 0)
{
/*
* muxDevLoad() calls us twice. If the string is
* zero length, then this is the first time through
* this routine, so we just return.
*/
pEnd = dec21x40EndLoad (pParamStr);
}
else
{
if (pciFindDevice (VENDOR_ID_DEC, DEVICE_ID_21143, unit,
&busNo, &deviceNo, &funcNo) == OK)
{
flags = DEC_USR_21143;
}
else
if (pciFindDevice (VENDOR_ID_DEC, DEVICE_ID_21140, unit,
&busNo, &deviceNo, &funcNo) == OK)
{
flags = DEC_USR_21140;
}
else
if (pciFindDevice (VENDOR_ID_DEC, DEVICE_ID_21041, unit,
&busNo, &deviceNo, &funcNo) == OK)
{
flags = 0;
}
else
{
return (END_OBJ *)ERROR;
}
pciConfigInLong (busNo, deviceNo, funcNo, DEC_CFG_CBMA, &csrAdrs);
pciConfigInByte (busNo, deviceNo, funcNo, DEC_CFG_CFIT, &intLine);
/* Make sure that chip is out of sleep mode. */
pciConfigInLong (busNo, deviceNo, funcNo, DEC_CFG_CFDD, &cfdd);
pciConfigOutLong (busNo, deviceNo, funcNo, DEC_CFG_CFDD, 0);
pciConfigInLong (busNo, deviceNo, funcNo, DEC_CFG_CFDD, &cfdd);
/*
* On the second pass though here, we actually create
* the initialization parameter string on the fly.
* Note that we will be handed our unit number on the
* second pass through and we need to preserve that information.
* So we use the unit number handed from the input string.
*/
cp = strcpy (paramStr, pParamStr); /* cp points to paramStr */
/* Now, we advance cp, by finding the end the string */
cp += strlen (paramStr);
/* finish off the initialization parameter string */
flags |= DEC_USR_CAL_08 | DEC_USR_PBL_32 | DEC_USR_RML | DEC_USR_SF;
sprintf (cp, dec21x40ParamTemplate, csrAdrs, intLine, flags);
if ((pEnd = dec21x40EndLoad (paramStr)) == (END_OBJ *)ERROR)
{
printf ("Error: dec21x40 device failed EndLoad routine.\n");
}
}
return (pEnd);
}
int probe1()
{
unsigned int pciBusNo, pciDevNo, pciFuncNo;
unsigned char byte;
/* int i,j;*/
UINT32 s_pBA0, s_pBA1;
/* To ensure that taskDelay(1) is 1ms delay */
sysClkRateSet(1000);
if (pciConfigLibInit (PCI_MECHANISM_1, 0xCF8, 0xCFC, 0) != OK) {
printf("PCI lib config error\n");
return 1;
}
/****************************
* Find SoundCard
* Set BaseAddr0, BaseAddr1
****************************/
if(!(pciFindDevice(PCI_VENDOR_ID_CIRRUS,PCI_DEVICE_ID_CRYSTAL_CS4281,
0, &pciBusNo, &pciDevNo, &pciFuncNo)==OK)) {
printf("\n CS4281 sound card NOT FOUND!!! \n");
return 1;
}
printf("\n FOUND CS4281 sound card, configuring BA0,BA1... \n");
pciConfigOutLong( pciBusNo, pciDevNo, pciFuncNo,
PCI_CFG_BASE_ADDRESS_0, CS4281_pBA0);
/*
pciConfigOutLong( pciBusNo, pciDevNo, pciFuncNo,
PCI_CFG_BASE_ADDRESS_1, CS4281_pBA1);
*/
pciConfigInLong( pciBusNo, pciDevNo, pciFuncNo,
PCI_CFG_BASE_ADDRESS_0, &s_pBA0);
pciConfigInLong( pciBusNo, pciDevNo, pciFuncNo,
PCI_CFG_BASE_ADDRESS_1, &s_pBA1 );
printf ("\npBusNo pDeviceNo pFuncNo pBA0 pBA1\n\n");
printf ("%.8x %.8x %.8x %.8x %.8x \n",
pciBusNo, pciDevNo, pciFuncNo, s_pBA0,s_pBA1);
/********************************
* Config PCI Device Capability
* DMA Master
* MEM mapped
********************************/
/* Set the INTA vector */
pciConfigInByte(pciBusNo, pciDevNo, pciFuncNo,
PCI_CFG_DEV_INT_LINE, &cs4281_irq);
printf("\nFound CS4281 configured for IRQ %d\n", cs4281_irq);
pciConfigInByte(pciBusNo, pciDevNo, pciFuncNo,
PCI_CFG_DEV_INT_PIN, &byte);
printf("\tINT_PIN=%.8x\n", byte);
/* Enable the device's capabilities as specified
* Bus Master Enable/ Mem Space Enable */
pciConfigOutWord(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_COMMAND,
(unsigned short)0x0006);
/***************************
* BringUp Hardware
***************************/
/*Include Init Function Here*/
cs4281_hw_init();
/****************************
* Allocate ADC_BUFFER
* Allocate DAC_BUFFER
*
* Hook cs4281_interrupt
*
* Program CoDec
****************************/
if((DAC_BUFFER=valloc(DAC_BUFFER_SIZE))==NULL) {
printf("\n DAC_BUFFER valloc failed!\n");
return 1;
}
memset( DAC_BUFFER, 0, DAC_BUFFER_SIZE );
printf("\ndac=%x",DAC_BUFFER);
/*for( i=0 ; i < DAC_BUFFER_SIZE ; i++ )
((char *)DAC_BUFFER)[i]=0x7f;*/
writel((UINT32)DAC_BUFFER+8,CS4281_pBA0 + BA0_DBA0);
writel(DAC_BUFFER_SIZE-16, CS4281_pBA0 + BA0_DBC0);
printf("\nbao=%x",readl(CS4281_pBA0 + BA0_DBA0));
printf("\nbco=%x",readl(CS4281_pBA0 + BA0_DBC0));
printf("\ncco=%x",readl(CS4281_pBA0 + BA0_DCC0));
if((ADC_BUFFER=valloc(ADC_BUFFER_SIZE))==NULL) {
printf("\n ADC_BUFFER valloc failed!\n");
return 1;
}
printf("\nadc=%x",ADC_BUFFER);
/*for( i=0 ; i < ADC_BUFFER_SIZE ; i++ )
((char *)ADC_BUFFER)[i]=0x7f;*/
writel((UINT32)ADC_BUFFER+8,CS4281_pBA0 + BA0_DBA1);
writel(ADC_BUFFER_SIZE-16, CS4281_pBA0 + BA0_DBC1);
/* connect interrupt */
printf("\n Hook cs4281_interrupt to vector %d\n",
(INUM_TO_IVEC (cs4281_irq+INT_NUM_IRQ0)));
pciIntConnect((INUM_TO_IVEC (cs4281_irq+INT_NUM_IRQ0)),
(VOIDFUNCPTR)cs4281_interrupt, 0);
sysIntEnablePIC(cs4281_irq);
SEM_DMA_Playback = semBCreate(SEM_Q_FIFO,SEM_EMPTY);
SEM_MY_Playback = semBCreate(SEM_Q_FIFO,SEM_EMPTY);
SEM_DMA_Record = semBCreate(SEM_Q_FIFO,SEM_EMPTY);
SEM_Sample = semBCreate(SEM_Q_FIFO,SEM_EMPTY);
CNT_DMA_Playback = CNT_DMA_Record = 0;
/* program coDec */
printf("\n Program CoDec (sample rate, DMA...)\n");
prog_codec();
/*********************************************
* start dac/adc, interrupt is comming...
*********************************************/
start_dac();
return 0;
}
void sysAic7880PciInit(void)
{
int busNo; /* PCI bus number */
int devNo; /* PCI device number */
int funcNo; /* PCI function number */
int index = 0; /* desired instance of device */
UINT32 membaseCsr; /* base address 0 */
UINT32 iobaseCsr; /* base address 1 */
char irq; /* IRQ level */
AIC7880_INFO *aicRes;
aicRes = &aic7880InfoTable;
if ((pciFindDevice (AIC7880_PCI_VENDOR_ID, AIC7880_PCI_DEVICE_ID,
index, &busNo, &devNo, &funcNo)) != OK)
{
logMsg("AIC 7880 SCSI controller not found\n", 0, 0, 0, 0, 0, 0);
return;
}
/* if PCI_CFG_FORCE is specified then set configuration parameters */
if (PCI_CFG_TYPE == PCI_CFG_FORCE)
{
pciConfigOutLong(busNo, devNo, funcNo, PCI_CFG_BASE_ADDRESS_0,
AIC7880_IOBASE);
pciConfigOutLong(busNo, devNo, funcNo, PCI_CFG_BASE_ADDRESS_1,
AIC7880_MEMBASE);
pciConfigOutByte(busNo, devNo, funcNo, PCI_CFG_DEV_INT_LINE,
AIC7880_INT_LVL);
}
/* read the configuration parameters */
pciConfigInLong(busNo, devNo, funcNo, PCI_CFG_BASE_ADDRESS_0,
&iobaseCsr);
pciConfigInLong(busNo, devNo, funcNo, PCI_CFG_BASE_ADDRESS_1,
&membaseCsr);
pciConfigInByte(busNo, devNo, funcNo, PCI_CFG_DEV_INT_LINE,
&irq);
membaseCsr &= PCI_MEMBASE_MASK;
iobaseCsr &= PCI_IOBASE_MASK;
/* update the mmu table */
if (sysMmuMapAdd((void *)membaseCsr, (UINT)AIC7880_MEMSIZE,
(UINT)AIC7880_INIT_STATE_MASK,
(UINT)AIC7880_INIT_STATE) == ERROR)
{
logMsg("Unable map requested memory\n", 0, 0, 0, 0, 0, 0);
return;
}
/* update the device specific info */
aicRes->pciBus = busNo;
aicRes->pciDevice = devNo;
aicRes->pciFunc = funcNo;
aicRes->irq = irq;
/* enable mapped memory and IO addresses */
pciConfigOutWord (aicRes->pciBus, aicRes->pciDevice, aicRes->pciFunc,
PCI_CFG_COMMAND, PCI_CMD_IO_ENABLE |
PCI_CMD_MEM_ENABLE | PCI_CMD_MASTER_ENABLE);
}
STATUS sysRtl81x9PciInit (
UINT32 pciBus, /* store a PCI bus number */
UINT32 pciDevice, /* store a PCI device number */
UINT32 pciFunc, /* store a PCI function number */
UINT32 vendorId, /* store a PCI vendor ID */
UINT32 deviceId, /* store a PCI device ID */
UINT8 revisionId /* store a PCI revision ID */
)
{
UINT32 membaseCsr;
UINT32 iobaseCsr;
char irq;
RTL81X9_PCI_RESOURCES * pRsrc;
/* for all the support network devices find if some of them exist */
sysDebugTrace(0x70);
if(rtl81x9EndUnits >= RTL81X9_MAX_DEV){
return ERROR;
}
/* load up the PCI device table */
pRsrc = rtl81x9PciResrcs + rtl81x9EndUnits;
pRsrc->pciBus = pciBus;
pRsrc->pciDevice = pciDevice;
pRsrc->pciFunc = pciFunc;
rtl81x9EndUnits++; /* number of units found */
sysDebugTrace(0x72);
/* Now initialize the unit */
/* Fill in the resource entry */
sysDebugTrace(0x74);
/*
* get memory base address and IO base address
* Note: we read it in again, even if we just wrote it out because
* the device can change what we wrote
*/
pciConfigInLong (pRsrc->pciBus,
pRsrc->pciDevice,
pRsrc->pciFunc,
PCI_CFG_BASE_ADDRESS_0, &iobaseCsr);
pciConfigInLong (pRsrc->pciBus,
pRsrc->pciDevice,
pRsrc->pciFunc,
PCI_CFG_BASE_ADDRESS_1, &membaseCsr);
pciConfigInByte (pRsrc->pciBus,
pRsrc->pciDevice,
pRsrc->pciFunc,
PCI_CFG_DEV_INT_LINE, &irq);
sysDebugTrace(0x75);
/*
* mask off registers. IO base needs to be masked off because bit0
* will always be set to 1
*/
membaseCsr &= PCI_MEMBASE_MASK;
iobaseCsr &= PCI_IOBASE_MASK;
#if defined(INCLUDE_MMU_BASIC) || defined(INCLUDE_MMU_FULL)
sysDebugTrace(0x76);
if (sysMmuMapAdd ((void *)(membaseCsr & PCI_DEV_MMU_MSK),
VM_PAGE_SIZE,
VM_STATE_MASK_FOR_ALL,
VM_STATE_FOR_PCI
) == ERROR)
{
/* for now, exit, but later break and stop where we're at
when we're detecting multiple units */
return (ERROR);
}
#endif /* INCLUDE_MMU_BASIC */
sysDebugTrace(0x78);
/* over write the resource table with values read */
pRsrc->membaseCsr = membaseCsr;
pRsrc->iobaseCsr = iobaseCsr;
pRsrc->irq = irq;
pRsrc->irqvec = irq + EXT_INTERRUPT_BASE;
/* enable mapped memory and IO addresses */
pciConfigOutWord (pRsrc->pciBus,
pRsrc->pciDevice,
pRsrc->pciFunc,
PCI_CFG_COMMAND, PCI_CMD_IO_ENABLE |
PCI_CMD_MEM_ENABLE | PCI_CMD_MASTER_ENABLE);
/* disable sleep mode */
sysDebugTrace(0x79);
pciConfigOutWord (
pRsrc->pciBus,
pRsrc->pciDevice,
pRsrc->pciFunc,
PCI_CFG_MODE,
SLEEP_MODE_DIS);
rtl81x9Resources[rtl81x9EndUnits-1][0]=membaseCsr;
rtl81x9Resources[rtl81x9EndUnits-1][1]=irq;
rtl81x9Resources[rtl81x9EndUnits-1][2]=irq+EXT_INTERRUPT_BASE;
sysDebugTrace(0x7a);
return OK;
}
void sysPciPirqShow (void)
{
# if defined (INCLUDE_ICH2) || defined (INCLUDE_ICH3)
{
INT32 ix;
/* show the PIRQ[A-H] - IRQ[0-15] routing table */
for (ix = 0; ix < N_IOAPIC_PIRQS; ix++)
{
printf ("PIRQ%c: offset=0x%04x, PIRQ=0x%02x, IRQ=0x%02x\n",
'A' + ix,
sysPciPirqTbl[ix].offset,
sysPciPirqTbl[ix].pirq,
sysPciPirqTbl[ix].irq);
}
}
# endif /* defined (INCLUDE_ICH2) || defined (INCLUDE_ICH3) */
# ifdef INCLUDE_UNKNOWN_MOTHER
{
INT32 ix;
/* show the network device table */
for (ix = 0; ix < sysPciNnets; ix++)
{
printf ("bus=0x%04x dev=0x%04x venId=0x%04x "
"devId=0x%04x intPin=0x%02x intLine=0x%02x\n",
sysPciNetTbl[ix].pciBus,
sysPciNetTbl[ix].pciDev,
sysPciNetTbl[ix].vendorId,
sysPciNetTbl[ix].deviceId,
sysPciNetTbl[ix].intPin,
sysPciNetTbl[ix].intLine);
}
}
# elif defined (INCLUDE_D815EEA) || defined (INCLUDE_D850GB)
{
INT32 pciBusSlot = MOTHER_PCI_BUSNO_SLOT;
INT32 pciFuncSlot = MOTHER_PCI_FUNCNO_SLOT;
FUNCPTR defIsr; /* ISR of the default IRQ */
FUNCPTR curIsr; /* ISR of the current IRQ */
INT32 idtType; /* IDT type */
INT32 selector; /* CS selector */
INT32 vendorId; /* PCI vendor Id */
UINT8 intPin; /* PCI INT[A-D] from PCI Int Pin Reg */
UINT8 defIrq; /* default IRQ */
UINT8 curIrq; /* current IRQ */
UINT8 pirq; /* PIRQ[n] */
INT32 ix;
for (ix = 0; ix < N_PCI_SLOTS; ix++)
{
/* skip if the slot is empty */
pciConfigInLong (pciBusSlot, sysPciSlotTbl[ix], pciFuncSlot,
PCI_CFG_VENDOR_ID, &vendorId);
if ((vendorId & 0x0000ffff) == 0x0000ffff)
{
printf ("slot %d: empty \n", ix);
continue;
}
/* get the PCI INT[A-D] and IRQ[0-15] of the device */
pciConfigInByte (pciBusSlot, sysPciSlotTbl[ix], pciFuncSlot,
PCI_CFG_DEV_INT_PIN, &intPin);
pciConfigInByte (pciBusSlot, sysPciSlotTbl[ix], pciFuncSlot,
PCI_CFG_DEV_INT_LINE, &curIrq);
/* get the PIRQ[A-H] of the device */
pirq = sysPciIntTbl[ix][intPin - 1];
/* if sysPciPirqTbl[] table is not initialized, use the curIrq */
defIrq = sysPciPirqTbl[pirq - IOAPIC_PIRQA_INT_LVL].irq;
/* get the default Isr and current Isr */
intVecGet2 ((FUNCPTR *)INUM_TO_IVEC (INT_NUM_GET (defIrq)),
&defIsr, &idtType, &selector);
intVecGet2 ((FUNCPTR *)INUM_TO_IVEC (INT_NUM_GET (curIrq)),
&curIsr, &idtType, &selector);
/* show the default IRQ and the current IRQ setting */
printf ("slot %d: def-IRQ(ISR) = 0x%04x(0x%08x) "
"cur-IRQ(ISR) = 0x%04x(0x%08x)\n",
ix, defIrq, (int)defIsr, curIrq, (int)curIsr);
}
}
# endif /* INCLUDE_UNKNOWN_MOTHER */
}
VOID sysPciPirqEnable
(
BOOL enable /* TRUE to enable, FALSE to disable */
)
{
static BOOL sysPciFirstTime = TRUE;
if (sysPciFirstTime)
{
# if defined (INCLUDE_ICH2) || defined (INCLUDE_ICH3)
{
INT32 pciBusLpc = ICH2_LPC_PCI_BUSNO;
INT32 pciDevLpc = ICH2_LPC_PCI_DEVNO;
INT32 pciFuncLpc = ICH2_LPC_PCI_FUNCNO;
INT32 pirq;
UINT8 irq;
/* saves the default PIRQ[A-H] routing info */
for (pirq = 0; pirq < N_IOAPIC_PIRQS; pirq++)
{
pciConfigInByte (pciBusLpc, pciDevLpc, pciFuncLpc,
sysPciPirqTbl[pirq].offset, &irq);
sysPciPirqTbl[pirq].irq = (irq & ~ICH2_IRQ_DIS);
}
}
# endif /* defined (INCLUDE_ICH2) || defined (INCLUDE_ICH3) */
# ifdef INCLUDE_UNKNOWN_MOTHER
{
INT32 pciBus;
INT32 pciDev;
UINT16 vendorId;
UINT16 deviceId;
UINT8 classCode;
UINT8 intPin;
UINT8 intLine;
INT32 ix;
/* collect the PCI network device info */
ix = 0;
for (pciBus = 0; pciBus < PCI_MAX_BUS; pciBus++)
{
for (pciDev = 0; pciDev < PCI_MAX_DEV; pciDev++)
{
/* just PCI function 0 for now */
pciConfigInWord (pciBus, pciDev, 0, PCI_CFG_VENDOR_ID,
&vendorId);
pciConfigInWord (pciBus, pciDev, 0, PCI_CFG_DEVICE_ID,
&deviceId);
pciConfigInByte (pciBus, pciDev, 0, PCI_CFG_CLASS,
&classCode);
pciConfigInByte (pciBus, pciDev, 0, PCI_CFG_DEV_INT_PIN,
&intPin);
pciConfigInByte (pciBus, pciDev, 0, PCI_CFG_DEV_INT_LINE,
&intLine);
/* just PCI network card for now */
if ((vendorId != 0xffff) && (classCode == 0x2))
{
if (ix < N_PCI_NETS)
{
sysPciNetTbl[ix].pciBus = pciBus;
sysPciNetTbl[ix].pciDev = pciDev;
sysPciNetTbl[ix].pciFunc = 0;
sysPciNetTbl[ix].vendorId = vendorId;
sysPciNetTbl[ix].deviceId = deviceId;
sysPciNetTbl[ix].classCode = classCode;
sysPciNetTbl[ix].intPin = intPin;
sysPciNetTbl[ix].intLine = intLine;
ix++;
}
sysPciNnets++;
}
}
}
}
# endif /* INCLUDE_UNKNOWN_MOTHER */
sysPciFirstTime = FALSE;
}
/* enables or disables the PIRQ direct handling */
# if defined (INCLUDE_ICH2) || defined (INCLUDE_ICH3)
{
INT32 pciBusLpc = ICH2_LPC_PCI_BUSNO;
INT32 pciDevLpc = ICH2_LPC_PCI_DEVNO;
INT32 pciFuncLpc = ICH2_LPC_PCI_FUNCNO;
INT32 pirq;
for (pirq = 0; pirq < N_IOAPIC_PIRQS; pirq++)
{
if (enable)
{
pciConfigOutByte (pciBusLpc, pciDevLpc, pciFuncLpc,
sysPciPirqTbl[pirq].offset,
(sysPciPirqTbl[pirq].irq | ICH2_IRQ_DIS));
}
else
{
pciConfigOutByte (pciBusLpc, pciDevLpc, pciFuncLpc,
sysPciPirqTbl[pirq].offset,
(sysPciPirqTbl[pirq].irq & ~ICH2_IRQ_DIS));
}
}
}
# endif /* defined (INCLUDE_ICH2) || defined (INCLUDE_ICH3) */
/* set the PIRQ[A-H] to PCI_CFG_DEV_INT_LINE for direct handling */
# ifdef INCLUDE_UNKNOWN_MOTHER
{
INT32 ix;
if (enable)
{
/*
* INT_LINE should have IRQ number of PIRQ[A-H] (16 - 23).
* Since INT[A-D] to PIRQ[A-H] wiring info is unknown, value to set
* is unknown too. So set PIRQA to PCI_CFG_DEV_INT_LINE for now.
* Note, setting PIRQA does not mean the device generates PIRQA.
*/
for (ix = 0; ix < sysPciNnets; ix++)
{
pciConfigOutByte (sysPciNetTbl[ix].pciBus, sysPciNetTbl[ix].pciDev,
sysPciNetTbl[ix].pciFunc, PCI_CFG_DEV_INT_LINE,
IOAPIC_PIRQA_INT_LVL);
}
}
else
{
/* restore the original IRQn to PCI_CFG_DEV_INT_LINE */
for (ix = 0; ix < sysPciNnets; ix++)
{
pciConfigOutByte (sysPciNetTbl[ix].pciBus, sysPciNetTbl[ix].pciDev,
sysPciNetTbl[ix].pciFunc, PCI_CFG_DEV_INT_LINE,
sysPciNetTbl[ix].intLine);
}
}
}
# elif defined (INCLUDE_D815EEA) || defined (INCLUDE_D850GB)
{
INT32 pciBusSlot = MOTHER_PCI_BUSNO_SLOT;
INT32 pciFuncSlot = MOTHER_PCI_FUNCNO_SLOT;
INT32 pciBusLpc = ICH2_LPC_PCI_BUSNO;
INT32 pciDevLpc = ICH2_LPC_PCI_DEVNO;
INT32 pciFuncLpc = ICH2_LPC_PCI_FUNCNO;
UINT8 intPin; /* PCI INT[A-D] from PCI Int Pin Reg */
UINT8 irq; /* IRQ[0-15] of the device */
INT32 vendorId; /* PCI vendor Id */
INT32 pirq;
UINT32 index;
INT32 ix;
for (ix = 0; ix < N_PCI_SLOTS; ix++)
{
/* skip if the slot is empty */
pciConfigInLong (pciBusSlot, sysPciSlotTbl[ix], pciFuncSlot,
PCI_CFG_VENDOR_ID, &vendorId);
if ((vendorId & 0x0000ffff) == 0x0000ffff)
continue;
/* get the PCI INT[A-D] of the device */
pciConfigInByte (pciBusSlot, sysPciSlotTbl[ix], pciFuncSlot,
PCI_CFG_DEV_INT_PIN, &intPin);
/* get the PIRQ[A-H] */
pirq = sysPciIntTbl[ix][intPin - 1];
/* get the original IRQ[0-15] */
index = pirq - IOAPIC_PIRQA_INT_LVL;
irq = sysPciPirqTbl[index].irq;
if (enable)
{
/* set the PIRQ[A-H] to the PCI_CFG_DEV_INT_LINE */
pciConfigOutByte (pciBusSlot, sysPciSlotTbl[ix], pciFuncSlot,
PCI_CFG_DEV_INT_LINE, pirq);
}
else
{
/* restore the original IRQ[0-15] to PCI_CFG_DEV_INT_LINE */
pciConfigOutByte (pciBusSlot, sysPciSlotTbl[ix], pciFuncSlot,
PCI_CFG_DEV_INT_LINE, irq);
}
}
}
# endif /* INCLUDE_UNKNOWN_MOTHER */
}