static void
mainbus_attach(device_t parent, device_t self, void *aux)
{
size_t i;
mainbus_found = true;
aprint_normal("\n");
#if defined(PCI_NETBSD_CONFIGURE)
{
struct extent *ioext, *memext;
ioext = extent_create("pciio", 0x00001000, 0x00003fff,
NULL, 0, EX_NOWAIT);
memext = extent_create("pcimem", 0, BONITO_PCILO_SIZE,
NULL, 0, EX_NOWAIT);
pci_configure_bus(&gdium_configuration.gc_pc, ioext, memext,
NULL, 0, mips_dcache_align);
extent_destroy(ioext);
extent_destroy(memext);
}
#endif /* PCI_NETBSD_CONFIGURE */
for (i = 0; i < __arraycount(mainbusdevs); i++) {
struct mainbus_attach_args maa;
maa.maa_name = mainbusdevs[i];
(void) config_found(self, &maa, mainbus_print);
}
}
static void
mainbus_attach(device_t parent, device_t self, void *aux)
{
struct mainbus_attach_args ma;
const struct mainbusdev *md;
#if defined(PCI_NETBSD_ENABLE_IDE) || defined(PCI_NETBSD_CONFIGURE)
struct malta_config *mcp = &malta_configuration;
pci_chipset_tag_t pc = &mcp->mc_pc;
#endif
#if defined(PCI_NETBSD_ENABLE_IDE)
pcitag_t idetag;
pcireg_t idetim;
#endif
mainbus_found = true;
printf("\n");
#if defined(PCI_NETBSD_CONFIGURE)
struct mips_cache_info * const mci = &mips_cache_info;
struct extent *ioext = extent_create("pciio", 0x00001000, 0x0000efff,
NULL, 0, EX_NOWAIT);
struct extent *memext = extent_create("pcimem", MALTA_PCIMEM1_BASE,
MALTA_PCIMEM1_BASE + MALTA_PCIMEM1_SIZE,
NULL, 0, EX_NOWAIT);
pci_configure_bus(pc, ioext, memext, NULL, 0, mci->mci_dcache_align);
extent_destroy(ioext);
extent_destroy(memext);
#endif /* PCI_NETBSD_CONFIGURE */
#if defined(PCI_NETBSD_ENABLE_IDE)
/*
* Perhaps PMON has not enabled the IDE controller. Easy to
* fix -- just set the ENABLE bits for each channel in the
* IDETIM register. Just clear all the bits for the channel
* except for the ENABLE bits -- the `pciide' driver will
* properly configure it later.
*/
idetim = 0;
if (PCI_NETBSD_ENABLE_IDE & 0x01)
idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 0);
if (PCI_NETBSD_ENABLE_IDE & 0x02)
idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1);
/* pciide0 is pci device 10, function 1 */
idetag = pci_make_tag(pc, 0, 10, 1);
pci_conf_write(pc, idetag, PIIX_IDETIM, idetim);
#endif
for (md = mainbusdevs; md->md_name != NULL; md++) {
ma.ma_name = md->md_name;
ma.ma_addr = md->md_addr;
ma.ma_intr = md->md_intr;
(void) config_found_sm_loc(self, "mainbus", NULL, &ma,
mainbus_print, mainbus_submatch);
}
}
void
i80321_pci_init(pci_chipset_tag_t pc, void *cookie)
{
#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
struct i80321_softc *sc = cookie;
struct extent *ioext, *memext;
uint32_t busno;
#endif
pc->pc_conf_v = cookie;
pc->pc_attach_hook = i80321_pci_attach_hook;
pc->pc_bus_maxdevs = i80321_pci_bus_maxdevs;
pc->pc_make_tag = i80321_pci_make_tag;
pc->pc_decompose_tag = i80321_pci_decompose_tag;
pc->pc_conf_read = i80321_pci_conf_read;
pc->pc_conf_write = i80321_pci_conf_write;
#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
/*
* Configure the PCI bus.
*
* XXX We need to revisit this. We only configure the Secondary
* bus (and its children). The bus configure code needs changes
* to support how the busses are arranged on this chip. We also
* need to only configure devices in the private device space on
* the Secondary bus.
*/
busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR);
busno = PCIXSR_BUSNO(busno);
if (busno == 0xff)
busno = 0;
ioext = extent_create("pciio",
sc->sc_ioout_xlate + sc->sc_ioout_xlate_offset,
sc->sc_ioout_xlate + VERDE_OUT_XLATE_IO_WIN_SIZE - 1,
M_DEVBUF, NULL, 0, EX_NOWAIT);
#ifdef I80321_USE_DIRECT_WIN
memext = extent_create("pcimem", VERDE_OUT_DIRECT_WIN_BASE + VERDE_OUT_DIRECT_WIN_SKIP,
VERDE_OUT_DIRECT_WIN_BASE + VERDE_OUT_DIRECT_WIN_SIZE- 1,
M_DEVBUF, NULL, 0, EX_NOWAIT);
#else
memext = extent_create("pcimem", sc->sc_owin[0].owin_xlate_lo,
sc->sc_owin[0].owin_xlate_lo + VERDE_OUT_XLATE_MEM_WIN_SIZE - 1,
M_DEVBUF, NULL, 0, EX_NOWAIT);
#endif
aprint_normal("%s: configuring PCI bus\n", sc->sc_dev.dv_xname);
pci_configure_bus(pc, ioext, memext, NULL, busno, arm_dcache_align);
extent_destroy(ioext);
extent_destroy(memext);
#endif
}
void
becc_pci_init(pci_chipset_tag_t pc, void *cookie)
{
#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
struct becc_softc *sc = cookie;
struct extent *ioext, *memext;
#endif
pc->pc_conf_v = cookie;
pc->pc_attach_hook = becc_pci_attach_hook;
pc->pc_bus_maxdevs = becc_pci_bus_maxdevs;
pc->pc_make_tag = becc_pci_make_tag;
pc->pc_decompose_tag = becc_pci_decompose_tag;
pc->pc_conf_read = becc_pci_conf_read;
pc->pc_conf_write = becc_pci_conf_write;
pc->pc_conf_interrupt = becc_pci_conf_interrupt;
pc->pc_intr_v = cookie;
pc->pc_intr_map = becc_pci_intr_map;
pc->pc_intr_string = becc_pci_intr_string;
pc->pc_intr_evcnt = becc_pci_intr_evcnt;
pc->pc_intr_establish = becc_pci_intr_establish;
pc->pc_intr_disestablish = becc_pci_intr_disestablish;
#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
/*
* Configure the PCI bus.
*
* XXX We need to revisit this. We only configure the Secondary
* bus (and its children). The bus configure code needs changes
* to support how the busses are arranged on this chip. We also
* need to only configure devices in the private device space on
* the Secondary bus.
*/
/* Reserve the bottom 32K of the PCI address space. */
ioext = extent_create("pciio", sc->sc_ioout_xlate + (32 * 1024),
sc->sc_ioout_xlate + (64 * 1024) - 1,
NULL, 0, EX_NOWAIT);
memext = extent_create("pcimem", sc->sc_owin_xlate[0],
sc->sc_owin_xlate[0] + BECC_PCI_MEM1_SIZE - 1,
NULL, 0, EX_NOWAIT);
aprint_normal("%s: configuring PCI bus\n", device_xname(sc->sc_dev));
pci_configure_bus(pc, ioext, memext, NULL, 0, arm_dcache_align);
extent_destroy(ioext);
extent_destroy(memext);
#endif
}
static void
rmixl_pcix_init(rmixl_pcix_softc_t *sc)
{
pci_chipset_tag_t pc = &sc->sc_pci_chipset;
#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
struct extent *ioext, *memext;
#endif
pc->pc_conf_v = (void *)sc;
pc->pc_attach_hook = rmixl_pcix_attach_hook;
pc->pc_bus_maxdevs = rmixl_pcix_bus_maxdevs;
pc->pc_make_tag = rmixl_pcix_make_tag;
pc->pc_decompose_tag = rmixl_pcix_decompose_tag;
pc->pc_conf_read = rmixl_pcix_conf_read;
pc->pc_conf_write = rmixl_pcix_conf_write;
pc->pc_intr_v = (void *)sc;
pc->pc_intr_map = rmixl_pcix_intr_map;
pc->pc_intr_string = rmixl_pcix_intr_string;
pc->pc_intr_evcnt = rmixl_pcix_intr_evcnt;
pc->pc_intr_establish = rmixl_pcix_intr_establish;
pc->pc_intr_disestablish = rmixl_pcix_intr_disestablish;
pc->pc_conf_interrupt = rmixl_conf_interrupt;
#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
/*
* Configure the PCI bus.
*/
struct rmixl_config *rcp = &rmixl_configuration;
aprint_normal_dev(sc->sc_dev, "%s: configuring PCI bus\n");
ioext = extent_create("pciio",
rcp->rc_pci_io_pbase,
rcp->rc_pci_io_pbase + rcp->rc_pci_io_size - 1,
M_DEVBUF, NULL, 0, EX_NOWAIT);
memext = extent_create("pcimem",
rcp->rc_pci_mem_pbase,
rcp->rc_pci_mem_pbase + rcp->rc_pci_mem_size - 1,
M_DEVBUF, NULL, 0, EX_NOWAIT);
pci_configure_bus(pc, ioext, memext, NULL, 0,
mips_cache_info.mci_dcache_align);
extent_destroy(ioext);
extent_destroy(memext);
#endif
}
void
i80312_pci_init(pci_chipset_tag_t pc, void *cookie)
{
#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
struct i80312_softc *sc = cookie;
struct extent *ioext, *memext;
pcireg_t binfo;
int sbus;
#endif
pc->pc_conf_v = cookie;
pc->pc_attach_hook = i80312_pci_attach_hook;
pc->pc_bus_maxdevs = i80312_pci_bus_maxdevs;
pc->pc_make_tag = i80312_pci_make_tag;
pc->pc_decompose_tag = i80312_pci_decompose_tag;
pc->pc_conf_read = i80312_pci_conf_read;
pc->pc_conf_write = i80312_pci_conf_write;
pc->pc_conf_interrupt = i80312_pci_conf_interrupt;
#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
/*
* Configure the PCI bus.
*
* XXX We need to revisit this. We only configure the Secondary
* bus (and its children). The bus configure code needs changes
* to support how the busses are arranged on this chip. We also
* need to only configure devices in the private device space on
* the Secondary bus.
*/
binfo = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PPB_REG_BUSINFO);
/* pbus = PPB_BUSINFO_PRIMARY(binfo); */
sbus = PPB_BUSINFO_SECONDARY(binfo);
ioext = extent_create("pciio", sc->sc_sioout_base,
sc->sc_sioout_base + sc->sc_sioout_size - 1,
NULL, 0, EX_NOWAIT);
memext = extent_create("pcimem", sc->sc_smemout_base,
sc->sc_smemout_base + sc->sc_smemout_size - 1,
NULL, 0, EX_NOWAIT);
aprint_normal_dev(sc->sc_dev, "configuring Secondary PCI bus\n");
pci_configure_bus(pc, ioext, memext, NULL, sbus, arm_dcache_align);
extent_destroy(ioext);
extent_destroy(memext);
#endif
}
static void
necpbattach(device_t parent, device_t self, void *aux)
{
struct necpb_softc *sc = device_private(self);
struct pcibus_attach_args pba;
pci_chipset_tag_t pc;
int i;
sc->sc_dev = self;
necpbfound = 1;
aprint_normal("\n");
sc->sc_ncp = &necpb_main_context;
necpb_init(sc->sc_ncp);
pc = &sc->sc_ncp->nc_pc;
#ifdef PCI_NETBSD_CONFIGURE
pc->pc_ioext = extent_create("necpbio", 0x00100000, 0x01ffffff,
NULL, 0, EX_NOWAIT);
pc->pc_memext = extent_create("necpbmem", 0x08000000, 0x3fffffff,
NULL, 0, EX_NOWAIT);
pci_configure_bus(pc, pc->pc_ioext, pc->pc_memext, NULL, 0,
mips_cache_info.mci_dcache_align);
#endif
out32(RD94_SYS_PCI_INTMASK, 0xf);
for (i = 0; i < 4; i++)
necpb_inttbl[i] = NULL;
(*platform->set_intr)(MIPS_INT_MASK_2, necpb_intr, ARC_INTPRI_PCIISA);
pba.pba_iot = &sc->sc_ncp->nc_iot;
pba.pba_memt = &sc->sc_ncp->nc_memt;
pba.pba_dmat = &sc->sc_ncp->nc_dmat;
pba.pba_dmat64 = NULL;
pba.pba_pc = pc;
pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY;
pba.pba_bus = 0;
pba.pba_bridgetag = NULL;
config_found_ia(self, "pcibus", &pba, pcibusprint);
}
static void
shpcic_attach(device_t parent, device_t self, void *aux)
{
struct pcibus_attach_args pba;
#ifdef PCI_NETBSD_CONFIGURE
struct extent *ioext, *memext;
#endif
pcireg_t id, class;
char devinfo[256];
shpcic_found = 1;
aprint_naive("\n");
id = _reg_read_4(SH4_PCICONF0);
class = _reg_read_4(SH4_PCICONF2);
pci_devinfo(id, class, 1, devinfo, sizeof(devinfo));
aprint_normal(": %s\n", devinfo);
/* allow PCIC request */
_reg_write_4(SH4_BCR1, _reg_read_4(SH4_BCR1) | BCR1_BREQEN);
/* Initialize PCIC */
_reg_write_4(SH4_PCICR, PCICR_BASE | PCICR_RSTCTL);
delay(10 * 1000);
_reg_write_4(SH4_PCICR, PCICR_BASE);
/* Class: Host-Bridge */
_reg_write_4(SH4_PCICONF2,
PCI_CLASS_CODE(PCI_CLASS_BRIDGE, PCI_SUBCLASS_BRIDGE_HOST, 0x00));
#if !defined(DONT_INIT_PCIBSC)
#if defined(PCIBCR_BCR1_VAL)
_reg_write_4(SH4_PCIBCR1, PCIBCR_BCR1_VAL);
#else
_reg_write_4(SH4_PCIBCR1, _reg_read_4(SH4_BCR1) | BCR1_MASTER);
#endif
#if defined(PCIBCR_BCR2_VAL)
_reg_write_4(SH4_PCIBCR2, PCIBCR_BCR2_VAL);
#else
_reg_write_4(SH4_PCIBCR2, _reg_read_2(SH4_BCR2));
#endif
#if defined(SH4) && defined(SH7751R)
if (cpu_product == CPU_PRODUCT_7751R) {
#if defined(PCIBCR_BCR3_VAL)
_reg_write_4(SH4_PCIBCR3, PCIBCR_BCR3_VAL);
#else
_reg_write_4(SH4_PCIBCR3, _reg_read_2(SH4_BCR3));
#endif
}
#endif /* SH4 && SH7751R && PCIBCR_BCR3_VAL */
#if defined(PCIBCR_WCR1_VAL)
_reg_write_4(SH4_PCIWCR1, PCIBCR_WCR1_VAL);
#else
_reg_write_4(SH4_PCIWCR1, _reg_read_4(SH4_WCR1));
#endif
#if defined(PCIBCR_WCR2_VAL)
_reg_write_4(SH4_PCIWCR2, PCIBCR_WCR2_VAL);
#else
_reg_write_4(SH4_PCIWCR2, _reg_read_4(SH4_WCR2));
#endif
#if defined(PCIBCR_WCR3_VAL)
_reg_write_4(SH4_PCIWCR3, PCIBCR_WCR3_VAL);
#else
_reg_write_4(SH4_PCIWCR3, _reg_read_4(SH4_WCR3));
#endif
#if defined(PCIBCR_MCR_VAL)
_reg_write_4(SH4_PCIMCR, PCIBCR_MCR_VAL);
#else
_reg_write_4(SH4_PCIMCR, _reg_read_4(SH4_MCR));
#endif
#endif /* !DONT_INIT_PCIBSC */
/* set PCI I/O, memory base address */
_reg_write_4(SH4_PCIIOBR, SH4_PCIC_IO);
_reg_write_4(SH4_PCIMBR, SH4_PCIC_MEM);
/* set PCI local address 0 */
_reg_write_4(SH4_PCILSR0, (64 - 1) << 20);
_reg_write_4(SH4_PCILAR0, 0xac000000);
_reg_write_4(SH4_PCICONF5, 0xac000000);
/* set PCI local address 1 */
_reg_write_4(SH4_PCILSR1, (64 - 1) << 20);
_reg_write_4(SH4_PCILAR1, 0xac000000);
_reg_write_4(SH4_PCICONF6, 0x8c000000);
/* Enable I/O, memory, bus-master */
_reg_write_4(SH4_PCICONF1, PCI_COMMAND_IO_ENABLE
| PCI_COMMAND_MEM_ENABLE
| PCI_COMMAND_MASTER_ENABLE
| PCI_COMMAND_STEPPING_ENABLE
| PCI_STATUS_DEVSEL_MEDIUM);
/* Initialize done. */
_reg_write_4(SH4_PCICR, PCICR_BASE | PCICR_CFINIT);
/* set PCI controller interrupt priority */
intpri_intr_priority(SH4_INTEVT_PCIERR, shpcic_intr_priority[0]);
intpri_intr_priority(SH4_INTEVT_PCISERR, shpcic_intr_priority[1]);
/* PCI bus */
#ifdef PCI_NETBSD_CONFIGURE
ioext = extent_create("pciio",
SH4_PCIC_IO, SH4_PCIC_IO + SH4_PCIC_IO_SIZE - 1,
M_DEVBUF, NULL, 0, EX_NOWAIT);
memext = extent_create("pcimem",
SH4_PCIC_MEM, SH4_PCIC_MEM + SH4_PCIC_MEM_SIZE - 1,
M_DEVBUF, NULL, 0, EX_NOWAIT);
pci_configure_bus(NULL, ioext, memext, NULL, 0, sh_cache_line_size);
extent_destroy(ioext);
extent_destroy(memext);
#endif
/* PCI bus */
memset(&pba, 0, sizeof(pba));
pba.pba_iot = shpcic_get_bus_io_tag();
pba.pba_memt = shpcic_get_bus_mem_tag();
pba.pba_dmat = shpcic_get_bus_dma_tag();
pba.pba_dmat64 = NULL;
pba.pba_pc = NULL;
pba.pba_bus = 0;
pba.pba_bridgetag = NULL;
pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED;
config_found(self, &pba, NULL);
}
static void
giopci_attach(struct device *parent, struct device *self, void *aux)
{
struct giopci_softc *sc = (void *)self;
pci_chipset_tag_t pc = &sc->sc_pc;
struct gio_attach_args *ga = aux;
uint32_t pci_off, pci_len, arb;
struct pcibus_attach_args pba;
u_long m_start, m_end;
#ifdef PCI_NETBSD_CONFIGURE
extern int pci_conf_debug;
pci_conf_debug = giopci_debug;
#endif
sc->sc_iot = ga->ga_iot;
sc->sc_slot = ga->ga_slot;
sc->sc_gprid = GIO_PRODUCT_PRODUCTID(ga->ga_product);
if (mach_type == MACH_SGI_IP22 &&
mach_subtype == MACH_SGI_IP22_FULLHOUSE)
arb = GIO_ARB_RT | GIO_ARB_MST | GIO_ARB_PIPE;
else
arb = GIO_ARB_RT | GIO_ARB_MST;
if (gio_arb_config(ga->ga_slot, arb)) {
printf(": failed to configure GIO bus arbiter\n");
return;
}
#if (NIMC > 0)
imc_disable_sysad_parity();
#endif
switch (sc->sc_gprid) {
case PHOBOS_G100:
case PHOBOS_G130:
case PHOBOS_G160:
pci_off = PHOBOS_PCI_OFFSET;
pci_len = PHOBOS_PCI_LENGTH;
m_start = MIPS_KSEG1_TO_PHYS(ga->ga_addr + PHOBOS_TULIP_START);
m_end = MIPS_KSEG1_TO_PHYS(ga->ga_addr + PHOBOS_TULIP_END);
break;
case SETENG_GFE:
/*
* NB: The SetEng board does not allow the ThunderLAN's DMA
* engine to properly transfer segments that span page
* boundaries. See sgimips/autoconf.c where we catch a
* tl(4) device attachment and create an appropriate
* proplib entry to enable the workaround.
*/
pci_off = SETENG_PCI_OFFSET;
pci_len = SETENG_PCI_LENGTH;
m_start = MIPS_KSEG1_TO_PHYS(ga->ga_addr + SETENG_TLAN_START);
m_end = MIPS_KSEG1_TO_PHYS(ga->ga_addr + SETENG_TLAN_END);
bus_space_write_4(ga->ga_iot, ga->ga_ioh,
SETENG_MAGIC_OFFSET, SETENG_MAGIC_VALUE);
break;
default:
panic("giopci_attach: unsupported GIO product id 0x%02x",
sc->sc_gprid);
}
if (bus_space_subregion(ga->ga_iot, ga->ga_ioh, pci_off, pci_len,
&sc->sc_ioh)) {
printf("%s: unable to map PCI registers\n",sc->sc_dev.dv_xname);
return;
}
sc->sc_pci_len = pci_len;
pc->pc_bus_maxdevs = giopci_bus_maxdevs;
pc->pc_conf_read = giopci_conf_read;
pc->pc_conf_write = giopci_conf_write;
pc->pc_conf_hook = giopci_conf_hook;
pc->pc_intr_map = giopci_intr_map;
pc->pc_intr_string = giopci_intr_string;
pc->intr_establish = giopci_intr_establish;
pc->intr_disestablish = giopci_intr_disestablish;
pc->iot = ga->ga_iot;
pc->ioh = ga->ga_ioh;
pc->cookie = sc;
printf(": %s\n", gio_product_string(sc->sc_gprid));
#ifdef PCI_NETBSD_CONFIGURE
pc->pc_memext = extent_create("giopcimem", m_start, m_end,
M_DEVBUF, NULL, 0, EX_NOWAIT);
pci_configure_bus(pc, NULL, pc->pc_memext, NULL, 0, mips_dcache_align);
#endif
memset(&pba, 0, sizeof(pba));
pba.pba_memt = SGIMIPS_BUS_SPACE_MEM;
pba.pba_dmat = ga->ga_dmat;
pba.pba_pc = pc;
pba.pba_flags = PCI_FLAGS_MEM_ENABLED;
/* NB: do not set PCI_FLAGS_{MRL,MRM,MWI}_OKAY -- true ?! */
config_found_ia(self, "pcibus", &pba, pcibusprint);
}
/*
* Attach the mainbus.
*/
void
mainbus_attach(device_t parent, device_t self, void *aux)
{
struct pcibus_attach_args pba;
#if NPCI > 0
struct genppc_pci_chipset_businfo *pbi;
#endif
#ifdef PCI_NETBSD_CONFIGURE
struct extent *ioext, *memext;
#endif
mainbus_found = 1;
aprint_normal("\n");
/* attach cpu */
config_found_ia(self, "mainbus", NULL, mainbus_print);
/*
* XXX Note also that the presence of a PCI bus should
* XXX _always_ be checked, and if present the bus should be
* XXX 'found'. However, because of the structure of the code,
* XXX that's not currently possible.
*/
#if NPCI > 0
genppc_pct = malloc(sizeof(struct genppc_pci_chipset), M_DEVBUF,
M_NOWAIT);
KASSERT(genppc_pct != NULL);
mvmeppc_pci_get_chipset_tag(genppc_pct);
pbi = malloc(sizeof(struct genppc_pci_chipset_businfo),
M_DEVBUF, M_NOWAIT);
KASSERT(pbi != NULL);
pbi->pbi_properties = prop_dictionary_create();
KASSERT(pbi->pbi_properties != NULL);
SIMPLEQ_INIT(&genppc_pct->pc_pbi);
SIMPLEQ_INSERT_TAIL(&genppc_pct->pc_pbi, pbi, next);
#ifdef PCI_NETBSD_CONFIGURE
ioext = extent_create("pciio", 0x00008000, 0x0000ffff,
NULL, 0, EX_NOWAIT);
memext = extent_create("pcimem", 0x00000000, 0x0fffffff,
NULL, 0, EX_NOWAIT);
pci_configure_bus(genppc_pct, ioext, memext, NULL, 0, CACHELINESIZE);
extent_destroy(ioext);
extent_destroy(memext);
#endif
pba.pba_iot = &prep_io_space_tag;
pba.pba_memt = &prep_mem_space_tag;
pba.pba_dmat = &pci_bus_dma_tag;
pba.pba_dmat64 = NULL;
pba.pba_pc = genppc_pct;
pba.pba_bus = 0;
pba.pba_bridgetag = NULL;
pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY;
config_found_ia(self, "pcibus", &pba, pcibusprint);
#endif
}
static void
mppb_attach(device_t parent, device_t self, void *aux)
{
struct mppb_softc *sc;
struct pcibus_attach_args pba;
struct zbus_args *zap;
pci_chipset_tag_t pc;
#ifdef PCI_NETBSD_CONFIGURE
struct extent *ioext, *memext;
#endif /* PCI_NETBSD_CONFIGURE */
zap = aux;
sc = device_private(self);
pc = &sc->apc;
sc->sc_dev = self;
sc->ba = zap->va;
aprint_normal(": Matay Prometheus PCI bridge\n");
/* Setup bus space mappings. */
sc->pci_conf_area.base = (bus_addr_t) sc->ba + MPPB_CONF_BASE;
sc->pci_conf_area.absm = &amiga_bus_stride_1swap;
sc->pci_mem_area.base = (bus_addr_t) sc->ba + MPPB_MEM_BASE;
sc->pci_mem_area.absm = &amiga_bus_stride_1;
sc->pci_io_area.base = (bus_addr_t) sc->ba + MPPB_IO_BASE;
sc->pci_io_area.absm = &amiga_bus_stride_1;
#ifdef MPPB_DEBUG
aprint_normal("mppb mapped conf %x->%x, mem %x->%x\n, io %x->%x\n",
kvtop((void*) sc->pci_conf_area.base), sc->pci_conf_area.base,
kvtop((void*) sc->pci_mem_area.base), sc->pci_mem_area.base,
kvtop((void*) sc->pci_io_area.base), sc->pci_io_area.base);
#endif
sc->apc.pci_conf_datat = &(sc->pci_conf_area);
if (bus_space_map(sc->apc.pci_conf_datat, 0, MPPB_CONF_SIZE, 0,
&sc->apc.pci_conf_datah))
aprint_error_dev(self,
"couldn't map PCI configuration data space\n");
/* Initialize the PCI chipset tag. */
sc->apc.pc_conf_v = (void*) pc;
sc->apc.pc_bus_maxdevs = mppb_pci_bus_maxdevs;
sc->apc.pc_make_tag = amiga_pci_make_tag;
sc->apc.pc_decompose_tag = amiga_pci_decompose_tag;
sc->apc.pc_conf_read = mppb_pci_conf_read;
sc->apc.pc_conf_write = mppb_pci_conf_write;
sc->apc.pc_attach_hook = mppb_pci_attach_hook;
sc->apc.pc_intr_map = mppb_pci_intr_map;
sc->apc.pc_intr_string = amiga_pci_intr_string;
sc->apc.pc_intr_establish = amiga_pci_intr_establish;
sc->apc.pc_intr_disestablish = amiga_pci_intr_disestablish;
sc->apc.pc_conf_hook = amiga_pci_conf_hook;
sc->apc.pc_conf_interrupt = amiga_pci_conf_interrupt;
#ifdef PCI_NETBSD_CONFIGURE
ioext = extent_create("mppbio", MPPB_IO_BASE,
MPPB_IO_BASE + MPPB_IO_SIZE, NULL, 0, EX_NOWAIT);
memext = extent_create("mppbmem", MPPB_MEM_BASE,
MPPB_MEM_BASE + MPPB_MEM_SIZE, NULL, 0, EX_NOWAIT);
#ifdef MPPB_DEBUG
aprint_normal("mppb: reconfiguring the bus!\n");
#endif /* MPPB_DEBUG */
pci_configure_bus(pc, ioext, memext, NULL, 0, CACHELINE_SIZE);
extent_destroy(ioext);
extent_destroy(memext);
#endif /* PCI_NETBSD_CONFIGURE */
pba.pba_iot = &(sc->pci_io_area);
pba.pba_memt = &(sc->pci_mem_area);
pba.pba_dmat = NULL;
pba.pba_dmat64 = NULL;
pba.pba_pc = pc;
pba.pba_flags = PCI_FLAGS_MEM_OKAY | PCI_FLAGS_IO_OKAY;
pba.pba_bus = 0;
pba.pba_bridgetag = NULL;
config_found_ia(self, "pcibus", &pba, pcibusprint);
}
/*
* Attach the mainbus.
*/
void
mainbus_attach(device_t parent, device_t self, void *aux)
{
union mainbus_attach_args mba;
struct confargs ca;
#if NPCI > 0
struct genppc_pci_chipset_businfo *pbi;
#ifdef PCI_NETBSD_CONFIGURE
struct extent *ioext, *memext;
#endif
#endif
mainbus_found = 1;
aprint_normal("\n");
#if defined(RESIDUAL_DATA_DUMP)
print_residual_device_info();
#endif
/*
* Always find the CPU
*/
ca.ca_name = "cpu";
ca.ca_node = 0;
config_found_ia(self, "mainbus", &ca, mainbus_print);
ca.ca_name = "cpu";
ca.ca_node = 1;
config_found_ia(self, "mainbus", &ca, mainbus_print);
/*
* XXX Note also that the presence of a PCI bus should
* XXX _always_ be checked, and if present the bus should be
* XXX 'found'. However, because of the structure of the code,
* XXX that's not currently possible.
*/
#if NPCI > 0
genppc_pct = malloc(sizeof(struct genppc_pci_chipset), M_DEVBUF,
M_NOWAIT);
KASSERT(genppc_pct != NULL);
bebox_pci_get_chipset_tag(genppc_pct);
pbi = malloc(sizeof(struct genppc_pci_chipset_businfo),
M_DEVBUF, M_NOWAIT);
KASSERT(pbi != NULL);
pbi->pbi_properties = prop_dictionary_create();
KASSERT(pbi->pbi_properties != NULL);
SIMPLEQ_INIT(&genppc_pct->pc_pbi);
SIMPLEQ_INSERT_TAIL(&genppc_pct->pc_pbi, pbi, next);
#ifdef PCI_NETBSD_CONFIGURE
ioext = extent_create("pciio", 0x00008000, 0x0000ffff,
NULL, 0, EX_NOWAIT);
memext = extent_create("pcimem", 0x00000000, 0x0fffffff,
NULL, 0, EX_NOWAIT);
pci_configure_bus(genppc_pct, ioext, memext, NULL, 0, CACHELINESIZE);
extent_destroy(ioext);
extent_destroy(memext);
#endif /* PCI_NETBSD_CONFIGURE */
#endif /* NPCI */
#if NPCI > 0
memset(&mba, 0, sizeof(mba));
mba.mba_pba.pba_iot = &prep_io_space_tag;
mba.mba_pba.pba_memt = &prep_mem_space_tag;
mba.mba_pba.pba_dmat = &pci_bus_dma_tag;
mba.mba_pba.pba_dmat64 = NULL;
mba.mba_pba.pba_pc = genppc_pct;
mba.mba_pba.pba_bus = 0;
mba.mba_pba.pba_bridgetag = NULL;
mba.mba_pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY;
config_found_ia(self, "pcibus", &mba.mba_pba, pcibusprint);
#endif /* NPCI */
#ifdef RESIDUAL_DATA_DUMP
SIMPLEQ_FOREACH(pbi, &genppc_pct->pc_pbi, next)
printf("%s\n", prop_dictionary_externalize(pbi->pbi_properties));
#endif
}
void
aupciattach(device_t parent, device_t self, void *aux)
{
struct aupci_softc *sc = device_private(self);
struct aubus_attach_args *aa = (struct aubus_attach_args *)aux;
uint32_t cfg;
#if NPCI > 0
uint32_t mbar, mask;
bus_addr_t mstart;
struct pcibus_attach_args pba;
#endif
aupci_found = 1;
sc->sc_dev = self;
sc->sc_bust = aa->aa_st;
if (bus_space_map(sc->sc_bust, aa->aa_addrs[0], 512, 0,
&sc->sc_bush) != 0) {
aprint_error(": unable to map PCI registers\n");
return;
}
#if NPCI > 0
/*
* These physical addresses are locked in on the CPUs we have
* seen. Perhaps these should be passed in via locators, thru
* the configuration file.
*/
sc->sc_cfgbase = PCI_CONFIG_BASE;
sc->sc_membase = PCI_MEM_BASE;
sc->sc_iobase = PCI_IO_BASE;
#endif
/*
* Configure byte swapping, as YAMON doesn't do it. YAMON does take
* care of most of the rest of the details (clocking, etc.), however.
*/
#if _BYTE_ORDER == _BIG_ENDIAN
/*
* N.B.: This still doesn't do the DMA thing properly. I have
* not yet figured out how to get DMA access to work properly
* without having bytes swapped while the processor is in
* big-endian mode. I'm not even sure that the Alchemy part
* can do it without swapping the bytes (which would be a
* bummer, since then only parts which had hardware detection
* and swapping support would work without special hacks in
* their drivers.)
*/
cfg = AUPCI_CONFIG_CH | AUPCI_CONFIG_R1H |
AUPCI_CONFIG_R2H | AUPCI_CONFIG_AEN |
AUPCI_CONFIG_SM | AUPCI_CONFIG_ST | AUPCI_CONFIG_SIC_DATA;
#else
cfg = AUPCI_CONFIG_CH | AUPCI_CONFIG_R1H |
AUPCI_CONFIG_R2H | AUPCI_CONFIG_AEN;
#endif
bus_space_write_4(sc->sc_bust, sc->sc_bush, AUPCI_CONFIG, cfg);
cfg = bus_space_read_4(sc->sc_bust, sc->sc_bush, AUPCI_COMMAND_STATUS);
aprint_normal(": Alchemy Host-PCI Bridge, %sMHz\n",
(cfg & PCI_STATUS_66MHZ_SUPPORT) ? "66" : "33");
aprint_naive("\n");
#if NPCI > 0
/*
* PCI configuration space. Address in this bus are
* orthogonal to other spaces. We need to make the entire
* 32-bit address space available.
*/
sc->sc_cfgt = &sc->sc_cfg_space;
au_himem_space_init(sc->sc_cfgt, "pcicfg", sc->sc_cfgbase,
0x00000000, 0xffffffff, AU_HIMEM_SPACE_IO);
/*
* Virtual PCI memory. Configured so that we don't overlap
* with PCI memory space.
*/
mask = bus_space_read_4(sc->sc_bust, sc->sc_bush, AUPCI_MWMASK);
mask >>= AUPCI_MWMASK_SHIFT;
mask <<= AUPCI_MWMASK_SHIFT;
mbar = bus_space_read_4(sc->sc_bust, sc->sc_bush, AUPCI_MBAR);
mstart = (mbar & mask) + (~mask + 1);
sc->sc_memt = &sc->sc_mem_space;
au_himem_space_init(sc->sc_memt, "pcimem", sc->sc_membase,
mstart, 0xffffffff, AU_HIMEM_SPACE_LITTLE_ENDIAN);
/*
* IO space. Address in this bus are orthogonal to other spaces.
* 16 MB should be plenty. We don't start from zero to avoid
* potential device bugs.
*/
sc->sc_iot = &sc->sc_io_space;
au_himem_space_init(sc->sc_iot, "pciio",
sc->sc_iobase, AUPCI_IO_START, AUPCI_IO_END,
AU_HIMEM_SPACE_LITTLE_ENDIAN | AU_HIMEM_SPACE_IO);
sc->sc_pc.pc_conf_v = sc;
sc->sc_pc.pc_attach_hook = aupci_attach_hook;
sc->sc_pc.pc_bus_maxdevs = aupci_bus_maxdevs;
sc->sc_pc.pc_make_tag = aupci_make_tag;
sc->sc_pc.pc_decompose_tag = aupci_decompose_tag;
sc->sc_pc.pc_conf_read = aupci_conf_read;
sc->sc_pc.pc_conf_write = aupci_conf_write;
sc->sc_pc.pc_intr_v = sc;
sc->sc_pc.pc_intr_map = aupci_intr_map;
sc->sc_pc.pc_intr_string = aupci_intr_string;
sc->sc_pc.pc_intr_establish = aupci_intr_establish;
sc->sc_pc.pc_intr_disestablish = aupci_intr_disestablish;
sc->sc_pc.pc_conf_interrupt = aupci_conf_interrupt;
#ifdef PCI_NETBSD_CONFIGURE
mem_ex = extent_create("pcimem", mstart, 0xffffffff,
NULL, 0, EX_WAITOK);
io_ex = extent_create("pciio", AUPCI_IO_START, AUPCI_IO_END,
NULL, 0, EX_WAITOK);
pci_configure_bus(&sc->sc_pc,
io_ex, mem_ex, NULL, 0, mips_cache_info.mci_dcache_align);
extent_destroy(mem_ex);
extent_destroy(io_ex);
#endif
pba.pba_iot = sc->sc_iot;
pba.pba_memt = sc->sc_memt;
/* XXX: review dma tag logic */
pba.pba_dmat = aa->aa_dt;
pba.pba_dmat64 = NULL;
pba.pba_pc = &sc->sc_pc;
pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY;
pba.pba_bus = 0;
pba.pba_bridgetag = NULL;
config_found_ia(self, "pcibus", &pba, pcibusprint);
#endif /* NPCI > 0 */
}
static void
ofwpci_attach(device_t parent, device_t self, void *aux)
{
struct ofwpci_softc *sc = device_private(self);
pci_chipset_tag_t pc = &sc->sc_pc;
struct confargs *ca = aux;
struct pcibus_attach_args pba;
struct genppc_pci_chipset_businfo *pbi;
int node = ca->ca_node;
int i, isprim = 0;
uint32_t busrange[2];
char buf[64];
#ifdef PCI_NETBSD_CONFIGURE
struct extent *ioext, *memext;
#endif
aprint_normal("\n");
sc->sc_dev = self;
/* PCI bus number */
if (OF_getprop(node, "bus-range", busrange, sizeof(busrange)) != 8)
return;
/* bus space map the io ranges */
sc->sc_iot.pbs_flags = _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_IO_TYPE;
sc->sc_iot.pbs_base = 0x00000000;
if (ofwoea_map_space(RANGE_TYPE_PCI, RANGE_IO, node, &sc->sc_iot,
"ofwpci io-space") != 0)
panic("Can't init ofwpci io tag");
sc->sc_memt.pbs_flags = _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE;
sc->sc_memt.pbs_base = 0x00000000;
if (ofwoea_map_space(RANGE_TYPE_PCI, RANGE_MEM, node, &sc->sc_memt,
"ofwpci mem-space") != 0)
panic("Can't init ofwpci mem tag");
aprint_debug("io base=0x%"PRIxPTR" offset=0x%"PRIxPTR" limit=0x%"PRIxPTR"\n",
sc->sc_iot.pbs_base, sc->sc_iot.pbs_offset, sc->sc_iot.pbs_limit);
aprint_debug("mem base=0x%"PRIxPTR" offset=0x%"PRIxPTR" limit=0x%"PRIxPTR"\n",
sc->sc_memt.pbs_base, sc->sc_memt.pbs_offset,
sc->sc_memt.pbs_limit);
/* are we the primary pci bus? */
if (of_find_firstchild_byname(OF_finddevice("/"), "pci") == node) {
int isa_node;
isprim++;
/* yes we are, now do we have an ISA child? */
isa_node = of_find_firstchild_byname(node, "isa");
if (isa_node != -1) {
/* isa == pci */
genppc_isa_io_space_tag = sc->sc_iot;
genppc_isa_mem_space_tag = sc->sc_memt;
map_isa_ioregs();
init_ofppc_interrupt();
ofppc_init_comcons(isa_node);
}
}
ofwpci_get_chipset_tag(pc);
pc->pc_node = node;
i = OF_package_to_path(node, buf, sizeof(buf)-5);
if (i <= 0)
panic("Can't determine path for pci node %d", node);
buf[i] = '\0';
pc->pc_ihandle = OF_open(buf);
if (pc->pc_ihandle < 0)
panic("Can't open device %s", buf);
pc->pc_bus = busrange[0];
pc->pc_iot = &sc->sc_iot;
pc->pc_memt = &sc->sc_memt;
pbi = malloc(sizeof(struct genppc_pci_chipset_businfo),
M_DEVBUF, M_NOWAIT);
KASSERT(pbi != NULL);
pbi->pbi_properties = prop_dictionary_create();
KASSERT(pbi->pbi_properties != NULL);
SIMPLEQ_INIT(&pc->pc_pbi);
SIMPLEQ_INSERT_TAIL(&pc->pc_pbi, pbi, next);
genofw_setup_pciintr_map((void *)pc, pbi, pc->pc_node);
#ifdef PCI_NETBSD_CONFIGURE
ioext = extent_create("pciio",
modeldata.pciiodata[device_unit(self)].start,
modeldata.pciiodata[device_unit(self)].limit,
NULL, 0, EX_NOWAIT);
memext = extent_create("pcimem", sc->sc_memt.pbs_base,
sc->sc_memt.pbs_limit-1, NULL, 0, EX_NOWAIT);
if (pci_configure_bus(pc, ioext, memext, NULL, 0, CACHELINESIZE))
aprint_error("pci_configure_bus() failed\n");
extent_destroy(ioext);
extent_destroy(memext);
#endif /* PCI_NETBSD_CONFIGURE */
memset(&pba, 0, sizeof(pba));
pba.pba_memt = pc->pc_memt;
pba.pba_iot = pc->pc_iot;
pba.pba_dmat = &pci_bus_dma_tag;
pba.pba_dmat64 = NULL;
pba.pba_bus = pc->pc_bus;
pba.pba_bridgetag = NULL;
pba.pba_pc = pc;
pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY;
config_found_ia(self, "pcibus", &pba, pcibusprint);
}
static void
pchbattach(device_t parent, device_t self, void *aux)
{
struct plb_attach_args *paa = aux;
struct pcibus_attach_args pba;
char devinfo[256];
#ifdef PCI_NETBSD_CONFIGURE
struct extent *ioext, *memext;
#ifdef PCI_CONFIGURE_VERBOSE
extern int pci_conf_debug;
pci_conf_debug = 1;
#endif
#endif
pci_chipset_tag_t pc = 0;
pcitag_t tag;
int class, id;
pci_machdep_init();
tag = pci_make_tag(pc, 0, 0, 0);
class = pci_conf_read(pc, tag, PCI_CLASS_REG);
id = pci_conf_read(pc, tag, PCI_ID_REG);
aprint_normal("\n");
pcifound = true;
/*
* All we do is print out a description. Eventually, we
* might want to add code that does something that's
* possibly chipset-specific.
*/
pci_devinfo(id, class, 0, devinfo, sizeof(devinfo));
aprprint_normal_dev(self, "%s (rev. 0x%02x)\n", devinfo,
PCI_REVISION(class));
pci_machdep_init(); /* Redundant... */
ibm4xx_setup_pci();
#ifdef PCI_CONFIGURE_VERBOSE
ibm4xx_show_pci_map();
#endif
if (bus_space_init(&pchb_io_tag, "pchbio", NULL, 0))
panic("pchbattach: can't init IO tag");
if (bus_space_init(&pchb_mem_tag, "pchbmem", NULL, 0))
panic("pchbattach: can't init MEM tag");
#ifdef PCI_NETBSD_CONFIGURE
memext = extent_create("pcimem", MIN_PCI_MEMADDR_NOPREFETCH,
MIN_PCI_MEMADDR_NOPREFETCH + 0x1fffffff, M_DEVBUF, NULL, 0,
EX_NOWAIT);
ioext = extent_create("pciio", MIN_PCI_PCI_IOADDR,
MIN_PCI_PCI_IOADDR + 0xffff, M_DEVBUF, NULL, 0, EX_NOWAIT);
pci_configure_bus(0, ioext, memext, NULL, 0, 32);
extent_destroy(memext);
extent_destroy(ioext);
#endif /* PCI_NETBSD_CONFIGURE */
#ifdef PCI_CONFIGURE_VERBOSE
printf("running config_found PCI\n");
#endif
/* IO window located @ e8000000 and maps to 0-0xffff */
pba.pba_iot = &pchb_io_tag;
/* PCI memory window is directly mapped */
pba.pba_memt = &pchb_mem_tag;
pba.pba_dmat = paa->plb_dmat;
pba.pba_dmat64 = NULL;
pba.pba_bus = 0;
pba.pba_bridgetag = NULL;
pba.pba_flags = PCI_FLAGS_MEM_OKAY | PCI_FLAGS_IO_OKAY;
config_found_ia(self, "pcibus", &pba, pchbprint);
}
static void
macepci_attach(device_t parent, device_t self, void *aux)
{
struct macepci_softc *sc = device_private(self);
pci_chipset_tag_t pc = &sc->sc_pc;
struct mace_attach_args *maa = aux;
struct pcibus_attach_args pba;
u_int32_t control;
int rev;
if (bus_space_subregion(maa->maa_st, maa->maa_sh,
maa->maa_offset, 0, &pc->ioh) )
panic("macepci_attach: couldn't map");
pc->iot = maa->maa_st;
rev = bus_space_read_4(pc->iot, pc->ioh, MACEPCI_REVISION);
printf(": rev %d\n", rev);
pc->pc_bus_maxdevs = macepci_bus_maxdevs;
pc->pc_conf_read = macepci_conf_read;
pc->pc_conf_write = macepci_conf_write;
pc->pc_intr_map = macepci_intr_map;
pc->pc_intr_string = macepci_intr_string;
pc->intr_establish = mace_intr_establish;
pc->intr_disestablish = mace_intr_disestablish;
bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_ERROR_ADDR, 0);
bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_ERROR_FLAGS, 0);
/* Turn on PCI error interrupts */
bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONTROL,
MACE_PCI_CONTROL_SERR_ENA |
MACE_PCI_CONTROL_PARITY_ERR |
MACE_PCI_CONTROL_PARK_LIU |
MACE_PCI_CONTROL_OVERRUN_INT |
MACE_PCI_CONTROL_PARITY_INT |
MACE_PCI_CONTROL_SERR_INT |
MACE_PCI_CONTROL_IT_INT |
MACE_PCI_CONTROL_RE_INT |
MACE_PCI_CONTROL_DPED_INT |
MACE_PCI_CONTROL_TAR_INT |
MACE_PCI_CONTROL_MAR_INT);
/*
* Enable all MACE PCI interrupts. They will be masked by
* the CRIME code.
*/
control = bus_space_read_4(pc->iot, pc->ioh, MACEPCI_CONTROL);
control |= CONTROL_INT_MASK;
bus_space_write_4(pc->iot, pc->ioh, MACEPCI_CONTROL, control);
#if NPCI > 0
pc->pc_ioext = extent_create("macepciio", 0x00001000, 0x01ffffff,
NULL, 0, EX_NOWAIT);
pc->pc_memext = extent_create("macepcimem", 0x80100000, 0x81ffffff,
NULL, 0, EX_NOWAIT);
pci_configure_bus(pc, pc->pc_ioext, pc->pc_memext, NULL, 0,
mips_cache_info.mci_dcache_align);
memset(&pba, 0, sizeof pba);
/*XXX*/ pba.pba_iot = SGIMIPS_BUS_SPACE_IO;
/*XXX*/ pba.pba_memt = SGIMIPS_BUS_SPACE_MEM;
pba.pba_dmat = &pci_bus_dma_tag;
pba.pba_dmat64 = NULL;
pba.pba_bus = 0;
pba.pba_bridgetag = NULL;
pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY |
PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY;
pba.pba_pc = pc;
#ifdef MACEPCI_IO_WAS_BUGGY
if (rev == 0)
pba.pba_flags &= ~PCI_FLAGS_IO_OKAY; /* Buggy? */
#endif
cpu_intr_establish(maa->maa_intr, IPL_NONE, macepci_intr, sc);
config_found_ia(self, "pcibus", &pba, pcibusprint);
#endif
}
static void
empb_callback(device_t self) {
struct empb_softc *sc;
pci_chipset_tag_t pc;
struct pcibus_attach_args pba;
#ifdef PCI_NETBSD_CONFIGURE
struct extent *ioext, *memext;
#endif /* PCI_NETBSD_CONFIGURE */
sc = device_private(self);
pc = &sc->apc;
#ifdef EMPB_DEBUG
aprint_normal("empb: mapped setup %x->%x, conf/io %x->%x\n",
kvtop((void*) sc->setup_area.base), sc->setup_area.base,
kvtop((void*) sc->pci_confio_area.base), sc->pci_confio_area.base);
#endif
sc->pci_confio_t = &(sc->pci_confio_area);
/*
* We should not map I/O space here, however we have no choice
* since these addresses are shared between configuration space and
* I/O space. Not really a problem on m68k, however on PPC...
*/
if (bus_space_map(sc->pci_confio_t, 0, EMPB_BRIDGE_SIZE, 0,
&sc->pci_confio_h))
aprint_error_dev(self,
"couldn't map PCI configuration & I/O space\n");
sc->apc.pci_conf_datat = sc->pci_confio_t;
sc->apc.pci_conf_datah = sc->pci_confio_h;
sc->setup_area_t = &(sc->setup_area);
if (bus_space_map(sc->setup_area_t, 0, EMPB_SETUP_SIZE, 0,
&sc->setup_area_h))
aprint_error_dev(self,
"couldn't map Mediator setup space\n");
empb_find_mem(sc);
if (sc->pci_mem_win_size == 0)
aprint_error_dev(self,
"couldn't find memory space, check your WINDOW jumper\n");
/* Initialize the PCI chipset tag. */
sc->apc.pc_conf_v = (void*) pc;
sc->apc.pc_bus_maxdevs = empb_pci_bus_maxdevs;
sc->apc.pc_make_tag = amiga_pci_make_tag;
sc->apc.pc_decompose_tag = amiga_pci_decompose_tag;
sc->apc.pc_conf_read = empb_pci_conf_read;
sc->apc.pc_conf_write = empb_pci_conf_write;
sc->apc.pc_attach_hook = empb_pci_attach_hook;
sc->apc.pc_intr_map = empb_pci_intr_map;
sc->apc.pc_intr_string = amiga_pci_intr_string;
sc->apc.pc_intr_establish = amiga_pci_intr_establish;
sc->apc.pc_intr_disestablish = amiga_pci_intr_disestablish;
sc->apc.pc_conf_hook = empb_pci_conf_hook;
sc->apc.pc_conf_interrupt = amiga_pci_conf_interrupt;
sc->apc.cookie = sc;
#ifdef PCI_NETBSD_CONFIGURE
ioext = extent_create("empbio", 0, EMPB_BRIDGE_SIZE,
NULL, 0, EX_NOWAIT);
memext = extent_create("empbmem", EMPB_MEM_BASE, EMPB_MEM_END,
NULL, 0, EX_NOWAIT);
pci_configure_bus(pc, ioext, memext, NULL, 0, CACHELINE_SIZE);
extent_destroy(ioext);
extent_destroy(memext);
#endif /* PCI_NETBSD_CONFIGURE */
pba.pba_iot = &(sc->pci_confio_area);
pba.pba_dmat = NULL;
pba.pba_dmat64 = NULL;
pba.pba_pc = pc;
pba.pba_flags = PCI_FLAGS_IO_OKAY;
if(sc->pci_mem_win_size > 0) {
pba.pba_memt = &(sc->pci_mem_win);
pba.pba_flags |= PCI_FLAGS_MEM_OKAY;
} else
pba.pba_memt = NULL;
pba.pba_bus = 0;
pba.pba_bridgetag = NULL;
/* Attach power management on SX and TX models. */
switch (sc->model) {
case ZORRO_PRODID_MED1K2SX:
case ZORRO_PRODID_MED1K2TX:
empb_empm_attach(sc);
default:
break;
}
empb_intr_enable(sc);
config_found_ia(self, "pcibus", &pba, pcibusprint);
}
