static int ide_system_bus_speed(void)
{
#ifdef CONFIG_PCI
static struct pci_device_id pci_default[] = {
{ PCI_DEVICE(PCI_ANY_ID, PCI_ANY_ID) },
{ }
};
#else
#define pci_default 0
#endif /* CONFIG_PCI */
if (!system_bus_speed) {
if (idebus_parameter) {
/* user supplied value */
system_bus_speed = idebus_parameter;
} else if (pci_dev_present(pci_default)) {
/* safe default value for PCI */
system_bus_speed = 33;
} else {
/* safe default value for VESA and PCI */
system_bus_speed = 50;
}
printk(KERN_INFO "ide: Assuming %dMHz system bus speed "
"for PIO modes%s\n", system_bus_speed,
idebus_parameter ? "" : "; override with idebus=xx");
}
return system_bus_speed;
}
static int __init cs5535_gpio_init(void)
{
dev_t dev_id;
u32 low, hi;
int retval;
if (pci_dev_present(divil_pci) == 0) {
printk(KERN_WARNING NAME ": DIVIL not found\n");
return -ENODEV;
}
rdmsr(MSR_LBAR_GPIO, low, hi);
if (hi != 0x0000f001) {
printk(KERN_WARNING NAME ": GPIO not enabled\n");
return -ENODEV;
}
gpio_base = low & 0x0000ff00;
if (mask != 0)
mask &= 0x1f7fffff;
else
mask = 0x0b003c66;
if (!request_region(gpio_base, CS5535_GPIO_SIZE, NAME)) {
printk(KERN_ERR NAME ": can't allocate I/O for GPIO\n");
return -ENODEV;
}
if (major) {
dev_id = MKDEV(major, 0);
retval = register_chrdev_region(dev_id, CS5535_GPIO_COUNT,
NAME);
} else {
retval = alloc_chrdev_region(&dev_id, 0, CS5535_GPIO_COUNT,
NAME);
major = MAJOR(dev_id);
}
if (retval) {
release_region(gpio_base, CS5535_GPIO_SIZE);
return -1;
}
printk(KERN_DEBUG NAME ": base=%#x mask=%#lx major=%d\n",
gpio_base, mask, major);
cdev_init(&cs5535_gpio_cdev, &cs5535_gpio_fops);
cdev_add(&cs5535_gpio_cdev, dev_id, CS5535_GPIO_COUNT);
return 0;
}
static int __init pmc_core_probe(void)
{
struct pmc_dev *pmcdev = &pmc;
const struct x86_cpu_id *cpu_id;
u64 slp_s0_addr;
int err;
cpu_id = x86_match_cpu(intel_pmc_core_ids);
if (!cpu_id)
return -ENODEV;
pmcdev->map = (struct pmc_reg_map *)cpu_id->driver_data;
/*
* Coffeelake has CPU ID of Kabylake and Cannonlake PCH. So here
* Sunrisepoint PCH regmap can't be used. Use Cannonlake PCH regmap
* in this case.
*/
if (!pci_dev_present(pmc_pci_ids))
pmcdev->map = &cnp_reg_map;
if (lpit_read_residency_count_address(&slp_s0_addr))
pmcdev->base_addr = PMC_BASE_ADDR_DEFAULT;
else
pmcdev->base_addr = slp_s0_addr - pmcdev->map->slp_s0_offset;
pmcdev->regbase = ioremap(pmcdev->base_addr,
pmcdev->map->regmap_length);
if (!pmcdev->regbase)
return -ENOMEM;
mutex_init(&pmcdev->lock);
pmcdev->pmc_xram_read_bit = pmc_core_check_read_lock_bit();
err = pmc_core_dbgfs_register(pmcdev);
if (err < 0) {
pr_warn(" debugfs register failed.\n");
iounmap(pmcdev->regbase);
return err;
}
pr_info(" initialized\n");
return 0;
}
static bool lpe_audio_detect(struct drm_i915_private *dev_priv)
{
int lpe_present = false;
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
static const struct pci_device_id atom_hdaudio_ids[] = {
/* Baytrail */
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0f04)},
/* Braswell */
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2284)},
{}
};
if (!pci_dev_present(atom_hdaudio_ids)) {
DRM_INFO("HDaudio controller not detected, using LPE audio instead\n");
lpe_present = true;
}
}
return lpe_present;
}
int mv643xx_eth_add_pds(void)
{
int ret = 0;
static struct pci_device_id pci_marvell_mv64360[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_MV64360) },
{ }
};
#ifdef BE_VERBOSE
printk("Pegasos II/Marvell MV64361: init\n");
#endif
if (pci_dev_present(pci_marvell_mv64360)) {
ret = platform_add_devices(mv643xx_eth_pd_devs,
ARRAY_SIZE(mv643xx_eth_pd_devs));
if ( Enable_SRAM() < 0)
{
eth0_pd.tx_sram_addr = 0;
eth0_pd.tx_sram_size = 0;
eth0_pd.rx_sram_addr = 0;
eth0_pd.rx_sram_size = 0;
eth1_pd.tx_sram_addr = 0;
eth1_pd.tx_sram_size = 0;
eth1_pd.rx_sram_addr = 0;
eth1_pd.rx_sram_size = 0;
#ifdef BE_VERBOSE
printk("Pegasos II/Marvell MV64361: Can't enable the "
"SRAM\n");
#endif
}
}
#ifdef BE_VERBOSE
printk("Pegasos II/Marvell MV64361: init is over\n");
#endif
return ret;
}
static int tulip_init_one (struct pci_dev *pdev,
const struct pci_device_id *ent)
{
struct tulip_private *tp;
/* See note below on the multiport cards. */
static unsigned char last_phys_addr[6] = {0x00, 'L', 'i', 'n', 'u', 'x'};
static struct pci_device_id early_486_chipsets[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82424) },
{ PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496) },
{ },
};
#if defined(__i386__)
static int last_irq;
#endif
u8 chip_rev;
unsigned int i, irq;
unsigned short sum;
u8 ee_data[EEPROM_SIZE];
/*RTnet*/struct rtnet_device *rtdev;
long ioaddr;
static int board_idx = -1;
int chip_idx = ent->driver_data;
unsigned int t2104x_mode = 0;
unsigned int eeprom_missing = 0;
#ifndef MODULE
static int did_version; /* Already printed version info. */
if (tulip_debug > 0 && did_version++ == 0)
printk(KERN_INFO "%s", version);
#endif
board_idx++;
if (cards[board_idx] == 0)
return -ENODEV;
/*
* Lan media wire a tulip chip to a wan interface. Needs a very
* different driver (lmc driver)
*/
if (pdev->subsystem_vendor == PCI_VENDOR_ID_LMC) {
printk(KERN_ERR PFX "skipping LMC card.\n");
return -ENODEV;
}
/*
* Early DM9100's need software CRC and the DMFE driver
*/
if (pdev->vendor == 0x1282 && pdev->device == 0x9100)
{
u32 dev_rev;
/* Read Chip revision */
pci_read_config_dword(pdev, PCI_REVISION_ID, &dev_rev);
if(dev_rev < 0x02000030)
{
printk(KERN_ERR PFX "skipping early DM9100 with Crc bug (use dmfe)\n");
return -ENODEV;
}
}
/*
* Looks for early PCI chipsets where people report hangs
* without the workarounds being on.
*/
/* 1. Intel Saturn. Switch to 8 long words burst, 8 long word cache
aligned. Aries might need this too. The Saturn errata are not
pretty reading but thankfully it's an old 486 chipset.
2. The dreaded SiS496 486 chipset. Same workaround as Intel
Saturn.
*/
if (pci_dev_present(early_486_chipsets))
csr0 = MRL | MRM | (8 << BurstLenShift) | (1 << CALShift);
/* bugfix: the ASIX must have a burst limit or horrible things happen. */
if (chip_idx == AX88140) {
if ((csr0 & 0x3f00) == 0)
csr0 |= 0x2000;
}
/* PNIC doesn't have MWI/MRL/MRM... */
if (chip_idx == LC82C168)
csr0 &= ~0xfff10000; /* zero reserved bits 31:20, 16 */
/* DM9102A has troubles with MRM & clear reserved bits 24:22, 20, 16, 7:1 */
if (pdev->vendor == 0x1282 && pdev->device == 0x9102)
csr0 &= ~0x01f100ff;
#if defined(__sparc__)
/* DM9102A needs 32-dword alignment/burst length on sparc - chip bug? */
if (pdev->vendor == 0x1282 && pdev->device == 0x9102)
csr0 = (csr0 & ~0xff00) | 0xe000;
#endif
/*
* And back to business
*/
i = pci_enable_device(pdev);
if (i) {
printk(KERN_ERR PFX
"Cannot enable tulip board #%d, aborting\n",
board_idx);
return i;
}
ioaddr = pci_resource_start (pdev, 0);
irq = pdev->irq;
/* alloc_etherdev ensures aligned and zeroed private structures */
rtdev = /*RTnet*/rt_alloc_etherdev (sizeof (*tp), RX_RING_SIZE*2);
if (!rtdev) {
printk(KERN_ERR PFX "ether device alloc failed, aborting\n");
return -ENOMEM;
}
//rtdev_alloc_name(rtdev, "eth%d");//Done by register_rtdev()
rt_rtdev_connect(rtdev, &RTDEV_manager);
rtdev->vers = RTDEV_VERS_2_0;
if (pci_resource_len (pdev, 0) < tulip_tbl[chip_idx].io_size) {
printk(KERN_ERR PFX "%s: I/O region (0x%llx@0x%llx) too small, "
"aborting\n", pci_name(pdev),
(unsigned long long)pci_resource_len (pdev, 0),
(unsigned long long)pci_resource_start (pdev, 0));
goto err_out_free_netdev;
}
/* grab all resources from both PIO and MMIO regions, as we
* don't want anyone else messing around with our hardware */
if (pci_request_regions (pdev, "tulip"))
goto err_out_free_netdev;
#ifndef USE_IO_OPS
ioaddr = (unsigned long) ioremap (pci_resource_start (pdev, 1),
tulip_tbl[chip_idx].io_size);
if (!ioaddr)
goto err_out_free_res;
#endif
pci_read_config_byte (pdev, PCI_REVISION_ID, &chip_rev);
/*
* initialize private data structure 'tp'
* it is zeroed and aligned in alloc_etherdev
*/
tp = rtdev->priv;
tp->rx_ring = pci_alloc_consistent(pdev,
sizeof(struct tulip_rx_desc) * RX_RING_SIZE +
sizeof(struct tulip_tx_desc) * TX_RING_SIZE,
&tp->rx_ring_dma);
if (!tp->rx_ring)
goto err_out_mtable;
tp->tx_ring = (struct tulip_tx_desc *)(tp->rx_ring + RX_RING_SIZE);
tp->tx_ring_dma = tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * RX_RING_SIZE;
tp->chip_id = chip_idx;
tp->flags = tulip_tbl[chip_idx].flags;
tp->pdev = pdev;
tp->base_addr = ioaddr;
tp->revision = chip_rev;
tp->csr0 = csr0;
rtdm_lock_init(&tp->lock);
spin_lock_init(&tp->mii_lock);
rtdev->base_addr = ioaddr;
rtdev->irq = irq;
#ifdef XXX_CONFIG_TULIP_MWI
if (!force_csr0 && (tp->flags & HAS_PCI_MWI))
tulip_mwi_config (pdev, rtdev);
#else
/* MWI is broken for DC21143 rev 65... */
if (chip_idx == DC21143 && chip_rev == 65)
tp->csr0 &= ~MWI;
#endif
/* Stop the chip's Tx and Rx processes. */
tulip_stop_rxtx(tp);
pci_set_master(pdev);
/* Clear the missed-packet counter. */
inl(ioaddr + CSR8);
if (chip_idx == DC21041) {
if (inl(ioaddr + CSR9) & 0x8000) {
chip_idx = DC21040;
t2104x_mode = 1;
} else {
t2104x_mode = 2;
}
}
/* The station address ROM is read byte serially. The register must
be polled, waiting for the value to be read bit serially from the
EEPROM.
*/
sum = 0;
if (chip_idx == DC21040) {
outl(0, ioaddr + CSR9); /* Reset the pointer with a dummy write. */
for (i = 0; i < 6; i++) {
int value, boguscnt = 100000;
do
value = inl(ioaddr + CSR9);
while (value < 0 && --boguscnt > 0);
rtdev->dev_addr[i] = value;
sum += value & 0xff;
}
} else if (chip_idx == LC82C168) {
for (i = 0; i < 3; i++) {
int value, boguscnt = 100000;
outl(0x600 | i, ioaddr + 0x98);
do
value = inl(ioaddr + CSR9);
while (value < 0 && --boguscnt > 0);
put_unaligned(le16_to_cpu(value), ((u16*)rtdev->dev_addr) + i);
sum += value & 0xffff;
}
} else if (chip_idx == COMET) {
/* No need to read the EEPROM. */
put_unaligned(inl(ioaddr + 0xA4), (u32 *)rtdev->dev_addr);
put_unaligned(inl(ioaddr + 0xA8), (u16 *)(rtdev->dev_addr + 4));
for (i = 0; i < 6; i ++)
sum += rtdev->dev_addr[i];
} else {
/* A serial EEPROM interface, we read now and sort it out later. */
int sa_offset = 0;
int ee_addr_size = tulip_read_eeprom(ioaddr, 0xff, 8) & 0x40000 ? 8 : 6;
for (i = 0; i < sizeof(ee_data)/2; i++)
((u16 *)ee_data)[i] =
le16_to_cpu(tulip_read_eeprom(ioaddr, i, ee_addr_size));
/* DEC now has a specification (see Notes) but early board makers
just put the address in the first EEPROM locations. */
/* This does memcmp(eedata, eedata+16, 8) */
for (i = 0; i < 8; i ++)
if (ee_data[i] != ee_data[16+i])
sa_offset = 20;
if (ee_data[0] == 0xff && ee_data[1] == 0xff && ee_data[2] == 0)
sa_offset = 2; /* Grrr, damn Matrox boards. */
#ifdef CONFIG_DDB5476
if ((pdev->bus->number == 0) && (PCI_SLOT(pdev->devfn) == 6)) {
/* DDB5476 MAC address in first EEPROM locations. */
sa_offset = 0;
/* No media table either */
tp->flags &= ~HAS_MEDIA_TABLE;
}
#endif
#ifdef CONFIG_DDB5477
if ((pdev->bus->number == 0) && (PCI_SLOT(pdev->devfn) == 4)) {
/* DDB5477 MAC address in first EEPROM locations. */
sa_offset = 0;
/* No media table either */
tp->flags &= ~HAS_MEDIA_TABLE;
}
#endif
#ifdef CONFIG_MIPS_COBALT
if ((pdev->bus->number == 0) &&
((PCI_SLOT(pdev->devfn) == 7) ||
(PCI_SLOT(pdev->devfn) == 12))) {
/* Cobalt MAC address in first EEPROM locations. */
sa_offset = 0;
/* No media table either */
tp->flags &= ~HAS_MEDIA_TABLE;
}
#endif
for (i = 0; i < 6; i ++) {
rtdev->dev_addr[i] = ee_data[i + sa_offset];
sum += ee_data[i + sa_offset];
}
}
/* Lite-On boards have the address byte-swapped. */
if ((rtdev->dev_addr[0] == 0xA0 || rtdev->dev_addr[0] == 0xC0)
&& rtdev->dev_addr[1] == 0x00)
for (i = 0; i < 6; i+=2) {
char tmp = rtdev->dev_addr[i];
rtdev->dev_addr[i] = rtdev->dev_addr[i+1];
rtdev->dev_addr[i+1] = tmp;
}
/* On the Zynx 315 Etherarray and other multiport boards only the
first Tulip has an EEPROM.
On Sparc systems the mac address is held in the OBP property
"local-mac-address".
The addresses of the subsequent ports are derived from the first.
Many PCI BIOSes also incorrectly report the IRQ line, so we correct
that here as well. */
if (sum == 0 || sum == 6*0xff) {
#if defined(__sparc__)
struct pcidev_cookie *pcp = pdev->sysdata;
#endif
eeprom_missing = 1;
for (i = 0; i < 5; i++)
rtdev->dev_addr[i] = last_phys_addr[i];
rtdev->dev_addr[i] = last_phys_addr[i] + 1;
#if defined(__sparc__)
if ((pcp != NULL) && prom_getproplen(pcp->prom_node,
"local-mac-address") == 6) {
prom_getproperty(pcp->prom_node, "local-mac-address",
rtdev->dev_addr, 6);
}
#endif
#if defined(__i386__) /* Patch up x86 BIOS bug. */
if (last_irq)
irq = last_irq;
#endif
}
for (i = 0; i < 6; i++)
last_phys_addr[i] = rtdev->dev_addr[i];
#if defined(__i386__)
last_irq = irq;
#endif
/* The lower four bits are the media type. */
if (board_idx >= 0 && board_idx < MAX_UNITS) {
/* Somehow required for this RTnet version, don't ask me why... */
if (!options[board_idx])
tp->default_port = 11; /*MII*/
/*RTnet*/
if (options[board_idx] & MEDIA_MASK)
tp->default_port = options[board_idx] & MEDIA_MASK;
if ((options[board_idx] & FullDuplex) || full_duplex[board_idx] > 0)
tp->full_duplex = 1;
if (mtu[board_idx] > 0)
rtdev->mtu = mtu[board_idx];
}
if (rtdev->mem_start & MEDIA_MASK)
tp->default_port = rtdev->mem_start & MEDIA_MASK;
if (tp->default_port) {
printk(KERN_INFO "tulip%d: Transceiver selection forced to %s.\n",
board_idx, medianame[tp->default_port & MEDIA_MASK]);
tp->medialock = 1;
if (tulip_media_cap[tp->default_port] & MediaAlwaysFD)
tp->full_duplex = 1;
}
if (tp->full_duplex)
tp->full_duplex_lock = 1;
if (tulip_media_cap[tp->default_port] & MediaIsMII) {
u16 media2advert[] = { 0x20, 0x40, 0x03e0, 0x60, 0x80, 0x100, 0x200 };
tp->mii_advertise = media2advert[tp->default_port - 9];
tp->mii_advertise |= (tp->flags & HAS_8023X); /* Matching bits! */
}
if (tp->flags & HAS_MEDIA_TABLE) {
memcpy(tp->eeprom, ee_data, sizeof(tp->eeprom));
sprintf(rtdev->name, "tulip%d", board_idx); /* hack */
tulip_parse_eeprom(rtdev);
strcpy(rtdev->name, "rteth%d"); /* un-hack */
}
if ((tp->flags & ALWAYS_CHECK_MII) ||
(tp->mtable && tp->mtable->has_mii) ||
( ! tp->mtable && (tp->flags & HAS_MII))) {
if (tp->mtable && tp->mtable->has_mii) {
for (i = 0; i < tp->mtable->leafcount; i++)
if (tp->mtable->mleaf[i].media == 11) {
tp->cur_index = i;
tp->saved_if_port = rtdev->if_port;
tulip_select_media(rtdev, 2);
rtdev->if_port = tp->saved_if_port;
break;
}
}
/* Find the connected MII xcvrs.
Doing this in open() would allow detecting external xcvrs
later, but takes much time. */
tulip_find_mii (rtdev, board_idx);
}
rtdev->open = tulip_open;
rtdev->stop = tulip_close;
rtdev->hard_header = rt_eth_header;
rtdev->hard_start_xmit = tulip_start_xmit;
rtdev->get_stats = tulip_get_stats;
if (/*RTnet*/rt_register_rtnetdev(rtdev)) {
goto err_out_free_ring;
}
printk(KERN_INFO "%s: %s rev %d at %#3lx,",
rtdev->name, tulip_tbl[chip_idx].chip_name, chip_rev, ioaddr);
pci_set_drvdata(pdev, rtdev);
if (t2104x_mode == 1)
printk(" 21040 compatible mode,");
else if (t2104x_mode == 2)
printk(" 21041 mode,");
if (eeprom_missing)
printk(" EEPROM not present,");
for (i = 0; i < 6; i++)
printk("%c%2.2X", i ? ':' : ' ', rtdev->dev_addr[i]);
printk(", IRQ %d.\n", irq);
/*RTnet
if (tp->chip_id == PNIC2)
tp->link_change = pnic2_lnk_change;
else if ((tp->flags & HAS_NWAY) || tp->chip_id == DC21041)
tp->link_change = t21142_lnk_change;
else if (tp->flags & HAS_PNICNWAY)
tp->link_change = pnic_lnk_change;
*RTnet*/
tp->link_change = NULL;
/* Reset the xcvr interface and turn on heartbeat. */
switch (chip_idx) {
case DC21041:
if (tp->sym_advertise == 0)
tp->sym_advertise = 0x0061;
outl(0x00000000, ioaddr + CSR13);
outl(0xFFFFFFFF, ioaddr + CSR14);
outl(0x00000008, ioaddr + CSR15); /* Listen on AUI also. */
outl(inl(ioaddr + CSR6) | csr6_fd, ioaddr + CSR6);
outl(0x0000EF01, ioaddr + CSR13);
break;
case DC21040:
outl(0x00000000, ioaddr + CSR13);
outl(0x00000004, ioaddr + CSR13);
break;
case DC21140:
case DM910X:
default:
if (tp->mtable)
outl(tp->mtable->csr12dir | 0x100, ioaddr + CSR12);
break;
case DC21142:
if (tp->mii_cnt || tulip_media_cap[rtdev->if_port] & MediaIsMII) {
outl(csr6_mask_defstate, ioaddr + CSR6);
outl(0x0000, ioaddr + CSR13);
outl(0x0000, ioaddr + CSR14);
outl(csr6_mask_hdcap, ioaddr + CSR6);
} else
t21142_start_nway(rtdev);
break;
case PNIC2:
/* just do a reset for sanity sake */
outl(0x0000, ioaddr + CSR13);
outl(0x0000, ioaddr + CSR14);
break;
case LC82C168:
if ( ! tp->mii_cnt) {
tp->nway = 1;
tp->nwayset = 0;
outl(csr6_ttm | csr6_ca, ioaddr + CSR6);
outl(0x30, ioaddr + CSR12);
outl(0x0001F078, ioaddr + CSR6);
outl(0x0201F078, ioaddr + CSR6); /* Turn on autonegotiation. */
}
break;
case MX98713:
case COMPEX9881:
outl(0x00000000, ioaddr + CSR6);
outl(0x000711C0, ioaddr + CSR14); /* Turn on NWay. */
outl(0x00000001, ioaddr + CSR13);
break;
case MX98715:
case MX98725:
outl(0x01a80000, ioaddr + CSR6);
outl(0xFFFFFFFF, ioaddr + CSR14);
outl(0x00001000, ioaddr + CSR12);
break;
case COMET:
/* No initialization necessary. */
break;
}
/* put the chip in snooze mode until opened */
tulip_set_power_state (tp, 0, 1);
return 0;
err_out_free_ring:
pci_free_consistent (pdev,
sizeof (struct tulip_rx_desc) * RX_RING_SIZE +
sizeof (struct tulip_tx_desc) * TX_RING_SIZE,
tp->rx_ring, tp->rx_ring_dma);
err_out_mtable:
if (tp->mtable)
kfree (tp->mtable);
#ifndef USE_IO_OPS
iounmap((void *)ioaddr);
err_out_free_res:
#endif
pci_release_regions (pdev);
err_out_free_netdev:
/*RTnet*/rtdev_free (rtdev);
return -ENODEV;
}
static int __init cs5535_gpio_init(void)
{
dev_t dev_id;
u32 low, hi;
int retval;
if (pci_dev_present(divil_pci) == 0) {
printk(KERN_WARNING NAME ": DIVIL not found\n");
return -ENODEV;
}
/* Grab the GPIO I/O range */
rdmsr(MSR_LBAR_GPIO, low, hi);
/* Check the mask and whether GPIO is enabled (sanity check) */
if (hi != 0x0000f001) {
printk(KERN_WARNING NAME ": GPIO not enabled\n");
return -ENODEV;
}
/* Mask off the IO base address */
gpio_base = low & 0x0000ff00;
/**
* Some GPIO pins
* 31-29,23 : reserved (always mask out)
* 28 : Power Button
* 26 : PME#
* 22-16 : LPC
* 14,15 : SMBus
* 9,8 : UART1
* 7 : PCI INTB
* 3,4 : UART2/DDC
* 2 : IDE_IRQ0
* 0 : PCI INTA
*
* If a mask was not specified, be conservative and only allow:
* 1,2,5,6,10-13,24,25,27
*/
if (mask != 0)
mask &= 0x1f7fffff;
else
mask = 0x0b003c66;
if (request_region(gpio_base, CS5535_GPIO_SIZE, NAME) == 0) {
printk(KERN_ERR NAME ": can't allocate I/O for GPIO\n");
return -ENODEV;
}
if (major) {
dev_id = MKDEV(major, 0);
retval = register_chrdev_region(dev_id, CS5535_GPIO_COUNT,
NAME);
} else {
retval = alloc_chrdev_region(&dev_id, 0, CS5535_GPIO_COUNT,
NAME);
major = MAJOR(dev_id);
}
if (retval) {
release_region(gpio_base, CS5535_GPIO_SIZE);
return -1;
}
printk(KERN_DEBUG NAME ": base=%#x mask=%#lx major=%d\n",
gpio_base, mask, major);
cdev_init(&cs5535_gpio_cdev, &cs5535_gpio_fops);
cdev_add(&cs5535_gpio_cdev, dev_id, CS5535_GPIO_COUNT);
return 0;
}
