void lpc_read_resources(device_t dev)
{
struct resource *res;
printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_read_resources - Start.\n");
/* Get the normal pci resources of this device */
pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */
pci_get_resource(dev, SPIROM_BASE_ADDRESS); /* SPI ROM base address */
/* Add an extra subtractive resource for both memory and I/O. */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
res->base = 0;
res->size = 0x1000;
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
res->base = 0xff800000;
res->size = 0x00800000; /* 8 MB for flash */
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
res->base = 0xfec00000;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
compact_resources(dev);
printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_read_resources - End.\n");
}
static void pch_lpc_read_resources(device_t dev)
{
struct resource *res;
config_t *config = dev->chip_info;
u8 io_index = 0;
/* Get the normal PCI resources of this device. */
pci_dev_read_resources(dev);
/* Add an extra subtractive resource for both memory and I/O. */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
res->base = 0;
res->size = 0x1000;
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
res->base = 0xff800000;
res->size = 0x00800000; /* 8 MB for flash */
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
/* Set PCH IO decode ranges if required.*/
if ((config->gen1_dec & 0xFFFC) > 0x1000) {
res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
res->base = config->gen1_dec & 0xFFFC;
res->size = (config->gen1_dec >> 16) & 0xFC;
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
static void nc_read_resources(struct device *dev)
{
unsigned long mmconf;
unsigned long bmbound;
unsigned long bmbound_hi;
unsigned long smmrrh;
unsigned long smmrrl;
unsigned long base_k, size_k;
const unsigned long four_gig_kib = (4 << (30 - 10));
int index = 0;
/* Read standard PCI resources. */
pci_dev_read_resources(dev);
/* PCIe memory-mapped config space access - 256 MiB. */
mmconf = iosf_bunit_read(BUNIT_MMCONF_REG) & ~((1 << 28) - 1);
mmio_resource(dev, BUNIT_MMCONF_REG, RES_IN_KiB(mmconf), 256 * 1024);
/* 0 -> 0xa0000 */
base_k = RES_IN_KiB(0);
size_k = RES_IN_KiB(0xa0000) - base_k;
ram_resource(dev, index++, base_k, size_k);
/* The SMMRR registers are 1MiB granularity with smmrrh being
* inclusive of the SMM region. */
smmrrl = (iosf_bunit_read(BUNIT_SMRRL) & 0xffff) << 10;
smmrrh = ((iosf_bunit_read(BUNIT_SMRRH) & 0xffff) + 1) << 10;
/* 0xc0000 -> smrrl - cacheable and usable */
base_k = RES_IN_KiB(0xc0000);
size_k = smmrrl - base_k;
ram_resource(dev, index++, base_k, size_k);
if (smmrrh > smmrrl)
reserved_ram_resource(dev, index++, smmrrl, smmrrh - smmrrl);
/* All address space between bmbound and smmrrh is unusable. */
bmbound = RES_IN_KiB(nc_read_top_of_low_memory());
mmio_resource(dev, index++, smmrrh, bmbound - smmrrh);
/* The BMBOUND_HI register matches register bits of 31:24 with address
* bits of 35:28. Therefore, shift register to align properly. */
bmbound_hi = iosf_bunit_read(BUNIT_BMBOUND_HI) & ~((1 << 24) - 1);
bmbound_hi = RES_IN_KiB(bmbound_hi) << 4;
if (bmbound_hi > four_gig_kib)
ram_resource(dev, index++, four_gig_kib,
bmbound_hi - four_gig_kib);
/* Reserve everything between A segment and 1MB:
*
* 0xa0000 - 0xbffff: legacy VGA
* 0xc0000 - 0xfffff: RAM
*/
mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);
reserved_ram_resource(dev, index++, (0xc0000 >> 10),
(0x100000 - 0xc0000) >> 10);
if (CONFIG(CHROMEOS))
chromeos_reserve_ram_oops(dev, index++);
}
static void pci_pmc_read_resources(struct device *dev)
{
struct resource *res;
/* Get the normal PCI resources of this device. */
pci_dev_read_resources(dev);
/* Add MMIO resource
* Use 0xaa as an unused index for PWRM BAR.
*/
u32 reg32 = pci_read_config32(dev, PMC_PWRM_BASE) & MASK_PMC_PWRM_BASE;
if ((reg32 != 0x0) && (reg32 != 0xffffffff)) {
res = new_resource(dev, 0xaa);
res->base = reg32;
res->size = 64 * 1024; /* 64K bytes memory config space */
res->flags =
IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
printk(BIOS_DEBUG,
"Adding PMC PWRM config space BAR 0x%08lx-0x%08lx.\n",
(unsigned long)(res->base),
(unsigned long)(res->base + res->size));
}
/* Add MMIO resource
* Use 0xab as an unused index for ACPI BAR.
*/
u16 reg16 = pci_read_config16(dev, PMC_ACPI_BASE) & MASK_PMC_ACPI_BASE;
if ((reg16 != 0x0) && (reg16 != 0xffff)) {
res = new_resource(dev, 0xab);
res->base = reg16;
res->size = 0x100; /* 256 bytes I/O config space */
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
}
static void sb600_lpc_read_resources(device_t dev)
{
struct resource *res;
/* Get the normal pci resources of this device */
pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */
pci_get_resource(dev, 0xA0); /* SPI ROM base address */
/* Add an extra subtractive resource for both memory and I/O. */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
res->base = 0;
res->size = 0x1000;
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
res->base = 0xff800000;
res->size = 0x00800000; /* 8 MB for flash */
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
compact_resources(dev);
}
static void sch_lpc_read_resources(device_t dev)
{
struct resource *res;
/* Get the normal PCI resources of this device. */
pci_dev_read_resources(dev);
/* Add an extra subtractive resource for both memory and I/O. */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
res->base = 0;
res->size = 0xe000;
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
res->base = 0xff800000;
res->size = 0x00800000; /* 8 MB for flash */
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3);
res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
void lpc_read_resources(device_t dev)
{
struct resource *res;
printk(BIOS_SPEW, "SB700 - Lpc.c - %s - Start.\n", __func__);
/* Get the normal pci resources of this device */
pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */
/* Add an extra subtractive resource for both memory and I/O. */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
res->base = 0;
res->size = 0x1000;
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
res->base = 0xff800000;
res->size = 0x00800000; /* 8 MB for flash */
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
/* Add a memory resource for the SPI BAR. */
fixed_mem_resource(dev, 2, SPI_BASE_ADDRESS / 1024, 1, IORESOURCE_SUBTRACTIVE);
res = new_resource(dev, 3);
res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
compact_resources(dev);
printk(BIOS_SPEW, "SB700 - Lpc.c - %s - End.\n", __func__);
}
static void pch_lpc_read_resources(struct device *dev)
{
/* Get the PCI resources of this device. */
pci_dev_read_resources(dev);
/* Add IO resources to LPC. */
pch_lpc_add_io_resources(dev);
}
static void soc_lpc_read_resources(device_t dev)
{
/* Get the PCI resources of this device. */
pci_dev_read_resources(dev);
/* Add IO resources to LPC. */
soc_lpc_add_io_resources(dev);
}
static void lpe_read_resources(device_t dev)
{
pci_dev_read_resources(dev);
reserved_ram_resource(dev, FIRMWARE_PCI_REG_BASE,
FIRMWARE_PHYS_BASE >> 10,
FIRMWARE_PHYS_LENGTH >> 10);
}
static void qemu_nb_read_resources(struct device *dev)
{
pci_dev_read_resources(dev);
/* reserve mmconfig */
fixed_mem_resource(dev, 2, CONFIG_MMCONF_BASE_ADDRESS >> 10, 0x10000000 >> 10,
IORESOURCE_RESERVE);
}
static void nc_read_resources(device_t dev)
{
/* Call the normal read_resources */
pci_dev_read_resources(dev);
/* Calculate and add DRAM resources. */
mc_add_dram_resources(dev);
}
static void sb700_sm_read_resources(device_t dev)
{
struct resource *res;
/* Get the normal pci resources of this device */
pci_dev_read_resources(dev);
/* apic */
res = new_resource(dev, 0x74);
res->base = IO_APIC_ADDR;
res->size = 256 * 0x10;
res->limit = 0xFFFFFFFFUL; /* res->base + res->size -1; */
res->align = 8;
res->gran = 8;
res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED;
/* SB MMIO / WDT */
res = new_resource(dev, SB_MMIO_CFG_REG);
res->base = SB_MMIO_BASE_ADDRESS;
res->size = 0x1000;
res->limit = 0xFFFFFFFFUL; /* res->base + res->size -1; */
res->align = 8;
res->gran = 8;
res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED;
/* HPET */
res = new_resource(dev, 0xB4); /* TODO: test hpet */
res->base = 0xfed00000; /* reset hpet to widely accepted address */
res->size = 0x400;
res->limit = 0xFFFFFFFFUL; /* res->base + res->size -1; */
res->align = 8;
res->gran = 8;
res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED;
/* dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; */
/* primary smbus */
res = new_resource(dev, PRIMARY_SMBUS_RESOURCE_NUMBER);
res->base = SMBUS_IO_BASE;
res->size = 0x10;
res->limit = 0xFFFFUL; /* res->base + res->size -1; */
res->align = 8;
res->gran = 8;
res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED;
/* auxiliary smbus */
res = new_resource(dev, AUXILIARY_SMBUS_RESOURCE_NUMBER);
res->base = SMBUS_AUX_IO_BASE;
res->size = 0x10;
res->limit = 0xFFFFUL; /* res->base + res->size -1; */
res->align = 8;
res->gran = 8;
res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED;
compact_resources(dev);
}
static void rd890_read_resource(struct device *dev)
{
pci_dev_read_resources(dev);
/* rpr6.2.(1). Write the Base Address Register (BAR) */
pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */
pci_get_resource(dev, 0xFC); /* APIC located in sr5690 */
compact_resources(dev);
}
static void bcm5785_ide_read_resources(device_t dev)
{
/* Get the normal pci resources of this device */
pci_dev_read_resources(dev);
/* BAR */
pci_get_resource(dev, 0x64);
compact_resources(dev);
}
static void i82801ix_lpc_read_resources(device_t dev)
{
/*
* I/O Resources
*
* 0x0000 - 0x000f....ISA DMA
* 0x0010 - 0x001f....ISA DMA aliases
* 0x0020 ~ 0x003d....PIC
* 0x002e - 0x002f....Maybe Super I/O
* 0x0040 - 0x0043....Timer
* 0x004e - 0x004f....Maybe Super I/O
* 0x0050 - 0x0053....Timer aliases
* 0x0061.............NMI_SC
* 0x0070.............NMI_EN (readable in alternative access mode)
* 0x0070 - 0x0077....RTC
* 0x0080 - 0x008f....ISA DMA
* 0x0090 ~ 0x009f....ISA DMA aliases
* 0x0092.............Fast A20 and Init
* 0x00a0 ~ 0x00bd....PIC
* 0x00b2 - 0x00b3....APM
* 0x00c0 ~ 0x00de....ISA DMA
* 0x00c1 ~ 0x00df....ISA DMA aliases
* 0x00f0.............Coprocessor Error
* (0x0400-0x041f)....SMBus (SMBUS_IO_BASE, during raminit)
* 0x04d0 - 0x04d1....PIC
* 0x0500 - 0x057f....PM (DEFAULT_PMBASE)
* 0x0580 - 0x05bf....SB GPIO (DEFAULT_GPIOBASE)
* 0x05c0 - 0x05ff....SB GPIO cont. (mobile only)
* 0x0cf8 - 0x0cff....PCI
* 0x0cf9.............Reset Control
*/
struct resource *res;
/* Get the normal PCI resources of this device. */
pci_dev_read_resources(dev);
/* Add an extra subtractive resource for both memory and I/O. */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
res->base = 0;
res->size = 0x1000;
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
res->base = 0xff800000;
res->size = 0x00800000; /* 8 MB for flash */
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
static void aplk_uart_read_resources(struct device *dev)
{
pci_dev_read_resources(dev);
if ((IS_ENABLED(CONFIG_SOC_UART_DEBUG) &&
dev->path.pci.devfn == _PCH_DEVFN(UART,
CONFIG_UART_FOR_CONSOLE))) {
/* will override existing resource. */
fixed_mem_resource(dev, PCI_BASE_ADDRESS_0,
CONFIG_CONSOLE_UART_BASE_ADDRESS >> 10, 4, 0);
}
static void pch_pmc_read_resources(device_t dev)
{
/* Get the normal PCI resources of this device. */
pci_dev_read_resources(dev);
/* Add non-standard MMIO resources. */
pch_pmc_add_mmio_resources(dev);
/* Add IO resources. */
pch_pmc_add_io_resources(dev);
}
static void mcp55_sm_read_resources(device_t dev)
{
unsigned long index;
/* Get the normal pci resources of this device */
pci_dev_read_resources(dev);
for (index = 0x60; index <= 0x68; index+=4) { // We got another 3.
pci_get_resource(dev, index);
}
compact_resources(dev);
}
/* total kludge to get lxb to call our childrens set/enable functions - these are
not called unless this device has a resource to set - so set a dummy one */
static void vx800_read_resources(device_t dev)
{
struct resource *resource;
pci_dev_read_resources(dev);
resource = new_resource(dev, 1);
resource->flags |=
IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IO |
IORESOURCE_STORED;
resource->size = 2;
resource->base = 0x2e;
}
static void uart_read_resources(device_t dev)
{
struct resource *res;
/* Read the resources */
pci_dev_read_resources(dev);
/* Set the debug port configuration */
res = find_resource(dev, PCI_BASE_ADDRESS_0);
res->base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
res->size = 0x100;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
static void pch_uart_read_resources(struct device *dev)
{
pci_dev_read_resources(dev);
/* Set the configured UART base address for the debug port */
if (IS_ENABLED(CONFIG_UART_DEBUG) && pch_uart_is_debug(dev)) {
struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
/* Need to set the base and size for the resource allocator. */
res->base = UART_DEBUG_BASE_ADDRESS;
res->size = UART_DEBUG_BASE_SIZE;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED;
}
}
static void sc_read_resources(device_t dev)
{
printk(BIOS_SPEW, "%s/%s ( %s )\n",
__FILE__, __func__, dev_name(dev));
/* Get the normal PCI resources of this device. */
pci_dev_read_resources(dev);
/* Add non-standard MMIO resources. */
sc_add_mmio_resources(dev);
/* Add IO resources. */
sc_add_io_resources(dev);
}
static void lpc_read_resources(struct device *dev)
{
/* Get the normal PCI resources of this device. */
pci_dev_read_resources(dev);
/* Add non-standard MMIO resources. */
pch_lpc_add_mmio_resources(dev);
/* Add IO resources. */
pch_lpc_add_io_resources(dev);
/* Add MMIO resource for IOAPIC. */
pci_p2sb_read_resources(dev);
}
static void iommu_read_resources(device_t dev)
{
struct resource *res;
/* Get the normal pci resources of this device */
pci_dev_read_resources(dev);
/* Add an extra subtractive resource for both memory and I/O. */
res = new_resource(dev, 0x44);
res->size = 512 * 1024;
res->align = log2(res->size);
res->gran = log2(res->size);
res->limit = 0xffffffff; /* 4G */
res->flags = IORESOURCE_MEM;
}
static void read_resources(device_t dev)
{
struct resource *res;
pci_dev_read_resources(dev);
res = new_resource(dev, PCI_BASE_ADDRESS_0);
res->base = PMC_SRAM_BASE_0;
res->size = PMC_SRAM_SIZE_0;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, PCI_BASE_ADDRESS_2);
res->base = PMC_SRAM_BASE_1;
res->size = PMC_SRAM_SIZE_1;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
/**
* Read resources for AGP aperture.
*
* There is only one AGP aperture resource needed. The resoruce is added to
* the northbridge of BSP.
*
* The same trick can be used to augment legacy VGA resources which can
* be detect by generic PCI resource allocator for VGA devices.
* BAD: it is more tricky than I think, the resource allocation code is
* implemented in a way to NOT DOING legacy VGA resource allcation on
* purpose :-(.
*
* @param dev TODO
*/
static void sis761_read_resources(device_t dev)
{
/* Read the generic PCI resources */
printk(BIOS_DEBUG, "sis761_read_resources ------->\n");
pci_dev_read_resources(dev);
/* If we are not the first processor don't allocate the gart apeture */
if (dev->path.pci.devfn != PCI_DEVFN(0x0, 0)) {
printk(BIOS_DEBUG, "sis761_not_the_first_processor !!!\n");
return;
}
printk(BIOS_DEBUG, "sis761_read_resources <-------\n");
return;
}
static void nc_read_resources(struct device *dev)
{
unsigned long base_k;
int index = 0;
unsigned long size_k;
/* Read standard PCI resources. */
pci_dev_read_resources(dev);
/* 0 -> 0xa0000 */
base_k = 0;
size_k = 0xa0000 - base_k;
ram_resource(dev, index++, RES_IN_KIB(base_k), RES_IN_KIB(size_k));
/*
* Reserve everything between A segment and 1MB:
*
* 0xa0000 - 0xbffff: legacy VGA
* 0xc0000 - 0xdffff: RAM
* 0xe0000 - 0xfffff: ROM shadow
*/
base_k += size_k;
size_k = 0xc0000 - base_k;
mmio_resource(dev, index++, RES_IN_KIB(base_k), RES_IN_KIB(size_k));
base_k += size_k;
size_k = 0x100000 - base_k;
reserved_ram_resource(dev, index++, RES_IN_KIB(base_k),
RES_IN_KIB(size_k));
/* 0x100000 -> cbmem_top - cacheable and usable */
base_k += size_k;
size_k = (unsigned long)cbmem_top() - base_k;
ram_resource(dev, index++, RES_IN_KIB(base_k), RES_IN_KIB(size_k));
/* cbmem_top -> 0xc0000000 - reserved */
base_k += size_k;
size_k = 0xc0000000 - base_k;
reserved_ram_resource(dev, index++, RES_IN_KIB(base_k),
RES_IN_KIB(size_k));
/* 0xc0000000 -> 4GiB is mmio. */
base_k += size_k;
size_k = 0x100000000ull - base_k;
mmio_resource(dev, index++, RES_IN_KIB(base_k), RES_IN_KIB(size_k));
}
static void sc520_read_resources(device_t dev)
{
struct resource* res;
pci_dev_read_resources(dev);
res = new_resource(dev, 1);
res->base = 0x0UL;
res->size = 0x400UL;
res->limit = 0xffffUL;
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
static void acpi_read_resources(device_t dev)
{
struct resource *resource;
/* Handle the generic bars */
pci_dev_read_resources(dev);
/* Add the ACPI/SMBUS bar */
resource = new_resource(dev, 0x58);
resource->base = 0;
resource->size = 256;
resource->align = log2(256);
resource->gran = log2(256);
resource->limit = 65536;
resource->flags = IORESOURCE_IO;
resource->index = 0x58;
}
