void pci_init(void)
{
  struct pci_controller *hose = &pci9054_hose;

  /*
   * Register the hose
   */
  hose->first_busno = 0;
  hose->last_busno = 0xff;

  /* System memory space */
  pci_set_region(hose->regions + 0,
		 0x00000000, 0x00000000, 0x01000000,
		 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);

  /* PCI Memory space */
  pci_set_region(hose->regions + 1,
		 0x00000000, 0xc0000000, 0x10000000,
		 PCI_REGION_MEM);

  pci_set_ops(hose,
	      pci_hose_read_config_byte_via_dword,
	      pci_hose_read_config_word_via_dword,
	      pci9054_read_config_dword,
	      pci_hose_write_config_byte_via_dword,
	      pci_hose_write_config_word_via_dword,
	      pci9054_write_config_dword);

  hose->region_count = 2;

  pci_register_hose(hose);

  hose->last_busno = pci_hose_scan(hose);
}
Beispiel #2
0
void pci_init_board(void)
{
    struct pci_controller* hose = (struct pci_controller *)&local_hose;
    u16 reg16;

    hose->first_busno = 0;
    hose->last_busno = 0xff;

    pci_set_region(hose->regions + 0,
	CONFIG_SYS_PCI_MEMORY_BUS,
	CONFIG_SYS_PCI_MEMORY_PHYS,
	CONFIG_SYS_PCI_MEMORY_SIZE,
	PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);

    /* PCI memory space */
    pci_set_region(hose->regions + 1,
	CONFIG_SYS_PCI_MEM_BUS,
	CONFIG_SYS_PCI_MEM_PHYS,
	CONFIG_SYS_PCI_MEM_SIZE,
	PCI_REGION_MEM);

    /* ISA/PCI memory space */
    pci_set_region(hose->regions + 2,
	CONFIG_SYS_ISA_MEM_BUS,
	CONFIG_SYS_ISA_MEM_PHYS,
	CONFIG_SYS_ISA_MEM_SIZE,
	PCI_REGION_MEM);

    /* PCI I/O space */
    pci_set_region(hose->regions + 3,
	CONFIG_SYS_PCI_IO_BUS,
	CONFIG_SYS_PCI_IO_PHYS,
	CONFIG_SYS_PCI_IO_SIZE,
	PCI_REGION_IO);

    /* ISA/PCI I/O space */
    pci_set_region(hose->regions + 4,
	CONFIG_SYS_ISA_IO_BUS,
	CONFIG_SYS_ISA_IO_PHYS,
	CONFIG_SYS_ISA_IO_SIZE,
	PCI_REGION_IO);

    hose->region_count = 5;

    pci_setup_indirect(hose,
	MPC106_REG_ADDR,
	MPC106_REG_DATA);

    pci_register_hose(hose);

    hose->last_busno = pci_hose_scan(hose);

    /* Initialises the MPC10x PCI Configuration regs. */
    pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
    reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
    pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);

    /* Clear non-reserved bits in status register */
    pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
}
Beispiel #3
0
void pci_init_board(void)
{
	EFI_STATUS status;

	tnc_hose.first_busno = 0;
	tnc_hose.last_busno = 0xff;

	pci_set_region(tnc_hose.regions + 0, 0, 0,
		gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
	pci_set_region(tnc_hose.regions + 1, CONFIG_SYS_PCI_MEM_BUS, CONFIG_SYS_PCI_MEM_PHYS,
		CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM);
	pci_set_region(tnc_hose.regions + 2, CONFIG_SYS_PCI_IO_BUS, CONFIG_SYS_PCI_IO_PHYS,
		CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
	tnc_hose.region_count = 3;

	pci_setup_type1(&tnc_hose);

	pci_register_hose(&tnc_hose);

	tnc_hose.last_busno = pci_hose_scan(&tnc_hose);

	/* call into FspNotify */
	printf("Calling into FSP (notify phase EnumInitPhaseAfterPciEnumeration): ");
	if ((status = FspNotifyWrapper(NULL, EnumInitPhaseAfterPciEnumeration)) != FSP_SUCCESS)
		printf("fail, error code %x\n", status);
	else
		printf("OK\n");
}
Beispiel #4
0
int pci_sh4_init(struct pci_controller *hose)
{
	hose->first_busno = 0;
	hose->region_count = 0;
	hose->last_busno = 0xff;

	/* PCI memory space */
	pci_set_region(hose->regions + 0,
		CONFIG_PCI_MEM_BUS,
		CONFIG_PCI_MEM_PHYS,
		CONFIG_PCI_MEM_SIZE,
		PCI_REGION_MEM);
	hose->region_count++;

	/* PCI IO space */
	pci_set_region(hose->regions + 1,
		CONFIG_PCI_IO_BUS,
		CONFIG_PCI_IO_PHYS,
		CONFIG_PCI_IO_SIZE,
		PCI_REGION_IO);
	hose->region_count++;

#if defined(CONFIG_PCI_SYS_BUS)
	/* PCI System Memory space */
	pci_set_region(hose->regions + 2,
		CONFIG_PCI_SYS_BUS,
		CONFIG_PCI_SYS_PHYS,
		CONFIG_PCI_SYS_SIZE,
		PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
	hose->region_count++;
#endif

	udelay(1000);

	pci_set_ops(hose,
		    pci_hose_read_config_byte_via_dword,
		    pci_hose_read_config_word_via_dword,
		    pci_sh4_read_config_dword,
		    pci_hose_write_config_byte_via_dword,
		    pci_hose_write_config_word_via_dword,
		    pci_sh4_write_config_dword);

	pci_register_hose(hose);

	udelay(1000);

#ifdef CONFIG_PCI_SCAN_SHOW
	printf("PCI:   Bus Dev VenId DevId Class Int\n");
#endif
	hose->last_busno = pci_hose_scan(hose);
	return 0;
}
Beispiel #5
0
void pci_mpc824x_init (struct pci_controller *hose)
{
	hose->first_busno = 0;
	hose->last_busno = 0xff;

	/* System memory space */
	pci_set_region(hose->regions + 0,
		       CHRP_PCI_MEMORY_BUS,
		       CHRP_PCI_MEMORY_PHYS,
		       CHRP_PCI_MEMORY_SIZE,
		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);

	/* PCI memory space */
	pci_set_region(hose->regions + 1,
		       CHRP_PCI_MEM_BUS,
		       CHRP_PCI_MEM_PHYS,
		       CHRP_PCI_MEM_SIZE,
		       PCI_REGION_MEM);

	/* ISA/PCI memory space */
	pci_set_region(hose->regions + 2,
		       CHRP_ISA_MEM_BUS,
		       CHRP_ISA_MEM_PHYS,
		       CHRP_ISA_MEM_SIZE,
		       PCI_REGION_MEM);

	/* PCI I/O space */
	pci_set_region(hose->regions + 3,
		       CHRP_PCI_IO_BUS,
		       CHRP_PCI_IO_PHYS,
		       CHRP_PCI_IO_SIZE,
		       PCI_REGION_IO);

	/* ISA/PCI I/O space */
	pci_set_region(hose->regions + 4,
		       CHRP_ISA_IO_BUS,
		       CHRP_ISA_IO_PHYS,
		       CHRP_ISA_IO_SIZE,
		       PCI_REGION_IO);

	hose->region_count = 5;

	pci_setup_indirect(hose,
			   CHRP_REG_ADDR,
			   CHRP_REG_DATA);

	pci_register_hose(hose);

	hose->last_busno = pci_hose_scan(hose);
}
Beispiel #6
0
/*
 * Unlock the configuration bit so that the host system can begin booting
 *
 * This should be used after you have:
 * 1) Called mpc83xx_pci_init()
 * 2) Set up your inbound translation windows to the appropriate size
 */
void mpc83xx_pcislave_unlock(int bus)
{
    struct pci_controller *hose = &pci_hose[bus];
    u32 dev;
    u16 reg16;

    /* Unlock configuration lock in PCI function configuration register */
    dev = PCI_BDF(hose->first_busno, 0, 0);
    pci_hose_read_config_word (hose, dev, PCI_FUNCTION_CONFIG, &reg16);
    reg16 &= ~(PCI_FUNCTION_CFG_LOCK);
    pci_hose_write_config_word (hose, dev, PCI_FUNCTION_CONFIG, reg16);

    /* The configuration bit is now unlocked, so we can scan the bus */
    hose->last_busno = pci_hose_scan(hose);
}
Beispiel #7
0
void pci_init_board(void)
{
    struct pci_controller *hose = &x86_hose;

    /* Stop using the early hose */
    gd->hose = NULL;

    board_pci_setup_hose(hose);
    pci_setup_type1(hose);
    pci_register_hose(hose);

    board_pci_pre_scan(hose);
    hose->last_busno = pci_hose_scan(hose);
    board_pci_post_scan(hose);
}
Beispiel #8
0
int pci_early_init_hose(struct pci_controller **hosep)
{
    struct pci_controller *hose;

    hose = calloc(1, sizeof(struct pci_controller));
    if (!hose)
        return -ENOMEM;

    board_pci_setup_hose(hose);
    pci_setup_type1(hose);
    hose->last_busno = pci_hose_scan(hose);
    gd->hose = hose;
    *hosep = hose;

    return 0;
}
Beispiel #9
0
void pci_init_board(void)
{
	coreboot_hose.config_table = pci_coreboot_config_table;
	coreboot_hose.first_busno = 0;
	coreboot_hose.last_busno = 0;

	pci_set_region(coreboot_hose.regions + 0, 0x0, 0x0, 0xffffffff,
		PCI_REGION_MEM);
	coreboot_hose.region_count = 1;

	pci_setup_type1(&coreboot_hose);

	pci_register_hose(&coreboot_hose);

	pci_hose_scan(&coreboot_hose);
}
Beispiel #10
0
void pci_sc520_init(struct pci_controller *hose)
{
	hose->first_busno = 0;
	hose->last_busno = 0xff;
	hose->region_count = pci_set_regions(hose);

	pci_setup_type1(hose,
			SC520_REG_ADDR,
			SC520_REG_DATA);

	pci_register_hose(hose);

	hose->last_busno = pci_hose_scan(hose);

	/* enable target memory acceses on host brige */
	pci_write_config_word(0, PCI_COMMAND,
			      PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
}
Beispiel #11
0
void pcie_setup_hoses(int busno)
{
	struct pci_controller *hose;
	int i, bus;
	int ret = 0;
	char *env;
	unsigned int delay;

	/*
	 * assume we're called after the PCIX hose is initialized, which takes
	 * bus ID 0 and therefore start numbering PCIe's from 1.
	 */
	bus = busno;
	for (i = 0; i <= 2; i++) {
		/* Check for katmai card presence */
		if (!katmai_pcie_card_present(i))
			continue;

		if (is_end_point(i))
			ret = ppc4xx_init_pcie_endport(i);
		else
			ret = ppc4xx_init_pcie_rootport(i);
		if (ret) {
			printf("PCIE%d: initialization as %s failed\n", i,
			       is_end_point(i) ? "endpoint" : "root-complex");
			continue;
		}

		hose = &pcie_hose[i];
		hose->first_busno = bus;
		hose->last_busno = bus;
		hose->current_busno = bus;

		/* setup mem resource */
		pci_set_region(hose->regions + 0,
			       CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
			       CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
			       CONFIG_SYS_PCIE_MEMSIZE,
			       PCI_REGION_MEM);
		hose->region_count = 1;
		pci_register_hose(hose);

		if (is_end_point(i)) {
			ppc4xx_setup_pcie_endpoint(hose, i);
			/*
			 * Reson for no scanning is endpoint can not generate
			 * upstream configuration accesses.
			 */
		} else {
			ppc4xx_setup_pcie_rootpoint(hose, i);
			env = getenv ("pciscandelay");
			if (env != NULL) {
				delay = simple_strtoul(env, NULL, 10);
				if (delay > 5)
					printf("Warning, expect noticable delay before "
					       "PCIe scan due to 'pciscandelay' value!\n");
				mdelay(delay * 1000);
			}

			/*
			 * Config access can only go down stream
			 */
			hose->last_busno = pci_hose_scan(hose);
			bus = hose->last_busno + 1;
		}
	}
}
Beispiel #12
0
void init_octeon_pcie(void)
{
	int first_busno;
	int i;
	int rc = 0;
	int node = cvmx_get_node_num();
	struct pci_controller *hose;
	int pcie_port;

	first_busno = OCTEON_FIRST_PCIE_BUSNO;
	memset(&hose_pcie[0], 0, sizeof(hose_pcie[0]) * num_pcie_ports);

	debug("Starting PCIE on node %d\n", node);

	for (i = 0; i < num_pcie_ports; i++) {
		pcie_port = ((node << 4) | i);

		rc = cvmx_pcie_rc_initialize(pcie_port);

		if (rc != 0)
			continue;

		mdelay(1000);	/* Should delay 1 second according to standard */

		hose = &hose_pcie[i];
		hose->priv_data = (void *)&oct_pcie_data[i];
		oct_pcie_data[i].pcie_port = pcie_port;;

		hose->config_table = pci_board_config_table;

		hose->first_busno = first_busno;
		hose->last_busno = 0xff;

		/* PCI I/O space (Sub-DID == 2) */
		pci_set_region(hose->regions + 0,
			       octeon_pcie_region_info[i].io_base,
			       octeon_pcie_region_info[i].io_base,
			       octeon_pcie_region_info[i].io_size,
			       PCI_REGION_IO);
		/* PCI memory space (Sub-DID == 3) */
		pci_set_region(hose->regions + 1,
			       octeon_pcie_region_info[i].mem_base,
			       octeon_pcie_region_info[i].mem_base,
			       octeon_pcie_region_info[i].mem_size,
			       PCI_REGION_MEM);

		hose->region_count = 2;

		pci_set_ops(hose,
			    octeon_pcie_read_config_byte,
			    octeon_pcie_read_config_word,
			    octeon_pcie_read_config_dword,
			    octeon_pcie_write_config_byte,
			    octeon_pcie_write_config_word,
			    octeon_pcie_write_config_dword);

		pci_register_hose(hose);

		hose->last_busno = pci_hose_scan(hose);

		debug("PCIe: port=%d, first_bus=%d, last_bus=%d,\n\t"
		      "mem_base=0x%x, mem_size=0x%x, io_base=0x%x, io_size=0x%x\n",
		      octeon_get_pcie_port(hose),
		      hose->first_busno, hose->last_busno,
		      octeon_pcie_region_info[i].mem_base,
		      octeon_pcie_region_info[i].mem_size,
		      octeon_pcie_region_info[i].io_base,
		      octeon_pcie_region_info[i].io_size);

		first_busno = hose->last_busno + 1;
#if CONFIG_OCTEON_PCI_ENABLE_32BIT_MAPPING
		if (OCTEON_IS_OCTEON2() || OCTEON_IS_OCTEON3()) {
			cvmx_pemx_bar_ctl_t bar_ctl;
			cvmx_pemx_bar1_indexx_t pemx_bar1_indexx;
			uint64_t bar_base;
			int j;
			/* Setup BAR1 to map bus address 0x0 to the base of
			 * u-boot's TLB mapping.  This allows us to have u-boot
			 * located anywhere in memory (including above 32 bit
			 * addressable space) and still have 32 bit PCI devices
			 * have access to memory that is statically allocated
			 * or malloced by u-boot, both of which are TLB mapped.
			 */
			cvmx_write_csr_node(node, CVMX_PEMX_P2N_BAR1_START(i), 0);

			/* Disable bar0/bar2, as we are not using them here */
			cvmx_write_csr_node(node, CVMX_PEMX_P2N_BAR0_START(i), -1);
			cvmx_write_csr_node(node, CVMX_PEMX_P2N_BAR2_START(i), -1);

			/* Select 64 MByte mapping size for bar 1 on
			 * all ports
			 */
			bar_ctl.u64 = cvmx_read_csr_node(node, CVMX_PEMX_BAR_CTL(i));
			bar_ctl.s.bar1_siz = 1;	/* 64MB */
			bar_ctl.s.bar2_enb = 0;
			cvmx_write_csr_node(node, CVMX_PEMX_BAR_CTL(i), bar_ctl.u64);
			/* Configure the regions in bar 1 to map to the
			 * DRAM used by u-boot.
			 */
			/* Round down to 4MByte boundary to meet BAR mapping
			 * requirements
			 */
			bar_base = gd->bd->bi_uboot_ram_addr & ~0x3fffffull;

			debug("pcie: port %d, setting BAR base to 0x%llx\n",
			      i, bar_base);

			pemx_bar1_indexx.u64 = 0;
			pemx_bar1_indexx.s.addr_v = 1;
			pemx_bar1_indexx.s.end_swp = 1;
			pemx_bar1_indexx.s.ca = 1;

			for (j = 0; j < 16; j++) {
				pemx_bar1_indexx.s.addr_idx =
					(bar_base + 4 * 1024 * 1024 * j) >> 22;
				cvmx_write64_uint64(CVMX_PEMX_BAR1_INDEXX(j, i),
						    pemx_bar1_indexx.u64);
			}
		}
#endif /* CONFIG_OCTEON_PCI_ENABLE_32BIT_MAPPING */
	}
void pci_init_board(void)
{
	int mem_target, mem_attr, i;
	int bus = 0;
	u32 reg;
	u32 soc_ctrl = readl(MVEBU_SYSTEM_REG_BASE + 0x4);

	/* Check SoC Control Power State */
	debug("%s: SoC Control %08x, 0en %01lx, 1en %01lx, 2en %01lx\n",
	      __func__, soc_ctrl, SELECT(soc_ctrl, 0), SELECT(soc_ctrl, 1),
	      SELECT(soc_ctrl, 2));

	for (i = 0; i < MAX_PEX; i++) {
		struct mvebu_pcie *pcie = &pcie_bus[i];
		struct pci_controller *hose = &pcie->hose;

		/* Get port number, lane number and memory target / attr */
		mvebu_get_port_lane(pcie, i, &mem_target, &mem_attr);

		/* Don't read at all from pci registers if port power is down */
		if (pcie->lane == 0 && SELECT(soc_ctrl, pcie->port) == 0) {
			i += 3;
			debug("%s: skipping port %d\n", __func__, pcie->port);
			continue;
		}

		pcie->base = (void __iomem *)PCIE_BASE(i);

		/* Check link and skip ports that have no link */
		if (!mvebu_pcie_link_up(pcie)) {
			debug("%s: PCIe %d.%d - down\n", __func__,
			      pcie->port, pcie->lane);
			continue;
		}
		debug("%s: PCIe %d.%d - up, base %08x\n", __func__,
		      pcie->port, pcie->lane, (u32)pcie->base);

		/* Read Id info and local bus/dev */
		debug("direct conf read %08x, local bus %d, local dev %d\n",
		      readl(pcie->base), mvebu_pcie_get_local_bus_nr(pcie),
		      mvebu_pcie_get_local_dev_nr(pcie));

		mvebu_pcie_set_local_bus_nr(pcie, bus);
		mvebu_pcie_set_local_dev_nr(pcie, 0);
		pcie->dev = PCI_BDF(bus, 0, 0);

		pcie->mem.start = (u32)mvebu_pcie_membase;
		pcie->mem.end = pcie->mem.start + PCIE_MEM_SIZE - 1;
		mvebu_pcie_membase += PCIE_MEM_SIZE;

		if (mvebu_mbus_add_window_by_id(mem_target, mem_attr,
						(phys_addr_t)pcie->mem.start,
						PCIE_MEM_SIZE)) {
			printf("PCIe unable to add mbus window for mem at %08x+%08x\n",
			       (u32)pcie->mem.start, PCIE_MEM_SIZE);
		}

		/* Setup windows and configure host bridge */
		mvebu_pcie_setup_wins(pcie);

		/* Master + slave enable. */
		reg = readl(pcie->base + PCIE_CMD_OFF);
		reg |= PCI_COMMAND_MEMORY;
		reg |= PCI_COMMAND_MASTER;
		reg |= BIT(10);		/* disable interrupts */
		writel(reg, pcie->base + PCIE_CMD_OFF);

		/* Setup U-Boot PCI Controller */
		hose->first_busno = 0;
		hose->current_busno = bus;

		/* PCI memory space */
		pci_set_region(hose->regions + 0, pcie->mem.start,
			       pcie->mem.start, PCIE_MEM_SIZE, PCI_REGION_MEM);
		pci_set_region(hose->regions + 1,
			       0, 0,
			       gd->ram_size,
			       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
		hose->region_count = 2;

		pci_set_ops(hose,
			    pci_hose_read_config_byte_via_dword,
			    pci_hose_read_config_word_via_dword,
			    mvebu_pcie_read_config_dword,
			    pci_hose_write_config_byte_via_dword,
			    pci_hose_write_config_word_via_dword,
			    mvebu_pcie_write_config_dword);
		pci_register_hose(hose);

		hose->last_busno = pci_hose_scan(hose);

		/* Set BAR0 to internal registers */
		writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0));
		writel(0, pcie->base + PCIE_BAR_HI_OFF(0));

		bus = hose->last_busno + 1;
	}
}
Beispiel #14
0
void pci_init_board(void)
{
    struct pci_controller* hose = (struct pci_controller *)&local_hose;
    u32 reg32;
    u16 reg16;

    hose->first_busno = 0;
    hose->last_busno = 0xff;

    pci_set_region(hose->regions + 0,
	CFG_PCI_MEMORY_BUS,
	CFG_PCI_MEMORY_PHYS,
    /*
    * Attention: pci_hose_phys_to_bus() failes in address compare,
    * so we need (CFG_PCI_MEMORY_SIZE-1)
    */
	CFG_PCI_MEMORY_SIZE-1,
	PCI_REGION_MEM | PCI_REGION_MEMORY);

    /* PCI memory space */
    pci_set_region(hose->regions + 1,
	CFG_PCI_MEM_BUS,
	CFG_PCI_MEM_PHYS,
	CFG_PCI_MEM_SIZE,
	PCI_REGION_MEM);

    /* ISA/PCI memory space */
    pci_set_region(hose->regions + 2,
	CFG_ISA_MEM_BUS,
	CFG_ISA_MEM_PHYS,
	CFG_ISA_MEM_SIZE,
	PCI_REGION_MEM);

    /* PCI I/O space */
    pci_set_region(hose->regions + 3,
	CFG_PCI_IO_BUS,
	CFG_PCI_IO_PHYS,
	CFG_PCI_IO_SIZE,
	PCI_REGION_IO);

    /* ISA/PCI I/O space */
    pci_set_region(hose->regions + 4,
	CFG_ISA_IO_BUS,
	CFG_ISA_IO_PHYS,
	CFG_ISA_IO_SIZE,
	PCI_REGION_IO);

    hose->region_count = 5;

    pci_setup_indirect(hose,
	MPC106_REG_ADDR,
	MPC106_REG_DATA);

    pci_register_hose(hose);

    hose->last_busno = pci_hose_scan(hose);

    /* Initialises the MPC10x PCI Configuration regs. */
    pci_read_config_dword (PCI_BDF(0,0,0), PCI_PICR2, &reg32);
    reg32 |= PICR2_CF_SNOOP_WS(3) |
	     PICR2_CF_FLUSH_L2 |
	     PICR2_CF_L2_HIT_DELAY(3) |
	     PICR2_CF_APHASE_WS(3);
    reg32 &= ~(PICR2_L2_EN | PICR2_L2_UPDATE_EN);
    pci_write_config_dword (PCI_BDF(0,0,0), PCI_PICR2, reg32);

    pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
    reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
    pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);

    /* Clear non-reserved bits in status register */
    pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);

    pci_read_config_dword (PCI_BDF(0,0,0), PCI_PICR1, &reg32);
    reg32 |= PICR1_CF_CBA(63) |
	     PICR1_CF_BREAD_WS(2) |
	     PICR1_MCP_EN |
	     PICR1_CF_DPARK |
	     PICR1_PROC_TYPE_604 |
	     PICR1_CF_LOOP_SNOOP |
	     PICR1_CF_APARK;
    pci_write_config_dword (PCI_BDF(0,0,0), PCI_PICR1, reg32);
}
/**************************************************************************
 * pci_init_board()
 *
 */
void
pci_init_board(void)
{
	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
	volatile law512x_t *pci_law;
	volatile pot512x_t *pci_pot;
	volatile pcictrl512x_t *pci_ctrl;
	volatile pciconf512x_t *pci_conf;
	u16 reg16;
	u32 reg32;
	u32 dev;
	int i;
	struct pci_controller *hose;

	/* Set PCI divider for 33MHz */
	reg32 = in_be32(&im->clk.scfr[0]);
	reg32 &= ~(SCFR1_PCI_DIV_MASK);
	reg32 |= SCFR1_PCI_DIV << SCFR1_PCI_DIV_SHIFT;
	out_be32(&im->clk.scfr[0], reg32);

	clrsetbits_be32(&im->clk.scfr[0],
			SCFR1_PCI_DIV_MASK,
			SCFR1_PCI_DIV << SCFR1_PCI_DIV_SHIFT
	);

	pci_law = im->sysconf.pcilaw;
	pci_pot = im->ios.pot;
	pci_ctrl = &im->pci_ctrl;
	pci_conf = &im->pci_conf;

	hose = &pci_hose;

	/*
	 * Release PCI RST Output signal
	 */
	out_be32(&pci_ctrl->gcr, 0);
	udelay(2000);
	out_be32(&pci_ctrl->gcr, 1);

	/* We need to wait at least a 1sec based on PCI specs */
	for (i = 0; i < 1000; i++)
		udelay(1000);

	/*
	 * Configure PCI Local Access Windows
	 */
	out_be32(&pci_law[0].bar, CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR);
	out_be32(&pci_law[0].ar, LAWAR_EN | LAWAR_SIZE_512M);

	out_be32(&pci_law[1].bar, CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR);
	out_be32(&pci_law[1].ar, LAWAR_EN | LAWAR_SIZE_16M);

	/*
	 * Configure PCI Outbound Translation Windows
	 */

	/* PCI mem space - prefetch */
	out_be32(&pci_pot[0].potar,
		(CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK);
	out_be32(&pci_pot[0].pobar,
		(CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK);
	out_be32(&pci_pot[0].pocmr,
		POCMR_EN | POCMR_PRE | POCMR_CM_256M);

	/* PCI IO space */
	out_be32(&pci_pot[1].potar,
		(CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK);
	out_be32(&pci_pot[1].pobar,
		(CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK);
	out_be32(&pci_pot[1].pocmr,
		POCMR_EN | POCMR_IO | POCMR_CM_16M);

	/* PCI mmio - non-prefetch mem space */
	out_be32(&pci_pot[2].potar,
		(CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK);
	out_be32(&pci_pot[2].pobar,
		(CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK);
	out_be32(&pci_pot[2].pocmr,
		POCMR_EN | POCMR_CM_256M);

	/*
	 * Configure PCI Inbound Translation Windows
	 */

	/* we need RAM mapped to PCI space for the devices to
	 * access main memory */
	out_be32(&pci_ctrl[0].pitar1, 0x0);
	out_be32(&pci_ctrl[0].pibar1, 0x0);
	out_be32(&pci_ctrl[0].piebar1, 0x0);
	out_be32(&pci_ctrl[0].piwar1,
		PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
		PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1));

	hose->first_busno = 0;
	hose->last_busno = 0xff;

	/* PCI memory prefetch space */
	pci_set_region(hose->regions + 0,
		       CONFIG_SYS_PCI_MEM_BASE,
		       CONFIG_SYS_PCI_MEM_PHYS,
		       CONFIG_SYS_PCI_MEM_SIZE,
		       PCI_REGION_MEM|PCI_REGION_PREFETCH);

	/* PCI memory space */
	pci_set_region(hose->regions + 1,
		       CONFIG_SYS_PCI_MMIO_BASE,
		       CONFIG_SYS_PCI_MMIO_PHYS,
		       CONFIG_SYS_PCI_MMIO_SIZE,
		       PCI_REGION_MEM);

	/* PCI IO space */
	pci_set_region(hose->regions + 2,
		       CONFIG_SYS_PCI_IO_BASE,
		       CONFIG_SYS_PCI_IO_PHYS,
		       CONFIG_SYS_PCI_IO_SIZE,
		       PCI_REGION_IO);

	/* System memory space */
	pci_set_region(hose->regions + 3,
		       CONFIG_PCI_SYS_MEM_BUS,
		       CONFIG_PCI_SYS_MEM_PHYS,
		       gd->ram_size,
		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);

	hose->region_count = 4;

	pci_setup_indirect(hose,
			   (CONFIG_SYS_IMMR + 0x8300),
			   (CONFIG_SYS_IMMR + 0x8304));

	pci_register_hose(hose);

	/*
	 * Write to Command register
	 */
	reg16 = 0xff;
	dev = PCI_BDF(hose->first_busno, 0, 0);
	pci_hose_read_config_word(hose, dev, PCI_COMMAND, &reg16);
	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
	pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);

	/*
	 * Clear non-reserved bits in status register.
	 */
	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);

#ifdef CONFIG_PCI_SCAN_SHOW
	printf("PCI:   Bus Dev VenId DevId Class Int\n");
#endif
	/*
	 * Hose scan.
	 */
	hose->last_busno = pci_hose_scan(hose);
}
Beispiel #16
0
/**************************************************************************
 * pci_init_board()
 *
 * NOTICE: PCI2 is not supported. There is only one
 * physical PCI slot on the board.
 *
 */
void
pci_init_board(void)
{
	volatile immap_t *	immr;
	volatile clk83xx_t *	clk;
	volatile law83xx_t *	pci_law;
	volatile pot83xx_t *	pci_pot;
	volatile pcictrl83xx_t *	pci_ctrl;
	volatile pciconf83xx_t *	pci_conf;
	u16 reg16;
	u32 reg32;
	u32 dev;
	struct	pci_controller * hose;

	immr = (immap_t *)CONFIG_SYS_IMMR;
	clk = (clk83xx_t *)&immr->clk;
	pci_law = immr->sysconf.pcilaw;
	pci_pot = immr->ios.pot;
	pci_ctrl = immr->pci_ctrl;
	pci_conf = immr->pci_conf;

	hose = &pci_hose[0];

	/*
	 * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
	 */

	reg32 = clk->occr;
	udelay(2000);
	clk->occr = 0xff000000;
	udelay(2000);

	/*
	 * Release PCI RST Output signal
	 */
	pci_ctrl[0].gcr = 0;
	udelay(2000);
	pci_ctrl[0].gcr = 1;

#ifdef CONFIG_MPC83XX_PCI2
	pci_ctrl[1].gcr = 0;
	udelay(2000);
	pci_ctrl[1].gcr = 1;
#endif

	/* We need to wait at least a 1sec based on PCI specs */
	{
		int i;

		for (i = 0; i < 1000; ++i)
			udelay (1000);
	}

	/*
	 * Configure PCI Local Access Windows
	 */
	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;

	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;

	/*
	 * Configure PCI Outbound Translation Windows
	 */

	/* PCI1 mem space - prefetch */
	pci_pot[0].potar = (CONFIG_SYS_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
	pci_pot[0].pobar = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
	pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);

	/* PCI1 IO space */
	pci_pot[1].potar = (CONFIG_SYS_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
	pci_pot[1].pobar = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
	pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);

	/* PCI1 mmio - non-prefetch mem space */
	pci_pot[2].potar = (CONFIG_SYS_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK;
	pci_pot[2].pobar = (CONFIG_SYS_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK;
	pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK);

	/*
	 * Configure PCI Inbound Translation Windows
	 */

	/* we need RAM mapped to PCI space for the devices to
	 * access main memory */
	pci_ctrl[0].pitar1 = 0x0;
	pci_ctrl[0].pibar1 = 0x0;
	pci_ctrl[0].piebar1 = 0x0;
	pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);

	hose->first_busno = 0;
	hose->last_busno = 0xff;

	/* PCI memory prefetch space */
	pci_set_region(hose->regions + 0,
		       CONFIG_SYS_PCI1_MEM_BASE,
		       CONFIG_SYS_PCI1_MEM_PHYS,
		       CONFIG_SYS_PCI1_MEM_SIZE,
		       PCI_REGION_MEM|PCI_REGION_PREFETCH);

	/* PCI memory space */
	pci_set_region(hose->regions + 1,
		       CONFIG_SYS_PCI1_MMIO_BASE,
		       CONFIG_SYS_PCI1_MMIO_PHYS,
		       CONFIG_SYS_PCI1_MMIO_SIZE,
		       PCI_REGION_MEM);

	/* PCI IO space */
	pci_set_region(hose->regions + 2,
		       CONFIG_SYS_PCI1_IO_BASE,
		       CONFIG_SYS_PCI1_IO_PHYS,
		       CONFIG_SYS_PCI1_IO_SIZE,
		       PCI_REGION_IO);

	/* System memory space */
	pci_set_region(hose->regions + 3,
		       CONFIG_PCI_SYS_MEM_BUS,
		       CONFIG_PCI_SYS_MEM_PHYS,
		       gd->ram_size,
		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);

	hose->region_count = 4;

	pci_setup_indirect(hose,
			   (CONFIG_SYS_IMMR+0x8300),
			   (CONFIG_SYS_IMMR+0x8304));

	pci_register_hose(hose);

	/*
	 * Write to Command register
	 */
	reg16 = 0xff;
	dev = PCI_BDF(hose->first_busno, 0, 0);
	pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
	pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);

	/*
	 * Clear non-reserved bits in status register.
	 */
	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);

#ifdef CONFIG_PCI_SCAN_SHOW
	printf("PCI:   Bus Dev VenId DevId Class Int\n");
#endif
	/*
	 * Hose scan.
	 */
	hose->last_busno = pci_hose_scan(hose);

#ifdef CONFIG_MPC83XX_PCI2
	hose = &pci_hose[1];

	/*
	 * Configure PCI Outbound Translation Windows
	 */

	/* PCI2 mem space - prefetch */
	pci_pot[3].potar = (CONFIG_SYS_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
	pci_pot[3].pobar = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
	pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);

	/* PCI2 IO space */
	pci_pot[4].potar = (CONFIG_SYS_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
	pci_pot[4].pobar = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
	pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);

	/* PCI2 mmio - non-prefetch mem space */
	pci_pot[5].potar = (CONFIG_SYS_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK;
	pci_pot[5].pobar = (CONFIG_SYS_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK;
	pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK);

	/*
	 * Configure PCI Inbound Translation Windows
	 */

	/* we need RAM mapped to PCI space for the devices to
	 * access main memory */
	pci_ctrl[1].pitar1 = 0x0;
	pci_ctrl[1].pibar1 = 0x0;
	pci_ctrl[1].piebar1 = 0x0;
	pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);

	hose->first_busno = pci_hose[0].last_busno + 1;
	hose->last_busno = 0xff;

	/* PCI memory prefetch space */
	pci_set_region(hose->regions + 0,
		       CONFIG_SYS_PCI2_MEM_BASE,
		       CONFIG_SYS_PCI2_MEM_PHYS,
		       CONFIG_SYS_PCI2_MEM_SIZE,
		       PCI_REGION_MEM|PCI_REGION_PREFETCH);

	/* PCI memory space */
	pci_set_region(hose->regions + 1,
		       CONFIG_SYS_PCI2_MMIO_BASE,
		       CONFIG_SYS_PCI2_MMIO_PHYS,
		       CONFIG_SYS_PCI2_MMIO_SIZE,
		       PCI_REGION_MEM);

	/* PCI IO space */
	pci_set_region(hose->regions + 2,
		       CONFIG_SYS_PCI2_IO_BASE,
		       CONFIG_SYS_PCI2_IO_PHYS,
		       CONFIG_SYS_PCI2_IO_SIZE,
		       PCI_REGION_IO);

	/* System memory space */
	pci_set_region(hose->regions + 3,
		       CONFIG_PCI_SYS_MEM_BUS,
		       CONFIG_PCI_SYS_MEM_PHYS,
		       gd->ram_size,
		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);

	hose->region_count = 4;

	pci_setup_indirect(hose,
			   (CONFIG_SYS_IMMR+0x8380),
			   (CONFIG_SYS_IMMR+0x8384));

	pci_register_hose(hose);

	/*
	 * Write to Command register
	 */
	reg16 = 0xff;
	dev = PCI_BDF(hose->first_busno, 0, 0);
	pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
	pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);

	/*
	 * Clear non-reserved bits in status register.
	 */
	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);

	/*
	 * Hose scan.
	 */
	hose->last_busno = pci_hose_scan(hose);
#endif

}
Beispiel #17
0
void pci_mcf547x_8x_init(struct pci_controller *hose)
{
	volatile pci_t *pci = (volatile pci_t *) MMAP_PCI;
	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;

	/* Port configuration */
	gpio->par_pcibg =
	    GPIO_PAR_PCIBG_PCIBG0(3) | GPIO_PAR_PCIBG_PCIBG1(3) |
	    GPIO_PAR_PCIBG_PCIBG2(3) | GPIO_PAR_PCIBG_PCIBG3(3) |
	    GPIO_PAR_PCIBG_PCIBG4(3);
	gpio->par_pcibr =
	    GPIO_PAR_PCIBR_PCIBR0(3) | GPIO_PAR_PCIBR_PCIBR1(3) |
	    GPIO_PAR_PCIBR_PCIBR2(3) | GPIO_PAR_PCIBR_PCIBR3(3) |
	    GPIO_PAR_PCIBR_PCIBR4(3);

	/* Assert reset bit */
	pci->gscr |= PCI_GSCR_PR;

	pci->tcr1 = PCI_TCR1_P;

	/* Initiator windows */
	pci->iw0btar = CFG_PCI_MEM_PHYS | (CFG_PCI_MEM_PHYS >> 16);
	pci->iw1btar = CFG_PCI_IO_PHYS | (CFG_PCI_IO_PHYS >> 16);
	pci->iw2btar = CFG_PCI_CFG_PHYS | (CFG_PCI_CFG_PHYS >> 16);

	pci->iwcr =
	    PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
	    PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO;

	pci->icr = 0;

	/* Enable bus master and mem access */
	pci->scr = PCI_SCR_B | PCI_SCR_M;

	/* Cache line size and master latency */
	pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8);
	pci->cr2 = 0;

#ifdef CFG_PCI_BAR0
	pci->bar0 = PCI_BAR_BAR0(CFG_PCI_BAR0);
	pci->tbatr0a = CFG_PCI_TBATR0 | PCI_TBATR_EN;
#endif
#ifdef CFG_PCI_BAR1
	pci->bar1 = PCI_BAR_BAR1(CFG_PCI_BAR1);
	pci->tbatr1a = CFG_PCI_TBATR1 | PCI_TBATR_EN;
#endif

	/* Deassert reset bit */
	pci->gscr &= ~PCI_GSCR_PR;
	udelay(1000);

	/* Enable PCI bus master support */
	hose->first_busno = 0;
	hose->last_busno = 0xff;

	pci_set_region(hose->regions + 0, CFG_PCI_MEM_BUS, CFG_PCI_MEM_PHYS,
		       CFG_PCI_MEM_SIZE, PCI_REGION_MEM);

	pci_set_region(hose->regions + 1, CFG_PCI_IO_BUS, CFG_PCI_IO_PHYS,
		       CFG_PCI_IO_SIZE, PCI_REGION_IO);

	pci_set_region(hose->regions + 2, CFG_PCI_SYS_MEM_BUS,
		       CFG_PCI_SYS_MEM_PHYS, CFG_PCI_SYS_MEM_SIZE,
		       PCI_REGION_MEM | PCI_REGION_MEMORY);

	hose->region_count = 3;

	hose->cfg_addr = &(pci->car);
	hose->cfg_data = (volatile unsigned char *)CFG_PCI_CFG_BUS;

	pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word,
		    pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word,
		    pci_write_cfg_dword);

	/* Hose scan */
	pci_register_hose(hose);
	hose->last_busno = pci_hose_scan(hose);
}
Beispiel #18
0
void
pci_mpc85xx_init(struct pci_controller *hose)
{
	volatile immap_t    *immap = (immap_t *)CFG_CCSRBAR;
	volatile ccsr_pcix_t *pcix = &immap->im_pcix;

	u16 reg16;

	hose->first_busno = 0;
	hose->last_busno = 0xff;

	pci_set_region(hose->regions + 0,
		       CFG_PCI1_MEM_BASE,
		       CFG_PCI1_MEM_PHYS,
		       CFG_PCI1_MEM_SIZE,
		       PCI_REGION_MEM);

	pci_set_region(hose->regions + 1,
		       CFG_PCI1_IO_BASE,
		       CFG_PCI1_IO_PHYS,
		       CFG_PCI1_IO_SIZE,
		       PCI_REGION_IO);

	hose->region_count = 2;

	pci_setup_indirect(hose,
			   (CFG_IMMR+0x8000),
			   (CFG_IMMR+0x8004));

	pcix->potar1   = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
	pcix->potear1  = 0x00000000;
	pcix->powbar1  = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
	pcix->powbear1 = 0x00000000;
	pcix->powar1   = 0x8004401c;	/* 512M MEM space */

	pcix->potar2   = 0x00000000;
	pcix->potear2  = 0x00000000;
	pcix->powbar2  = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
	pcix->powbear2 = 0x00000000;
	pcix->powar2   = 0x80088017;	/* 16M IO space */

	pcix->pitar1 = 0x00000000;
	pcix->piwbar1 = 0x00000000;
	pcix->piwar1 = 0xa0f5501e;	/* Enable, Prefetch, Local Mem,
					 * Snoop R/W, 2G */

	/*
	 * Hose scan.
	 */
	pci_register_hose(hose);

	pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
	pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);

	/*
	 * Clear non-reserved bits in status register.
	 */
	pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
	pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);

#if defined(CONFIG_MPC8555CDS) || defined(CONFIG_MPC8541CDS)
	/*
	 * This is a SW workaround for an apparent HW problem
	 * in the PCI controller on the MPC85555/41 CDS boards.
	 * The first config cycle must be to a valid, known
	 * device on the PCI bus in order to trick the PCI
	 * controller state machine into a known valid state.
	 * Without this, the first config cycle has the chance
	 * of hanging the controller permanently, just leaving
	 * it in a semi-working state, or leaving it working.
	 *
	 * Pick on the Tundra, Device 17, to get it right.
	 */
	{
		u8 header_type;

		pci_hose_read_config_byte(hose,
					  PCI_BDF(0,17,0),
					  PCI_HEADER_TYPE,
					  &header_type);
	}
#endif

	hose->last_busno = pci_hose_scan(hose);
}
void pcie_setup_hoses(int busno)
{
	struct pci_controller *hose;
	int i, bus;
	char *env;
	unsigned int delay;

	/*
	 * assume we're called after the PCIX hose is initialized, which takes
	 * bus ID 0 and therefore start numbering PCIe's from 1.
	 */
	bus = busno;
	for (i = 0; i <= 2; i++) {
		/* Check for yucca card presence */
		if (!yucca_pcie_card_present(i))
			continue;

#ifdef PCIE_ENDPOINT
 		yucca_setup_pcie_fpga_endpoint(i);
 		if (ppc440spe_init_pcie_endport(i)) {
#else
		yucca_setup_pcie_fpga_rootpoint(i);
		if (ppc440spe_init_pcie_rootport(i)) {
#endif
			printf("PCIE%d: initialization failed\n", i);
			continue;
		}

		hose = &pcie_hose[i];
		hose->first_busno = bus;
		hose->last_busno = bus;
		hose->current_busno = bus;

		/* setup mem resource */
		pci_set_region(hose->regions + 0,
			CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
			CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
			CFG_PCIE_MEMSIZE,
			PCI_REGION_MEM
			);
		hose->region_count = 1;
		pci_register_hose(hose);

#ifdef PCIE_ENDPOINT
		ppc440spe_setup_pcie_endpoint(hose, i);
		/*
		 * Reson for no scanning is endpoint can not generate
		 * upstream configuration accesses.
		 */
#else
		ppc440spe_setup_pcie_rootpoint(hose, i);

		env = getenv ("pciscandelay");
		if (env != NULL) {
			delay = simple_strtoul (env, NULL, 10);
			if (delay > 5)
				printf ("Warning, expect noticable delay before PCIe"
					"scan due to 'pciscandelay' value!\n");
			mdelay (delay * 1000);
		}

		/*
		 * Config access can only go down stream
		 */
		hose->last_busno = pci_hose_scan(hose);
		bus = hose->last_busno + 1;
#endif
	}
}
#endif	/* defined(CONFIG_PCI) */

int misc_init_f (void)
{
	uint reg;
#if defined(CONFIG_STRESS)
	uint i ;
	uint disp;
#endif

	out16(FPGA_REG10, (in16(FPGA_REG10) &
			~(FPGA_REG10_AUTO_NEG_DIS|FPGA_REG10_RESET_ETH)) |
				FPGA_REG10_10MHZ_ENABLE |
				FPGA_REG10_100MHZ_ENABLE |
				FPGA_REG10_GIGABIT_ENABLE |
				FPGA_REG10_FULL_DUPLEX );

	udelay(10000);	/* wait 10ms */

	out16(FPGA_REG10, (in16(FPGA_REG10) | FPGA_REG10_RESET_ETH));

	/* minimal init for PCIe */
	/* pci express 0 Endpoint Mode */
	mfsdr(SDR0_PE0DLPSET, reg);
	reg &= (~0x00400000);
	mtsdr(SDR0_PE0DLPSET, reg);
	/* pci express 1 Rootpoint  Mode */
	mfsdr(SDR0_PE1DLPSET, reg);
	reg |= 0x00400000;
	mtsdr(SDR0_PE1DLPSET, reg);
	/* pci express 2 Rootpoint  Mode */
	mfsdr(SDR0_PE2DLPSET, reg);
	reg |= 0x00400000;
	mtsdr(SDR0_PE2DLPSET, reg);

	out16(FPGA_REG1C,(in16 (FPGA_REG1C) &
				~FPGA_REG1C_PE0_ROOTPOINT &
				~FPGA_REG1C_PE1_ENDPOINT  &
				~FPGA_REG1C_PE2_ENDPOINT));

#if defined(CONFIG_STRESS)
	/*
	 * all this setting done by linux only needed by stress an charac. test
	 * procedure
	 * PCIe 1 Rootpoint PCIe2 Endpoint
	 * PCIe 0 FIR Pre-emphasis Filter Coefficients & Transmit Driver
	 * Power Level
	 */
	for (i = 0, disp = 0; i < 8; i++, disp += 3) {
		mfsdr(SDR0_PE0HSSSET1L0 + disp, reg);
		reg |= 0x33000000;
		mtsdr(SDR0_PE0HSSSET1L0 + disp, reg);
	}

	/*
	 * PCIe 1 FIR Pre-emphasis Filter Coefficients & Transmit Driver
	 * Power Level
	 */
	for (i = 0, disp = 0; i < 4; i++, disp += 3) {
		mfsdr(SDR0_PE1HSSSET1L0 + disp, reg);
		reg |= 0x33000000;
		mtsdr(SDR0_PE1HSSSET1L0 + disp, reg);
	}

	/*
	 * PCIE 2 FIR Pre-emphasis Filter Coefficients & Transmit Driver
	 * Power Level
	 */
	for (i = 0, disp = 0; i < 4; i++, disp += 3) {
		mfsdr(SDR0_PE2HSSSET1L0 + disp, reg);
		reg |= 0x33000000;
		mtsdr(SDR0_PE2HSSSET1L0 + disp, reg);
	}

	reg = 0x21242222;
	mtsdr(SDR0_PE2UTLSET1, reg);
	reg = 0x11000000;
	mtsdr(SDR0_PE2UTLSET2, reg);
	/* pci express 1 Endpoint  Mode */
	reg = 0x00004000;
	mtsdr(SDR0_PE2DLPSET, reg);

	mtsdr(SDR0_UART1, 0x2080005a);	/* patch for TG */
#endif
	return 0;
}
Beispiel #20
0
void pci_mcf5445x_init(struct pci_controller *hose)
{
	volatile pci_t *pci = (volatile pci_t *)MMAP_PCI;
	volatile pciarb_t *pciarb = (volatile pciarb_t *)MMAP_PCIARB;
	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
	u32 barEn = 0;

	pciarb->acr = 0x001F001F;

	/* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT,
	   PCIREQ2, PCIGNT2 */
	gpio->par_pci =
	    GPIO_PAR_PCI_GNT3_GNT3 | GPIO_PAR_PCI_GNT2 | GPIO_PAR_PCI_GNT1 |
	    GPIO_PAR_PCI_GNT0 | GPIO_PAR_PCI_REQ3_REQ3 | GPIO_PAR_PCI_REQ2 |
	    GPIO_PAR_PCI_REQ1 | GPIO_PAR_PCI_REQ0;

	/* Assert reset bit */
	pci->gscr |= PCI_GSCR_PR;

	pci->tcr1 |= PCI_TCR1_P;

	/* Initiator windows */
	pci->iw0btar = CFG_PCI_MEM_PHYS | (CFG_PCI_MEM_PHYS >> 16);
	pci->iw1btar = CFG_PCI_IO_PHYS | (CFG_PCI_IO_PHYS >> 16);
	pci->iw2btar = CFG_PCI_CFG_PHYS | (CFG_PCI_CFG_PHYS >> 16);

	pci->iwcr =
	    PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
	    PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO;

	pci->icr = 0;

	/* Enable bus master and mem access */
	pci->scr = PCI_SCR_B | PCI_SCR_M;

	/* Cache line size and master latency */
	pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8);
	pci->cr2 = 0;

#ifdef CFG_PCI_BAR0
	pci->bar0 = PCI_BAR_BAR0(CFG_PCI_BAR0);
	pci->tbatr0 = CFG_PCI_TBATR0 | PCI_TBATR_EN;
	barEn |= PCI_TCR2_B0E;
#endif
#ifdef CFG_PCI_BAR1
	pci->bar1 = PCI_BAR_BAR1(CFG_PCI_BAR1);
	pci->tbatr1 = CFG_PCI_TBATR1 | PCI_TBATR_EN;
	barEn |= PCI_TCR2_B1E;
#endif
#ifdef CFG_PCI_BAR2
	pci->bar2 = PCI_BAR_BAR2(CFG_PCI_BAR2);
	pci->tbatr2 = CFG_PCI_TBATR2 | PCI_TBATR_EN;
	barEn |= PCI_TCR2_B2E;
#endif
#ifdef CFG_PCI_BAR3
	pci->bar3 = PCI_BAR_BAR3(CFG_PCI_BAR3);
	pci->tbatr3 = CFG_PCI_TBATR3 | PCI_TBATR_EN;
	barEn |= PCI_TCR2_B3E;
#endif
#ifdef CFG_PCI_BAR4
	pci->bar4 = PCI_BAR_BAR4(CFG_PCI_BAR4);
	pci->tbatr4 = CFG_PCI_TBATR4 | PCI_TBATR_EN;
	barEn |= PCI_TCR2_B4E;
#endif
#ifdef CFG_PCI_BAR5
	pci->bar5 = PCI_BAR_BAR5(CFG_PCI_BAR5);
	pci->tbatr5 = CFG_PCI_TBATR5 | PCI_TBATR_EN;
	barEn |= PCI_TCR2_B5E;
#endif

	pci->tcr2 = barEn;

	/* Deassert reset bit */
	pci->gscr &= ~PCI_GSCR_PR;
	udelay(1000);

	/* Enable PCI bus master support */
	hose->first_busno = 0;
	hose->last_busno = 0xff;

	pci_set_region(hose->regions + 0, CFG_PCI_MEM_BUS, CFG_PCI_MEM_PHYS,
		       CFG_PCI_MEM_SIZE, PCI_REGION_MEM);

	pci_set_region(hose->regions + 1, CFG_PCI_IO_BUS, CFG_PCI_IO_PHYS,
		       CFG_PCI_IO_SIZE, PCI_REGION_IO);

	pci_set_region(hose->regions + 2, CFG_PCI_SYS_MEM_BUS,
		       CFG_PCI_SYS_MEM_PHYS, CFG_PCI_SYS_MEM_SIZE,
		       PCI_REGION_MEM | PCI_REGION_MEMORY);

	hose->region_count = 3;

	hose->cfg_addr = &(pci->car);
	hose->cfg_data = (volatile unsigned char *)CFG_PCI_CFG_BUS;

	pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word,
		    pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word,
		    pci_write_cfg_dword);

	/* Hose scan */
	pci_register_hose(hose);
	hose->last_busno = pci_hose_scan(hose);
}
Beispiel #21
0
void
pci_mpc83xx_init(volatile struct pci_controller *hose)
{
	volatile immap_t *	immr;
	volatile clk8349_t *	clk;
	volatile law8349_t *	pci_law;
	volatile pot8349_t *	pci_pot;
	volatile pcictrl8349_t *	pci_ctrl;
	volatile pciconf8349_t *	pci_conf;

	u8 val8,tmp8,ret;
	u16 reg16,tmp16;
	u32 val32,tmp32;

	immr = (immap_t *)CFG_IMMRBAR;
	clk = (clk8349_t *)&immr->clk;
	pci_law = immr->sysconf.pcilaw;
	pci_pot = immr->ios.pot;
	pci_ctrl = immr->pci_ctrl;
	pci_conf = immr->pci_conf;

	/*
	 * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
	 */
	val32 = clk->occr;
	udelay(2000);
	clk->occr = 0xff000000;
	udelay(2000);

	/*
	 * Configure PCI Local Access Windows
	 */
	pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
	pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;

	/*
	 * Configure PCI Outbound Translation Windows
	 */
	pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
	pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
	pci_pot[0].pocmr = POCMR_EN | (POCMR_CM_512M & POCMR_CM_MASK);

	/* mapped to PCI1 IO space 0x0 to local 0xe2000000  */
	pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
	pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
	pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);

	pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
	pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
	pci_pot[3].pocmr = POCMR_EN | POCMR_DST | (POCMR_CM_512M & POCMR_CM_MASK);

	/* mapped to PCI2 IO space 0x0 to local 0xe3000000  */
	pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
	pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
	pci_pot[4].pocmr = POCMR_EN | POCMR_DST | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);

	/*
	 * Configure PCI Inbound Translation Windows
	 */
	pci_ctrl[0].pitar1 = 0x0;
	pci_ctrl[0].pibar1 = 0x0;
	pci_ctrl[0].piebar1 = 0x0;
	pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G;

	pci_ctrl[1].pitar1 = 0x0;
	pci_ctrl[1].pibar1 = 0x0;
	pci_ctrl[1].piebar1 = 0x0;
	pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G;
	/*
	 * Assign PIB PMC slot to desired PCI bus
	 */
#ifdef CONFIG_MPC8349ADS
	mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C2_OFFSET);
	i2c_init(CFG_I2C_SPEED,CFG_I2C_SLAVE);
#endif
	val8 = 0;
	ret = i2c_write(0x23,0x6,1,&val8,1);
	ret = i2c_write(0x23,0x7,1,&val8,1);
	val8 = 0xff;
	ret = i2c_write(0x23,0x2,1,&val8,1);
	ret = i2c_write(0x23,0x3,1,&val8,1);

	val8 = 0;
	ret = i2c_write(0x26,0x6,1,&val8,1);
	val8 = 0x34;
	ret = i2c_write(0x26,0x7,1,&val8,1);
#if defined(PCI_64BIT)
	val8 = 0xf4;	/* PMC2<->PCI1  64bit */
#elif defined(PCI_ALL_PCI1)
	val8 = 0xf3;	/* PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI1  32bit */
#elif defined(PCI_ONE_PCI1)
	val8 = 0xf9;	/* PMC1<->PCI1,PMC2<->PCI2,PMC3<->PCI2  32bit */
#elif defined(PCI_TWO_PCI1)
	val8 = 0xf5;	/* PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI2 32bit */
#else
	val8 = 0xf5;
#endif
	ret = i2c_write(0x26,0x2,1,&val8,1);
	val8 = 0xff;
	ret = i2c_write(0x26,0x3,1,&val8,1);
	val8 = 0;
	ret = i2c_write(0x27,0x6,1,&val8,1);
	ret = i2c_write(0x27,0x7,1,&val8,1);
	val8 = 0xff;
	ret = i2c_write(0x27,0x2,1,&val8,1);
	val8 = 0xef;
	ret = i2c_write(0x27,0x3,1,&val8,1);
	asm("eieio");

	/*
	 * Release PCI RST Output signal
	 */
	udelay(2000);
	pci_ctrl[0].gcr = 1;
#ifndef PCI_64BIT
	pci_ctrl[1].gcr = 1;
#endif
	udelay(2000);

	hose[0].first_busno = 0;
	hose[0].last_busno = 0xff;

	pci_set_region(hose[0].regions + 0,
		       CFG_PCI1_MEM_BASE,
		       CFG_PCI1_MEM_PHYS,
		       CFG_PCI1_MEM_SIZE,
		       PCI_REGION_MEM);

	pci_set_region(hose[0].regions + 1,
		       CFG_PCI1_IO_BASE,
		       CFG_PCI1_IO_PHYS,
		       CFG_PCI1_IO_SIZE,
		       PCI_REGION_IO);

	hose[0].region_count = 2;

	pci_setup_indirect(&hose[0],
			   (CFG_IMMRBAR+0x8300),
			   (CFG_IMMRBAR+0x8304));
#define PCI_CLASS_BRIDGE	0x06
	reg16 = 0xff;
	tmp32 = 0xffff;
	pci_hose_write_config_byte(&hose[0],PCI_BDF(0,0,0),PCI_CLASS_CODE,PCI_CLASS_BRIDGE);

	pci_hose_read_config_word (&hose[0],PCI_BDF(0,0,0),PCI_COMMAND, &reg16);
	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
	pci_hose_write_config_word(&hose[0],PCI_BDF(0,0,0), PCI_COMMAND, reg16);

	/*
	 * Clear non-reserved bits in status register.
	 */
	pci_hose_write_config_word(&hose[0],PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
	pci_hose_write_config_byte(&hose[0],PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
#ifndef PCI_64BIT
	hose[1].first_busno = 0;
	hose[1].last_busno = 0xff;

	pci_set_region(hose[1].regions + 0,
		       CFG_PCI2_MEM_BASE,
		       CFG_PCI2_MEM_PHYS,
		       CFG_PCI2_MEM_SIZE,
		       PCI_REGION_MEM);

	pci_set_region(hose[1].regions + 1,
		       CFG_PCI2_IO_BASE,
		       CFG_PCI2_IO_PHYS,
		       CFG_PCI2_IO_SIZE,
		       PCI_REGION_IO);

	hose[1].region_count = 2;

	pci_setup_indirect(&hose[1],
			   (CFG_IMMRBAR+0x8380),
			   (CFG_IMMRBAR+0x8384));

	pci_hose_write_config_byte(&hose[1],PCI_BDF(0,0,0),PCI_CLASS_CODE,PCI_CLASS_BRIDGE);
	pci_hose_read_config_word (&hose[1],PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
	pci_hose_write_config_word(&hose[1],PCI_BDF(0,0,0), PCI_COMMAND, reg16);

	/*
	 * Clear non-reserved bits in status register.
	 */
	pci_hose_write_config_word(&hose[1],PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
	pci_hose_write_config_byte(&hose[1],PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
#endif

#if defined(PCI_64BIT)
	printf("PCI1 64bit on PMC2\n");
#elif defined(PCI_ALL_PCI1)
	printf("PCI1 32bit on PMC1 & PMC2 & PMC3\n");
#elif defined(PCI_ONE_PCI1)
	printf("PCI1 32bit on PMC1,PCI2 32bit on PMC2 & PMC3\n");
#else
	printf("PCI1 32bit on PMC1 & PMC2 & PMC3 in default\n");
#endif

#if 1
	/*
	 * Hose scan.
	 */
	pci_register_hose(hose);
	hose->last_busno = pci_hose_scan(hose);
#endif
}
Beispiel #22
0
void pci_mcf5445x_init(struct pci_controller *hose)
{
	pci_t *pci = (pci_t *)MMAP_PCI;
	pciarb_t *pciarb = (pciarb_t *)MMAP_PCIARB;
	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
	u32 barEn = 0;

	out_be32(&pciarb->acr, 0x001f001f);

	/* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT,
	   PCIREQ2, PCIGNT2 */
	out_be16(&gpio->par_pci,
		GPIO_PAR_PCI_GNT3_GNT3 | GPIO_PAR_PCI_GNT2 |
		GPIO_PAR_PCI_GNT1 | GPIO_PAR_PCI_GNT0 |
		GPIO_PAR_PCI_REQ3_REQ3 | GPIO_PAR_PCI_REQ2 |
		GPIO_PAR_PCI_REQ1 | GPIO_PAR_PCI_REQ0);

	/* Assert reset bit */
	setbits_be32(&pci->gscr, PCI_GSCR_PR);

	setbits_be32(&pci->tcr1, PCI_TCR1_P);

	/* Initiator windows */
	out_be32(&pci->iw0btar,
		CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16));
	out_be32(&pci->iw1btar,
		CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16));
	out_be32(&pci->iw2btar,
		CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16));

	out_be32(&pci->iwcr,
		PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
		PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO);

	out_be32(&pci->icr, 0);

	/* Enable bus master and mem access */
	out_be32(&pci->scr, PCI_SCR_B | PCI_SCR_M);

	/* Cache line size and master latency */
	out_be32(&pci->cr1, PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8));
	out_be32(&pci->cr2, 0);

#ifdef CONFIG_SYS_PCI_BAR0
	out_be32(&pci->bar0, PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0));
	out_be32(&pci->tbatr0, CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN);
	barEn |= PCI_TCR2_B0E;
#endif
#ifdef CONFIG_SYS_PCI_BAR1
	out_be32(&pci->bar1, PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1));
	out_be32(&pci->tbatr1, CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN);
	barEn |= PCI_TCR2_B1E;
#endif
#ifdef CONFIG_SYS_PCI_BAR2
	out_be32(&pci->bar2, PCI_BAR_BAR2(CONFIG_SYS_PCI_BAR2));
	out_be32(&pci->tbatr2, CONFIG_SYS_PCI_TBATR2 | PCI_TBATR_EN);
	barEn |= PCI_TCR2_B2E;
#endif
#ifdef CONFIG_SYS_PCI_BAR3
	out_be32(&pci->bar3, PCI_BAR_BAR3(CONFIG_SYS_PCI_BAR3));
	out_be32(&pci->tbatr3, CONFIG_SYS_PCI_TBATR3 | PCI_TBATR_EN);
	barEn |= PCI_TCR2_B3E;
#endif
#ifdef CONFIG_SYS_PCI_BAR4
	out_be32(&pci->bar4, PCI_BAR_BAR4(CONFIG_SYS_PCI_BAR4));
	out_be32(&pci->tbatr4, CONFIG_SYS_PCI_TBATR4 | PCI_TBATR_EN);
	barEn |= PCI_TCR2_B4E;
#endif
#ifdef CONFIG_SYS_PCI_BAR5
	out_be32(&pci->bar5, PCI_BAR_BAR5(CONFIG_SYS_PCI_BAR5));
	out_be32(&pci->tbatr5, CONFIG_SYS_PCI_TBATR5 | PCI_TBATR_EN);
	barEn |= PCI_TCR2_B5E;
#endif

	out_be32(&pci->tcr2, barEn);

	/* Deassert reset bit */
	clrbits_be32(&pci->gscr, PCI_GSCR_PR);
	udelay(1000);

	/* Enable PCI bus master support */
	hose->first_busno = 0;
	hose->last_busno = 0xff;

	pci_set_region(hose->regions + 0, CONFIG_SYS_PCI_MEM_BUS, CONFIG_SYS_PCI_MEM_PHYS,
		       CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM);

	pci_set_region(hose->regions + 1, CONFIG_SYS_PCI_IO_BUS, CONFIG_SYS_PCI_IO_PHYS,
		       CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);

	pci_set_region(hose->regions + 2, CONFIG_SYS_PCI_SYS_MEM_BUS,
		       CONFIG_SYS_PCI_SYS_MEM_PHYS, CONFIG_SYS_PCI_SYS_MEM_SIZE,
		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);

	hose->region_count = 3;

	hose->cfg_addr = &(pci->car);
	hose->cfg_data = (volatile unsigned char *)CONFIG_SYS_PCI_CFG_BUS;

	pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word,
		    pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word,
		    pci_write_cfg_dword);

	/* Hose scan */
	pci_register_hose(hose);
	hose->last_busno = pci_hose_scan(hose);
}
Beispiel #23
0
/*-----------------------------------------------------------------------------+
 * pci_init.  Initializes the 405GP PCI Configuration regs.
 *-----------------------------------------------------------------------------*/
void pci_405gp_init(struct pci_controller *hose)
{
	int i, reg_num = 0;
	bd_t *bd = gd->bd;

	unsigned short temp_short;
	unsigned long ptmpcila[2] = {CONFIG_SYS_PCI_PTM1PCI, CONFIG_SYS_PCI_PTM2PCI};
#if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405)
	char *ptmla_str, *ptmms_str;
#endif
	unsigned long ptmla[2]    = {CONFIG_SYS_PCI_PTM1LA, CONFIG_SYS_PCI_PTM2LA};
	unsigned long ptmms[2]    = {CONFIG_SYS_PCI_PTM1MS, CONFIG_SYS_PCI_PTM2MS};
#if defined(CONFIG_PIP405) || defined (CONFIG_MIP405)
	unsigned long pmmla[3]    = {0x80000000, 0xA0000000, 0};
	unsigned long pmmma[3]    = {0xE0000001, 0xE0000001, 0};
	unsigned long pmmpcila[3] = {0x80000000, 0x00000000, 0};
	unsigned long pmmpciha[3] = {0x00000000, 0x00000000, 0};
#else
	unsigned long pmmla[3]    = {0x80000000, 0,0};
	unsigned long pmmma[3]    = {0xC0000001, 0,0};
	unsigned long pmmpcila[3] = {0x80000000, 0,0};
	unsigned long pmmpciha[3] = {0x00000000, 0,0};
#endif
#ifdef CONFIG_PCI_PNP
#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
	char *s;
#endif
#endif

#if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405)
	ptmla_str = getenv("ptm1la");
	ptmms_str = getenv("ptm1ms");
	if(NULL != ptmla_str && NULL != ptmms_str ) {
	        ptmla[0] = simple_strtoul (ptmla_str, NULL, 16);
		ptmms[0] = simple_strtoul (ptmms_str, NULL, 16);
	}

	ptmla_str = getenv("ptm2la");
	ptmms_str = getenv("ptm2ms");
	if(NULL != ptmla_str && NULL != ptmms_str ) {
	        ptmla[1] = simple_strtoul (ptmla_str, NULL, 16);
		ptmms[1] = simple_strtoul (ptmms_str, NULL, 16);
	}
#endif

	/*
	 * Register the hose
	 */
	hose->first_busno = 0;
	hose->last_busno = 0xff;

	/* ISA/PCI I/O space */
	pci_set_region(hose->regions + reg_num++,
		       MIN_PCI_PCI_IOADDR,
		       MIN_PLB_PCI_IOADDR,
		       0x10000,
		       PCI_REGION_IO);

	/* PCI I/O space */
	pci_set_region(hose->regions + reg_num++,
		       0x00800000,
		       0xe8800000,
		       0x03800000,
		       PCI_REGION_IO);

	reg_num = 2;

	/* Memory spaces */
	for (i=0; i<2; i++)
		if (ptmms[i] & 1)
		{
			if (!i) hose->pci_fb = hose->regions + reg_num;

			pci_set_region(hose->regions + reg_num++,
				       ptmpcila[i], ptmla[i],
				       ~(ptmms[i] & 0xfffff000) + 1,
				       PCI_REGION_MEM |
				       PCI_REGION_SYS_MEMORY);
		}

	/* PCI memory spaces */
	for (i=0; i<3; i++)
		if (pmmma[i] & 1)
		{
			pci_set_region(hose->regions + reg_num++,
				       pmmpcila[i], pmmla[i],
				       ~(pmmma[i] & 0xfffff000) + 1,
				       PCI_REGION_MEM);
		}

	hose->region_count = reg_num;

	pci_setup_indirect(hose,
			   PCICFGADR,
			   PCICFGDATA);

	if (hose->pci_fb)
		pciauto_region_init(hose->pci_fb);

	/* Let board change/modify hose & do initial checks */
	if (pci_pre_init (hose) == 0) {
		printf("PCI: Board-specific initialization failed.\n");
		printf("PCI: Configuration aborted.\n");
		return;
	}

	pci_register_hose(hose);

	/*--------------------------------------------------------------------------+
	 * 405GP PCI Master configuration.
	 * Map one 512 MB range of PLB/processor addresses to PCI memory space.
	 * PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF
	 * Use byte reversed out routines to handle endianess.
	 *--------------------------------------------------------------------------*/
	out32r(PMM0MA,    (pmmma[0]&~0x1)); /* disable, configure PMMxLA, PMMxPCILA first */
	out32r(PMM0LA,    pmmla[0]);
	out32r(PMM0PCILA, pmmpcila[0]);
	out32r(PMM0PCIHA, pmmpciha[0]);
	out32r(PMM0MA,    pmmma[0]);

	/*--------------------------------------------------------------------------+
	 * PMM1 is not used.  Initialize them to zero.
	 *--------------------------------------------------------------------------*/
	out32r(PMM1MA,    (pmmma[1]&~0x1));
	out32r(PMM1LA,    pmmla[1]);
	out32r(PMM1PCILA, pmmpcila[1]);
	out32r(PMM1PCIHA, pmmpciha[1]);
	out32r(PMM1MA,    pmmma[1]);

	/*--------------------------------------------------------------------------+
	 * PMM2 is not used.  Initialize them to zero.
	 *--------------------------------------------------------------------------*/
	out32r(PMM2MA,    (pmmma[2]&~0x1));
	out32r(PMM2LA,    pmmla[2]);
	out32r(PMM2PCILA, pmmpcila[2]);
	out32r(PMM2PCIHA, pmmpciha[2]);
	out32r(PMM2MA,    pmmma[2]);

	/*--------------------------------------------------------------------------+
	 * 405GP PCI Target configuration.  (PTM1)
	 * Note: PTM1MS is hardwire enabled but we set the enable bit anyway.
	 *--------------------------------------------------------------------------*/
	out32r(PTM1LA,    ptmla[0]);         /* insert address                     */
	out32r(PTM1MS,    ptmms[0]);         /* insert size, enable bit is 1       */
	pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_1, ptmpcila[0]);

	/*--------------------------------------------------------------------------+
	 * 405GP PCI Target configuration.  (PTM2)
	 *--------------------------------------------------------------------------*/
	out32r(PTM2LA, ptmla[1]);            /* insert address                     */
	pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, ptmpcila[1]);

	if (ptmms[1] == 0)
	{
		out32r(PTM2MS,    0x00000001);   /* set enable bit                     */
		pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, 0x00000000);
		out32r(PTM2MS,    0x00000000);   /* disable                            */
	}
	else
	{
		out32r(PTM2MS, ptmms[1]);        /* insert size, enable bit is 1       */
	}

	/*
	 * Insert Subsystem Vendor and Device ID
	 */
	pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
#ifdef CONFIG_CPCI405
	if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
		pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
	else
		pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID2);
#else
	pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
#endif

	/*
	 * Insert Class-code
	 */
#ifdef CONFIG_SYS_PCI_CLASSCODE
	pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CONFIG_SYS_PCI_CLASSCODE);
#endif /* CONFIG_SYS_PCI_CLASSCODE */

	/*--------------------------------------------------------------------------+
	 * If PCI speed = 66MHz, set 66MHz capable bit.
	 *--------------------------------------------------------------------------*/
	if (bd->bi_pci_busfreq >= 66000000) {
		pci_read_config_word(PCIDEVID_405GP, PCI_STATUS, &temp_short);
		pci_write_config_word(PCIDEVID_405GP,PCI_STATUS,(temp_short|PCI_STATUS_66MHZ));
	}

#if (CONFIG_PCI_HOST != PCI_HOST_ADAPTER)
#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
	if ((mfdcr(strap) & PSR_PCI_ARBIT_EN) ||
	    (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
#endif
	{
		/*--------------------------------------------------------------------------+
		 * Write the 405GP PCI Configuration regs.
		 * Enable 405GP to be a master on the PCI bus (PMM).
		 * Enable 405GP to act as a PCI memory target (PTM).
		 *--------------------------------------------------------------------------*/
		pci_read_config_word(PCIDEVID_405GP, PCI_COMMAND, &temp_short);
		pci_write_config_word(PCIDEVID_405GP, PCI_COMMAND, temp_short |
				      PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
	}
#endif

#if defined(CONFIG_405EP) /* on ppc405ep vendor id is not set */
	pci_write_config_word(PCIDEVID_405GP, PCI_VENDOR_ID, 0x1014); /* IBM */
#endif

	/*
	 * Set HCE bit (Host Configuration Enabled)
	 */
	pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &temp_short);
	pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (temp_short | 0x0001));

#ifdef CONFIG_PCI_PNP
	/*--------------------------------------------------------------------------+
	 * Scan the PCI bus and configure devices found.
	 *--------------------------------------------------------------------------*/
#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
	if ((mfdcr(strap) & PSR_PCI_ARBIT_EN) ||
	    (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
#endif
	{
#ifdef CONFIG_PCI_SCAN_SHOW
		printf("PCI:   Bus Dev VenId DevId Class Int\n");
#endif
		hose->last_busno = pci_hose_scan(hose);
	}
#endif  /* CONFIG_PCI_PNP */

}
Beispiel #24
0
static void pci_init_bus(int bus, struct pci_region *reg)
{
    volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
    volatile pot83xx_t *pot = immr->ios.pot;
    volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[bus];
    struct pci_controller *hose = &pci_hose[bus];
    u32 dev;
    u16 reg16;
    int i;

    if (bus == 1)
        pot += 3;

    /* Setup outbound translation windows */
    for (i = 0; i < 3; i++, reg++, pot++) {
        if (reg->size == 0)
            break;

        hose->regions[i] = *reg;
        hose->region_count++;

        pot->potar = reg->bus_start >> 12;
        pot->pobar = reg->phys_start >> 12;
        pot->pocmr = ~(reg->size - 1) >> 12;

        if (reg->flags & PCI_REGION_IO)
            pot->pocmr |= POCMR_IO;
#ifdef CONFIG_83XX_PCI_STREAMING
        else if (reg->flags & PCI_REGION_PREFETCH)
            pot->pocmr |= POCMR_SE;
#endif

        if (bus == 1)
            pot->pocmr |= POCMR_DST;

        pot->pocmr |= POCMR_EN;
    }

    /* Point inbound translation at RAM */
    pci_ctrl->pitar1 = 0;
    pci_ctrl->pibar1 = 0;
    pci_ctrl->piebar1 = 0;
    pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
                       PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size - 1));

    i = hose->region_count++;
    hose->regions[i].bus_start = 0;
    hose->regions[i].phys_start = 0;
    hose->regions[i].size = gd->ram_size;
    hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;

    hose->first_busno = pci_last_busno() + 1;
    hose->last_busno = 0xff;

    pci_setup_indirect(hose, CONFIG_SYS_IMMR + 0x8300 + bus * 0x80,
                       CONFIG_SYS_IMMR + 0x8304 + bus * 0x80);

    pci_register_hose(hose);

    /*
     * Write to Command register
     */
    reg16 = 0xff;
    dev = PCI_BDF(hose->first_busno, 0, 0);
    pci_hose_read_config_word(hose, dev, PCI_COMMAND, &reg16);
    reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
    pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);

    /*
     * Clear non-reserved bits in status register.
     */
    pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
    pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
    pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);

#ifdef CONFIG_PCI_SCAN_SHOW
    printf("PCI:   Bus Dev VenId DevId Class Int\n");
#endif
#ifndef CONFIG_PCISLAVE
    /*
     * Hose scan.
     */
    hose->last_busno = pci_hose_scan(hose);
#endif
}
Beispiel #25
0
int pci_440_init (struct pci_controller *hose)
{
	int reg_num = 0;

#ifndef CONFIG_DISABLE_PISE_TEST
	/*--------------------------------------------------------------------------+
	 * The PCI initialization sequence enable bit must be set ... if not abort
	 * pci setup since updating the bit requires chip reset.
	 *--------------------------------------------------------------------------*/
#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
	unsigned long strap;

	mfsdr(sdr_sdstp1,strap);
	if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) {
		printf("PCI: SDR0_STRP1[PISE] not set.\n");
		printf("PCI: Configuration aborted.\n");
		return -1;
	}
#elif defined(CONFIG_440GP)
	unsigned long strap;

	strap = mfdcr(cpc0_strp1);
	if ((strap & CPC0_STRP1_PISE_MASK) == 0) {
		printf("PCI: CPC0_STRP1[PISE] not set.\n");
		printf("PCI: Configuration aborted.\n");
		return -1;
	}
#endif
#endif /* CONFIG_DISABLE_PISE_TEST */

	/*--------------------------------------------------------------------------+
	 * PCI controller init
	 *--------------------------------------------------------------------------*/
	hose->first_busno = 0;
	hose->last_busno = 0;

	/* PCI I/O space */
	pci_set_region(hose->regions + reg_num++,
		       0x00000000,
		       PCIX0_IOBASE,
		       0x10000,
		       PCI_REGION_IO);

	/* PCI memory space */
	pci_set_region(hose->regions + reg_num++,
		       CONFIG_SYS_PCI_TARGBASE,
		       CONFIG_SYS_PCI_MEMBASE,
#ifdef CONFIG_SYS_PCI_MEMSIZE
		       CONFIG_SYS_PCI_MEMSIZE,
#else
		       0x10000000,
#endif
		       PCI_REGION_MEM );

#if defined(CONFIG_PCI_SYS_MEM_BUS) && defined(CONFIG_PCI_SYS_MEM_PHYS) && \
	defined(CONFIG_PCI_SYS_MEM_SIZE)
	/* System memory space */
	pci_set_region(hose->regions + reg_num++,
		       CONFIG_PCI_SYS_MEM_BUS,
		       CONFIG_PCI_SYS_MEM_PHYS,
		       CONFIG_PCI_SYS_MEM_SIZE,
		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY );
#endif

	hose->region_count = reg_num;

	pci_setup_indirect(hose, PCIX0_CFGADR, PCIX0_CFGDATA);

	/* Let board change/modify hose & do initial checks */
	if (pci_pre_init (hose) == 0) {
		printf("PCI: Board-specific initialization failed.\n");
		printf("PCI: Configuration aborted.\n");
		return -1;
	}

	pci_register_hose( hose );

	/*--------------------------------------------------------------------------+
	 * PCI target init
	 *--------------------------------------------------------------------------*/
#if defined(CONFIG_SYS_PCI_TARGET_INIT)
	pci_target_init(hose);                /* Let board setup pci target */
#else
	out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
	out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_ID );
	out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */
#endif

#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
    defined(CONFIG_460EX) || defined(CONFIG_460GT)
	out32r( PCIX0_BRDGOPT1, 0x04000060 );               /* PLB Rq pri highest   */
	out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1  */
#elif defined(PCIX0_BRDGOPT1)
	out32r( PCIX0_BRDGOPT1, 0x10000060 );               /* PLB Rq pri highest   */
	out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 1 ); /* Enable host config   */
#endif

	/*--------------------------------------------------------------------------+
	 * PCI master init: default is one 256MB region for PCI memory:
	 * 0x3_00000000 - 0x3_0FFFFFFF  ==> CONFIG_SYS_PCI_MEMBASE
	 *--------------------------------------------------------------------------*/
#if defined(CONFIG_SYS_PCI_MASTER_INIT)
	pci_master_init(hose);          /* Let board setup pci master */
#else
	out32r( PCIX0_POM0SA, 0 ); /* disable */
	out32r( PCIX0_POM1SA, 0 ); /* disable */
	out32r( PCIX0_POM2SA, 0 ); /* disable */
#if defined(CONFIG_440SPE) || \
    defined(CONFIG_460EX) || defined(CONFIG_460GT)
	out32r( PCIX0_POM0LAL, 0x10000000 );
	out32r( PCIX0_POM0LAH, 0x0000000c );
#else
	out32r( PCIX0_POM0LAL, 0x00000000 );
	out32r( PCIX0_POM0LAH, 0x00000003 );
#endif
	out32r( PCIX0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE );
	out32r( PCIX0_POM0PCIAH, 0x00000000 );
	out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */
	out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 );
#endif

	/*--------------------------------------------------------------------------+
	 * PCI host configuration -- we don't make any assumptions here ... the
	 * _board_must_indicate_ what to do -- there's just too many runtime
	 * scenarios in environments like cPCI, PPMC, etc. to make a determination
	 * based on hard-coded values or state of arbiter enable.
	 *--------------------------------------------------------------------------*/
	if (is_pci_host(hose)) {
#ifdef CONFIG_PCI_SCAN_SHOW
		printf("PCI:   Bus Dev VenId DevId Class Int\n");
#endif
#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \
    !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
		out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER);
#endif
		hose->last_busno = pci_hose_scan(hose);
	}
	return hose->last_busno;
}
Beispiel #26
0
void pci_mpc8250_init (struct pci_controller *hose)
{
	u16 tempShort;

	volatile immap_t *immap = (immap_t *) CFG_IMMR;
	pci_dev_t host_devno = PCI_BDF (0, 0, 0);

	pci_setup_indirect (hose, CFG_IMMR + PCI_CFG_ADDR_REG,
			    CFG_IMMR + PCI_CFG_DATA_REG);

	/*
	 * Setting required to enable local bus for PCI (SIUMCR [LBPC]).
	 */
#ifdef CONFIG_MPC8266ADS
	immap->im_siu_conf.sc_siumcr =
		(immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
		| SIUMCR_LBPC01;
#elif defined CONFIG_MPC8272
	immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
				  ~SIUMCR_BBD &
				  ~SIUMCR_ESE &
				  ~SIUMCR_PBSE &
				  ~SIUMCR_CDIS &
				  ~SIUMCR_DPPC11 &
				  ~SIUMCR_L2CPC11 &
				  ~SIUMCR_LBPC11 &
				  ~SIUMCR_APPC11 &
				  ~SIUMCR_CS10PC11 &
				  ~SIUMCR_BCTLC11 &
				  ~SIUMCR_MMR11)
				  | SIUMCR_DPPC11
				  | SIUMCR_L2CPC01
				  | SIUMCR_LBPC00
				  | SIUMCR_APPC10
				  | SIUMCR_CS10PC00
				  | SIUMCR_BCTLC00
				  | SIUMCR_MMR11;
#elif defined(CONFIG_TQM8272)
/* nothing to do for this Board here */
#else
	/*
	 * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
	 * and local bus for PCI (SIUMCR [LBPC]).
	 */
	immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
						~SIUMCR_LBPC11 &
						~SIUMCR_CS10PC11 &
						~SIUMCR_LBPC11) |
					SIUMCR_LBPC01 |
					SIUMCR_CS10PC01 |
					SIUMCR_APPC10;
#endif

	/* Make PCI lowest priority */
	/* Each 4 bits is a device bus request	and the MS 4bits
	   is highest priority */
	/* Bus		     4bit value
	   ---		     ----------
	   CPM high	     0b0000
	   CPM middle	     0b0001
	   CPM low	     0b0010
	   PCI reguest	     0b0011
	   Reserved	     0b0100
	   Reserved	     0b0101
	   Internal Core     0b0110
	   External Master 1 0b0111
	   External Master 2 0b1000
	   External Master 3 0b1001
	   The rest are reserved */
	immap->im_siu_conf.sc_ppc_alrh = 0x61207893;

	/* Park bus on core while modifying PCI Bus accesses */
	immap->im_siu_conf.sc_ppc_acr = 0x6;

	/*
	 * Set up master windows that allow the CPU to access PCI space. These
	 * windows are set up using the two SIU PCIBR registers.
	 */
	immap->im_memctl.memc_pcimsk0 = PCIMSK0_MASK;
	immap->im_memctl.memc_pcibr0 = PCI_MSTR0_LOCAL | PCIBR_ENABLE;

#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
	immap->im_memctl.memc_pcimsk1 = PCIMSK1_MASK;
	immap->im_memctl.memc_pcibr1 = PCI_MSTR1_LOCAL | PCIBR_ENABLE;
#endif

	/* Release PCI RST (by default the PCI RST signal is held low)	*/
	immap->im_pci.pci_gcr = cpu_to_le32 (PCIGCR_PCI_BUS_EN);

	/* give it some time */
	{
#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
		/* Give the PCI cards more time to initialize before query
		   This might be good for other boards also
		 */
		int i;

		for (i = 0; i < 1000; ++i)
#endif
			udelay (1000);
	}

	/*
	 * Set up master window that allows the CPU to access PCI Memory (prefetch)
	 * space. This window is set up using the first set of Outbound ATU registers.
	 */
	immap->im_pci.pci_potar0 = cpu_to_le32 (PCI_MSTR_MEM_BUS >> 12);	/* PCI base */
	immap->im_pci.pci_pobar0 = cpu_to_le32 (PCI_MSTR_MEM_LOCAL >> 12);	/* Local base */
	immap->im_pci.pci_pocmr0 = cpu_to_le32 (POCMR0_MASK_ATTRIB);	/* Size & attribute */

	/*
	 * Set up master window that allows the CPU to access PCI Memory (non-prefetch)
	 * space. This window is set up using the second set of Outbound ATU registers.
	 */
	immap->im_pci.pci_potar1 = cpu_to_le32 (PCI_MSTR_MEMIO_BUS >> 12);	/* PCI base */
	immap->im_pci.pci_pobar1 = cpu_to_le32 (PCI_MSTR_MEMIO_LOCAL >> 12);	/* Local base */
	immap->im_pci.pci_pocmr1 = cpu_to_le32 (POCMR1_MASK_ATTRIB);	/* Size & attribute */

	/*
	 * Set up master window that allows the CPU to access PCI IO space. This window
	 * is set up using the third set of Outbound ATU registers.
	 */
	immap->im_pci.pci_potar2 = cpu_to_le32 (PCI_MSTR_IO_BUS >> 12); /* PCI base */
	immap->im_pci.pci_pobar2 = cpu_to_le32 (PCI_MSTR_IO_LOCAL >> 12);	/* Local base */
	immap->im_pci.pci_pocmr2 = cpu_to_le32 (POCMR2_MASK_ATTRIB);	/* Size & attribute */

	/*
	 * Set up slave window that allows PCI masters to access MPC826x local memory.
	 * This window is set up using the first set of Inbound ATU registers
	 */
	immap->im_pci.pci_pitar0 = cpu_to_le32 (PCI_SLV_MEM_LOCAL >> 12);	/* PCI base */
	immap->im_pci.pci_pibar0 = cpu_to_le32 (PCI_SLV_MEM_BUS >> 12); /* Local base */
	immap->im_pci.pci_picmr0 = cpu_to_le32 (PICMR0_MASK_ATTRIB);	/* Size & attribute */

	/* See above for description - puts PCI request as highest priority */
#ifdef CONFIG_MPC8272
	immap->im_siu_conf.sc_ppc_alrh = 0x01236745;
#else
	immap->im_siu_conf.sc_ppc_alrh = 0x03124567;
#endif

	/* Park the bus on the PCI */
	immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;

	/* Host mode - specify the bridge as a host-PCI bridge */

	pci_hose_write_config_byte (hose, host_devno, PCI_CLASS_CODE,
				    PCI_CLASS_BRIDGE_CTLR);

	/* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */
	pci_hose_read_config_word (hose, host_devno, PCI_COMMAND, &tempShort);
	pci_hose_write_config_word (hose, host_devno, PCI_COMMAND,
				    tempShort | PCI_COMMAND_MASTER |
				    PCI_COMMAND_MEMORY);

	/* do some bridge init, should be done on all 8260 based bridges */
	pci_hose_write_config_byte (hose, host_devno, PCI_CACHE_LINE_SIZE,
				    0x08);
	pci_hose_write_config_byte (hose, host_devno, PCI_LATENCY_TIMER,
				    0xF8);

	hose->first_busno = 0;
	hose->last_busno = 0xff;

	/* System memory space */
#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 || defined CONFIG_PM826
	pci_set_region (hose->regions + 0,
			PCI_SLV_MEM_BUS,
			PCI_SLV_MEM_LOCAL,
			gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY);
#else
	pci_set_region (hose->regions + 0,
			CFG_SDRAM_BASE,
			CFG_SDRAM_BASE,
			0x4000000, PCI_REGION_MEM | PCI_REGION_MEMORY);
#endif

	/* PCI memory space */
#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
	pci_set_region (hose->regions + 1,
			PCI_MSTR_MEMIO_BUS,
			PCI_MSTR_MEMIO_LOCAL,
			PCI_MSTR_MEMIO_SIZE, PCI_REGION_MEM);
#else
	pci_set_region (hose->regions + 1,
			PCI_MSTR_MEM_BUS,
			PCI_MSTR_MEM_LOCAL,
			PCI_MSTR_MEM_SIZE, PCI_REGION_MEM);
#endif

	/* PCI I/O space */
	pci_set_region (hose->regions + 2,
			PCI_MSTR_IO_BUS,
			PCI_MSTR_IO_LOCAL, PCI_MSTR_IO_SIZE, PCI_REGION_IO);

	hose->region_count = 3;

	pci_register_hose (hose);
	/* Mask off master abort machine checks */
	immap->im_pci.pci_emr &= cpu_to_le32 (~PCI_ERROR_PCI_NO_RSP);
	eieio ();

	hose->last_busno = pci_hose_scan (hose);


	/* clear the error in the error status register */
	immap->im_pci.pci_esr = cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);

	/* unmask master abort machine checks */
	immap->im_pci.pci_emr |= cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);
}
Beispiel #27
0
/**************************************************************************
 * pci_init_board()
 *
 * NOTICE: MPC8349 internally has two PCI controllers (PCI1 and PCI2) but since
 * per TQM834x design physical connections to external devices (PCI sockets)
 * are routed only to the PCI1 we do not account for the second one - this code
 * supports PCI1 module only. Should support for the PCI2 be required in the
 * future it needs a separate pci_controller structure (above) and handling -
 * please refer to other boards' implementation for dual PCI host controllers,
 * for example board/Marvell/db64360/pci.c, pci_init_board()
 *
 */
void
pci_init_board(void)
{
	volatile immap_t *	immr;
	volatile clk83xx_t *	clk;
	volatile law83xx_t *	pci_law;
	volatile pot83xx_t *	pci_pot;
	volatile pcictrl83xx_t *	pci_ctrl;
	volatile pciconf83xx_t *	pci_conf;
	u16 reg16;
	u32 reg32;
	struct	pci_controller * hose;

	immr = (immap_t *)CONFIG_SYS_IMMR;
	clk = (clk83xx_t *)&immr->clk;
	pci_law = immr->sysconf.pcilaw;
	pci_pot = immr->ios.pot;
	pci_ctrl = immr->pci_ctrl;
	pci_conf = immr->pci_conf;

	hose = &pci1_hose;

	/*
	 * Configure PCI controller and PCI_CLK_OUTPUT
	 */

	/*
	 * WARNING! only PCI_CLK_OUTPUT1 is enabled here as this is the one
	 * line actually used for clocking all external PCI devices in TQM83xx.
	 * Enabling other PCI_CLK_OUTPUT lines may lead to board's hang for
	 * unknown reasons - particularly PCI_CLK_OUTPUT6 and PCI_CLK_OUTPUT7
	 * are known to hang the board; this issue is under investigation
	 * (13 oct 05)
	 */
	reg32 = OCCR_PCICOE1;
#if 0
	/* enabling all PCI_CLK_OUTPUT lines HANGS the board... */
	reg32 = 0xff000000;
#endif
	if (clk->spmr & SPMR_CKID) {
		/* PCI Clock is half CONFIG_83XX_CLKIN so need to set up OCCR
		 * fields accordingly */
		reg32 |= (OCCR_PCI1CR | OCCR_PCI2CR);

		reg32 |= (OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 \
			  | OCCR_PCICD3 | OCCR_PCICD4 | OCCR_PCICD5 \
			  | OCCR_PCICD6 | OCCR_PCICD7);
	}

	clk->occr = reg32;
	udelay(2000);

	/*
	 * Release PCI RST Output signal
	 */
	pci_ctrl[0].gcr = 0;
	udelay(2000);
	pci_ctrl[0].gcr = 1;
	udelay(2000);

	/*
	 * Configure PCI Local Access Windows
	 */
	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;

	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M;

	/*
	 * Configure PCI Outbound Translation Windows
	 */

	/* PCI1 mem space */
	pci_pot[0].potar = (CONFIG_SYS_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
	pci_pot[0].pobar = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
	pci_pot[0].pocmr = POCMR_EN | (POCMR_CM_512M & POCMR_CM_MASK);

	/* PCI1 IO space */
	pci_pot[1].potar = (CONFIG_SYS_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
	pci_pot[1].pobar = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
	pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);

	/*
	 * Configure PCI Inbound Translation Windows
	 */

	/* we need RAM mapped to PCI space for the devices to
	 * access main memory */
	pci_ctrl[0].pitar1 = 0x0;
	pci_ctrl[0].pibar1 = 0x0;
	pci_ctrl[0].piebar1 = 0x0;
	pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_256M;

	hose->first_busno = 0;
	hose->last_busno = 0xff;

	/* PCI memory space */
	pci_set_region(hose->regions + 0,
		       CONFIG_SYS_PCI1_MEM_BASE,
		       CONFIG_SYS_PCI1_MEM_PHYS,
		       CONFIG_SYS_PCI1_MEM_SIZE,
		       PCI_REGION_MEM);

	/* PCI IO space */
	pci_set_region(hose->regions + 1,
		       CONFIG_SYS_PCI1_IO_BASE,
		       CONFIG_SYS_PCI1_IO_PHYS,
		       CONFIG_SYS_PCI1_IO_SIZE,
		       PCI_REGION_IO);

	/* System memory space */
	pci_set_region(hose->regions + 2,
		       CONFIG_PCI_SYS_MEM_BUS,
		       CONFIG_PCI_SYS_MEM_PHYS,
		       CONFIG_PCI_SYS_MEM_SIZE,
		       PCI_REGION_MEM | PCI_REGION_MEMORY);

	hose->region_count = 3;

	pci_setup_indirect(hose,
			   (CONFIG_SYS_IMMR+0x8300),
			   (CONFIG_SYS_IMMR+0x8304));

	pci_register_hose(hose);

	/*
	 * Write to Command register
	 */
	reg16 = 0xff;
	pci_hose_read_config_word (hose, PCI_BDF(0,0,0), PCI_COMMAND,
					&reg16);
	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
	pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND,
					reg16);

	/*
	 * Clear non-reserved bits in status register.
	 */
	pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_STATUS,
					0xffff);
	pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_LATENCY_TIMER,
					0x80);

#ifdef CONFIG_PCI_SCAN_SHOW
	printf("PCI:   Bus Dev VenId DevId Class Int\n");
#endif
	/*
	 * Hose scan.
	 */
	hose->last_busno = pci_hose_scan(hose);
}