static void __init
yosemite_setup_hose(void)
{
unsigned int bar_response, bar;
struct pci_controller *hose;
yosemite_setup_pci();
hose = pcibios_alloc_controller();
if (!hose)
return;
hose->first_busno = 0;
hose->last_busno = 0xff;
hose->pci_mem_offset = YOSEMITE_PCI_MEM_OFFSET;
pci_init_resource(&hose->io_resource,
YOSEMITE_PCI_LOWER_IO,
YOSEMITE_PCI_UPPER_IO,
IORESOURCE_IO,
"PCI host bridge");
pci_init_resource(&hose->mem_resources[0],
YOSEMITE_PCI_LOWER_MEM,
YOSEMITE_PCI_UPPER_MEM,
IORESOURCE_MEM,
"PCI host bridge");
ppc_md.pci_exclude_device = yosemite_exclude_device;
hose->io_space.start = YOSEMITE_PCI_LOWER_IO;
hose->io_space.end = YOSEMITE_PCI_UPPER_IO;
hose->mem_space.start = YOSEMITE_PCI_LOWER_MEM;
hose->mem_space.end = YOSEMITE_PCI_UPPER_MEM;
isa_io_base =
(unsigned long)ioremap64(YOSEMITE_PCI_IO_BASE, YOSEMITE_PCI_IO_SIZE);
hose->io_base_virt = (void *)isa_io_base;
setup_indirect_pci(hose,
YOSEMITE_PCI_CFGA_PLB32,
YOSEMITE_PCI_CFGD_PLB32);
hose->set_cfg_type = 1;
/* Zero config bars */
for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
early_write_config_dword(hose, hose->first_busno,
PCI_FUNC(hose->first_busno), bar,
0x00000000);
early_read_config_dword(hose, hose->first_busno,
PCI_FUNC(hose->first_busno), bar,
&bar_response);
}
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = yosemite_map_irq;
}
void __init
mpc86xx_setup_one_hose(struct pci_controller * hose, u32 cfg_addr_offset, u32 cfg_data_offset,
u32 lower_mem, u32 upper_mem, u32 io_base)
{
extern void setup_indirect_pcie(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);
bd_t *binfo = (bd_t *) __res;
setup_indirect_pcie(hose, binfo->bi_immr_base + cfg_addr_offset,
binfo->bi_immr_base + cfg_data_offset);
hose->set_cfg_type = 1;
mpc86xx_setup_pcie(hose, cfg_addr_offset, lower_mem, upper_mem, io_base);
hose->pci_mem_offset = MPC86XX_PCIE_MEM_OFFSET;
hose->mem_space.start = lower_mem;
hose->mem_space.end = upper_mem;
hose->io_space.start = MPC86XX_PCIE_LOWER_IO;
hose->io_space.end = MPC86XX_PCIE_UPPER_IO;
hose->io_base_phys = io_base;
hose->io_base_virt = ioremap(io_base,
MPC86XX_PCIE_IO_SIZE);
/* setup resources */
pci_init_resource(&hose->mem_resources[0], lower_mem, upper_mem,
IORESOURCE_MEM, "PCI Express host bridge");
pci_init_resource(&hose->io_resource, MPC86XX_PCIE_LOWER_IO,
MPC86XX_PCIE_UPPER_IO, IORESOURCE_IO,
"PCI Express host bridge");
}
static void __init
yucca_setup_hoses(void)
{
struct pci_controller *hose;
char name[20];
int i;
if (0 && ppc440spe_init_pcie()) {
printk(KERN_WARNING "PPC440SPe PCI Express initialization failed\n");
return;
}
for (i = 0; i <= 2; ++i) {
if (!yucca_pcie_card_present(i))
continue;
printk(KERN_INFO "PCIE%d: card present\n", i);
yucca_setup_pcie_fpga_rootpoint(i);
if (ppc440spe_init_pcie_rootport(i)) {
printk(KERN_WARNING "PCIE%d: initialization failed\n", i);
continue;
}
hose = pcibios_alloc_controller();
if (!hose)
return;
sprintf(name, "PCIE%d host bridge", i);
pci_init_resource(&hose->io_resource,
YUCCA_PCIX_LOWER_IO,
YUCCA_PCIX_UPPER_IO,
IORESOURCE_IO,
name);
hose->mem_space.start = YUCCA_PCIE_LOWER_MEM +
i * YUCCA_PCIE_MEM_SIZE;
hose->mem_space.end = hose->mem_space.start +
YUCCA_PCIE_MEM_SIZE - 1;
pci_init_resource(&hose->mem_resources[0],
hose->mem_space.start,
hose->mem_space.end,
IORESOURCE_MEM,
name);
hose->first_busno = 0;
hose->last_busno = 15;
hose_type[hose->index] = HOSE_PCIE0 + i;
ppc440spe_setup_pcie(hose, i);
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
}
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = yucca_map_irq;
}
static void __init
p3p440_setup_hose(void)
{
struct pci_controller *hose;
if (!is_monarch()) {
/*
* REMARK: This Non-Monarch mode need perhaps some changes.
* It's not tested at all, because of lack of hardware. --sr
*/
printk("P3P440-PCI: Non-Monarch detected, skipping PCI init!\n");
return;
}
/* Configure windows on the PCI-X host bridge */
p3p440_setup_pcix();
hose = pcibios_alloc_controller();
if (!hose)
return;
hose->first_busno = 0;
hose->last_busno = 0xff;
hose->pci_mem_offset = P3P440_PCI_MEM_OFFSET;
pci_init_resource(&hose->io_resource,
P3P440_PCI_LOWER_IO,
P3P440_PCI_UPPER_IO,
IORESOURCE_IO,
"PCI host bridge");
pci_init_resource(&hose->mem_resources[0],
P3P440_PCI_LOWER_MEM,
P3P440_PCI_UPPER_MEM,
IORESOURCE_MEM,
"PCI host bridge");
hose->io_space.start = P3P440_PCI_LOWER_IO;
hose->io_space.end = P3P440_PCI_UPPER_IO;
hose->mem_space.start = P3P440_PCI_LOWER_MEM;
hose->mem_space.end = P3P440_PCI_UPPER_MEM;
hose->io_base_virt = ioremap64(P3P440_PCI_IO_BASE, P3P440_PCI_IO_SIZE);
isa_io_base = (unsigned long)hose->io_base_virt;
setup_indirect_pci(hose, PCIX0_CFGA, PCIX0_CFGD);
hose->set_cfg_type = 1;
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = p3p440_map_irq;
}
static void __init taiga_setup_bridge(void)
{
struct pci_controller *hose;
hose = pcibios_alloc_controller();
if (hose){
hose->first_busno = 0;
hose->last_busno = 0xff;
hose->pci_mem_offset = TAIGA_PCI_MEM_OFFSET;
/* Setup resources to match map
* PCI memory and IO space are set in PFAB_BARs by boot code
* 64KB take one 16MB LUT entry, PFAB_IO
*/
pci_init_resource(&hose->io_resource, TAIGA_PCI_IO_START,
TAIGA_PCI_IO_END, IORESOURCE_IO,
"PCI host bridge");
/* OCN to PCI/X transaction is unchanged,
* bar1 first 8 LUTs, 128MB
*/
pci_init_resource(&hose->mem_resources[0],
TAIGA_PCI_MEM_START,
TAIGA_PCI_MEM_END,
IORESOURCE_MEM, "PCI host bridge");
(hose)->io_space.start = TAIGA_PCI_IO_START;
(hose)->io_space.end = TAIGA_PCI_IO_END;
(hose)->mem_space.start = TAIGA_PCI_MEM_START;
(hose)->mem_space.end = TAIGA_PCI_MEM_END;
(hose)->io_base_virt = (void *)TAIGA_ISA_IO_BASE;
(hose)->ops = &direct_pci_ops;
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pcibios_fixup = NULL;
ppc_md.pcibios_fixup_bus = NULL;
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = taiga_map_irq;
if (ppc_md.progress)
ppc_md.progress("tsi108: resources set", 0x100);
tsi108_bridge_init(hose, TSI108_CSR_ADDR_PHYS);
} else {
printk("PCI Host bridge init failed\n");
}
}
static void __init
ebony_setup_hose(void)
{
struct pci_controller *hose;
/* Configure windows on the PCI-X host bridge */
ebony_setup_pcix();
hose = pcibios_alloc_controller();
if (!hose)
return;
hose->first_busno = 0;
hose->last_busno = 0xff;
hose->pci_mem_offset = EBONY_PCI_MEM_OFFSET;
pci_init_resource(&hose->io_resource,
EBONY_PCI_LOWER_IO,
EBONY_PCI_UPPER_IO,
IORESOURCE_IO,
"PCI host bridge");
pci_init_resource(&hose->mem_resources[0],
EBONY_PCI_LOWER_MEM,
EBONY_PCI_UPPER_MEM,
IORESOURCE_MEM,
"PCI host bridge");
hose->io_space.start = EBONY_PCI_LOWER_IO;
hose->io_space.end = EBONY_PCI_UPPER_IO;
hose->mem_space.start = EBONY_PCI_LOWER_MEM;
hose->mem_space.end = EBONY_PCI_UPPER_MEM;
isa_io_base =
(unsigned long)ioremap64(EBONY_PCI_IO_BASE, EBONY_PCI_IO_SIZE);
hose->io_base_virt = (void *)isa_io_base;
setup_indirect_pci(hose,
EBONY_PCI_CFGA_PLB32,
EBONY_PCI_CFGD_PLB32);
hose->set_cfg_type = 1;
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = ebony_map_irq;
}
void __init prpmc750_find_bridges(void)
{
struct pci_controller *hose;
hose = pcibios_alloc_controller();
if (!hose)
return;
hose->first_busno = 0;
hose->last_busno = 0xff;
hose->io_base_virt = (void *)PRPMC750_ISA_IO_BASE;
hose->pci_mem_offset = PRPMC750_PCI_PHY_MEM_OFFSET;
pci_init_resource(&hose->io_resource,
PRPMC750_PCI_IO_START,
PRPMC750_PCI_IO_END,
IORESOURCE_IO, "PCI host bridge");
pci_init_resource(&hose->mem_resources[0],
PRPMC750_PROC_PCI_MEM_START,
PRPMC750_PROC_PCI_MEM_END,
IORESOURCE_MEM, "PCI host bridge");
hose->io_space.start = PRPMC750_PCI_IO_START;
hose->io_space.end = PRPMC750_PCI_IO_END;
hose->mem_space.start = PRPMC750_PCI_MEM_START;
hose->mem_space.end = PRPMC750_PCI_MEM_END - HAWK_MPIC_SIZE;
if (hawk_init(hose, PRPMC750_HAWK_PPC_REG_BASE,
PRPMC750_PROC_PCI_MEM_START,
PRPMC750_PROC_PCI_MEM_END - HAWK_MPIC_SIZE,
PRPMC750_PROC_PCI_IO_START, PRPMC750_PROC_PCI_IO_END,
PRPMC750_PROC_PCI_MEM_END - HAWK_MPIC_SIZE + 1)
!= 0) {
printk(KERN_CRIT "Could not initialize host bridge\n");
}
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pcibios_fixup = prpmc750_pcibios_fixup;
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = prpmc_map_irq;
}
void __init
mvme5100_setup_bridge(void)
{
struct pci_controller* hose;
hose = pcibios_alloc_controller();
if (!hose)
return;
hose->first_busno = 0;
hose->last_busno = 0xff;
hose->pci_mem_offset = MVME5100_PCI_MEM_OFFSET;
pci_init_resource(&hose->io_resource,
MVME5100_PCI_LOWER_IO,
MVME5100_PCI_UPPER_IO,
IORESOURCE_IO,
"PCI host bridge");
pci_init_resource(&hose->mem_resources[0],
MVME5100_PCI_LOWER_MEM,
MVME5100_PCI_UPPER_MEM,
IORESOURCE_MEM,
"PCI host bridge");
hose->io_space.start = MVME5100_PCI_LOWER_IO;
hose->io_space.end = MVME5100_PCI_UPPER_IO;
hose->mem_space.start = MVME5100_PCI_LOWER_MEM;
hose->mem_space.end = MVME5100_PCI_UPPER_MEM;
hose->io_base_virt = (void *)MVME5100_ISA_IO_BASE;
/* Use indirect method of Hawk */
setup_indirect_pci(hose,
MVME5100_PCI_CONFIG_ADDR,
MVME5100_PCI_CONFIG_DATA);
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pcibios_fixup_resources = mvme5100_pcibios_fixup_resources;
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = mvme5100_map_irq;
}
void __init
spruce_setup_hose(void)
{
struct pci_controller *hose;
/* Setup hose */
hose = pcibios_alloc_controller();
if (!hose)
return;
hose->first_busno = 0;
hose->last_busno = 0xff;
pci_init_resource(&hose->io_resource,
SPRUCE_PCI_LOWER_IO,
SPRUCE_PCI_UPPER_IO,
IORESOURCE_IO,
"PCI host bridge");
pci_init_resource(&hose->mem_resources[0],
SPRUCE_PCI_LOWER_MEM,
SPRUCE_PCI_UPPER_MEM,
IORESOURCE_MEM,
"PCI host bridge");
hose->io_space.start = SPRUCE_PCI_LOWER_IO;
hose->io_space.end = SPRUCE_PCI_UPPER_IO;
hose->mem_space.start = SPRUCE_PCI_LOWER_MEM;
hose->mem_space.end = SPRUCE_PCI_UPPER_MEM;
hose->io_base_virt = (void *)SPRUCE_ISA_IO_BASE;
setup_indirect_pci(hose,
SPRUCE_PCI_CONFIG_ADDR,
SPRUCE_PCI_CONFIG_DATA);
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = spruce_map_irq;
}
void __init
pal4_find_bridges(void)
{
struct pci_controller *hose;
hose = pcibios_alloc_controller();
if (!hose)
return;
hose->first_busno = 0;
hose->last_busno = 0xff;
hose->pci_mem_offset = 0;
/* Could snatch these from the CPC700.... */
pci_init_resource(&hose->io_resource,
0x0,
0x03ffffff,
IORESOURCE_IO,
"PCI host bridge");
pci_init_resource(&hose->mem_resources[0],
0x90000000,
0x9fffffff,
IORESOURCE_MEM,
"PCI host bridge");
hose->io_space.start = 0x00800000;
hose->io_space.end = 0x03ffffff;
hose->mem_space.start = 0x90000000;
hose->mem_space.end = 0x9fffffff;
hose->io_base_virt = (void *) 0xf8000000;
setup_indirect_pci(hose, CPC700_PCI_CONFIG_ADDR,
CPC700_PCI_CONFIG_DATA);
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = pal4_map_irq;
}
static void __init
luan_setup_hose(struct pci_controller *hose,
int lower_mem,
int upper_mem,
int cfga,
int cfgd,
u64 pcix_io_base)
{
char name[20];
sprintf(name, "PCIX%d host bridge", hose->index);
hose->pci_mem_offset = LUAN_PCIX_MEM_OFFSET;
pci_init_resource(&hose->io_resource,
LUAN_PCIX_LOWER_IO,
LUAN_PCIX_UPPER_IO,
IORESOURCE_IO,
name);
pci_init_resource(&hose->mem_resources[0],
lower_mem,
upper_mem,
IORESOURCE_MEM,
name);
hose->io_space.start = LUAN_PCIX_LOWER_IO;
hose->io_space.end = LUAN_PCIX_UPPER_IO;
hose->mem_space.start = lower_mem;
hose->mem_space.end = upper_mem;
isa_io_base =
(unsigned long)ioremap64(pcix_io_base, PCIX_IO_SIZE);
hose->io_base_virt = (void *)isa_io_base;
setup_indirect_pci(hose, cfga, cfgd);
hose->set_cfg_type = 1;
}
void __init
mpc83xx_setup_hose(void)
{
u32 val32;
volatile immr_clk_t * clk;
struct pci_controller * hose1;
#ifdef CONFIG_MPC83xx_PCI2
struct pci_controller * hose2;
#endif
bd_t * binfo = (bd_t *)__res;
clk = ioremap(binfo->bi_immr_base + 0xA00,
sizeof(immr_clk_t));
/*
* Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
*/
val32 = clk->occr;
udelay(2000);
clk->occr = 0xff000000;
udelay(2000);
iounmap(clk);
hose1 = pcibios_alloc_controller();
if(!hose1)
return;
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = mpc83xx_map_irq;
hose1->bus_offset = 0;
hose1->first_busno = 0;
hose1->last_busno = 0xff;
setup_indirect_pci(hose1, binfo->bi_immr_base + PCI1_CFG_ADDR_OFFSET,
binfo->bi_immr_base + PCI1_CFG_DATA_OFFSET);
hose1->set_cfg_type = 1;
mpc83xx_setup_pci1(hose1);
hose1->pci_mem_offset = MPC83xx_PCI1_MEM_OFFSET;
hose1->mem_space.start = MPC83xx_PCI1_LOWER_MEM;
hose1->mem_space.end = MPC83xx_PCI1_UPPER_MEM;
hose1->io_base_phys = MPC83xx_PCI1_IO_BASE;
hose1->io_space.start = MPC83xx_PCI1_LOWER_IO;
hose1->io_space.end = MPC83xx_PCI1_UPPER_IO;
#ifdef CONFIG_MPC83xx_PCI2
isa_io_base = (unsigned long)ioremap(MPC83xx_PCI1_IO_BASE,
MPC83xx_PCI1_IO_SIZE + MPC83xx_PCI2_IO_SIZE);
#else
isa_io_base = (unsigned long)ioremap(MPC83xx_PCI1_IO_BASE,
MPC83xx_PCI1_IO_SIZE);
#endif /* CONFIG_MPC83xx_PCI2 */
hose1->io_base_virt = (void *)isa_io_base;
/* setup resources */
pci_init_resource(&hose1->io_resource,
MPC83xx_PCI1_LOWER_IO,
MPC83xx_PCI1_UPPER_IO,
IORESOURCE_IO, "PCI host bridge 1");
pci_init_resource(&hose1->mem_resources[0],
MPC83xx_PCI1_LOWER_MEM,
MPC83xx_PCI1_UPPER_MEM,
IORESOURCE_MEM, "PCI host bridge 1");
ppc_md.pci_exclude_device = mpc83xx_exclude_device;
hose1->last_busno = pciauto_bus_scan(hose1, hose1->first_busno);
#ifdef CONFIG_MPC83xx_PCI2
hose2 = pcibios_alloc_controller();
if(!hose2)
return;
hose2->bus_offset = hose1->last_busno + 1;
hose2->first_busno = hose1->last_busno + 1;
hose2->last_busno = 0xff;
setup_indirect_pci(hose2, binfo->bi_immr_base + PCI2_CFG_ADDR_OFFSET,
binfo->bi_immr_base + PCI2_CFG_DATA_OFFSET);
hose2->set_cfg_type = 1;
mpc83xx_setup_pci2(hose2);
hose2->pci_mem_offset = MPC83xx_PCI2_MEM_OFFSET;
hose2->mem_space.start = MPC83xx_PCI2_LOWER_MEM;
hose2->mem_space.end = MPC83xx_PCI2_UPPER_MEM;
hose2->io_base_phys = MPC83xx_PCI2_IO_BASE;
hose2->io_space.start = MPC83xx_PCI2_LOWER_IO;
hose2->io_space.end = MPC83xx_PCI2_UPPER_IO;
hose2->io_base_virt = (void *)(isa_io_base + MPC83xx_PCI1_IO_SIZE);
/* setup resources */
pci_init_resource(&hose2->io_resource,
MPC83xx_PCI2_LOWER_IO,
MPC83xx_PCI2_UPPER_IO,
IORESOURCE_IO, "PCI host bridge 2");
pci_init_resource(&hose2->mem_resources[0],
MPC83xx_PCI2_LOWER_MEM,
MPC83xx_PCI2_UPPER_MEM,
IORESOURCE_MEM, "PCI host bridge 2");
hose2->last_busno = pciauto_bus_scan(hose2, hose2->first_busno);
#endif /* CONFIG_MPC83xx_PCI2 */
}
void __init
mpc85xx_setup_hose(void)
{
struct pci_controller *hose_a;
#ifdef CONFIG_85xx_PCI2
struct pci_controller *hose_b;
#endif
bd_t *binfo = (bd_t *) __res;
hose_a = pcibios_alloc_controller();
if (!hose_a)
return;
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = mpc85xx_map_irq;
hose_a->first_busno = 0;
hose_a->bus_offset = 0;
hose_a->last_busno = 0xff;
setup_indirect_pci(hose_a, binfo->bi_immr_base + PCI1_CFG_ADDR_OFFSET,
binfo->bi_immr_base + PCI1_CFG_DATA_OFFSET);
hose_a->set_cfg_type = 1;
mpc85xx_setup_pci1(hose_a);
hose_a->pci_mem_offset = MPC85XX_PCI1_MEM_OFFSET;
hose_a->mem_space.start = MPC85XX_PCI1_LOWER_MEM;
hose_a->mem_space.end = MPC85XX_PCI1_UPPER_MEM;
hose_a->io_space.start = MPC85XX_PCI1_LOWER_IO;
hose_a->io_space.end = MPC85XX_PCI1_UPPER_IO;
hose_a->io_base_phys = MPC85XX_PCI1_IO_BASE;
#ifdef CONFIG_85xx_PCI2
hose_a->io_base_virt = ioremap(MPC85XX_PCI1_IO_BASE,
MPC85XX_PCI1_IO_SIZE +
MPC85XX_PCI2_IO_SIZE);
#else
hose_a->io_base_virt = ioremap(MPC85XX_PCI1_IO_BASE,
MPC85XX_PCI1_IO_SIZE);
#endif
isa_io_base = (unsigned long)hose_a->io_base_virt;
/* setup resources */
pci_init_resource(&hose_a->mem_resources[0],
MPC85XX_PCI1_LOWER_MEM,
MPC85XX_PCI1_UPPER_MEM,
IORESOURCE_MEM, "PCI1 host bridge");
pci_init_resource(&hose_a->io_resource,
MPC85XX_PCI1_LOWER_IO,
MPC85XX_PCI1_UPPER_IO,
IORESOURCE_IO, "PCI1 host bridge");
ppc_md.pci_exclude_device = mpc85xx_exclude_device;
#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
/* Pre pciauto_bus_scan VIA init */
mpc85xx_cds_enable_via(hose_a);
#endif
hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno);
#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
/* Post pciauto_bus_scan VIA fixup */
mpc85xx_cds_fixup_via(hose_a);
#endif
#ifdef CONFIG_85xx_PCI2
hose_b = pcibios_alloc_controller();
if (!hose_b)
return;
hose_b->bus_offset = hose_a->last_busno + 1;
hose_b->first_busno = hose_a->last_busno + 1;
hose_b->last_busno = 0xff;
setup_indirect_pci(hose_b, binfo->bi_immr_base + PCI2_CFG_ADDR_OFFSET,
binfo->bi_immr_base + PCI2_CFG_DATA_OFFSET);
hose_b->set_cfg_type = 1;
mpc85xx_setup_pci2(hose_b);
hose_b->pci_mem_offset = MPC85XX_PCI2_MEM_OFFSET;
hose_b->mem_space.start = MPC85XX_PCI2_LOWER_MEM;
hose_b->mem_space.end = MPC85XX_PCI2_UPPER_MEM;
hose_b->io_space.start = MPC85XX_PCI2_LOWER_IO;
hose_b->io_space.end = MPC85XX_PCI2_UPPER_IO;
hose_b->io_base_phys = MPC85XX_PCI2_IO_BASE;
hose_b->io_base_virt = hose_a->io_base_virt + MPC85XX_PCI1_IO_SIZE;
/* setup resources */
pci_init_resource(&hose_b->mem_resources[0],
MPC85XX_PCI2_LOWER_MEM,
MPC85XX_PCI2_UPPER_MEM,
IORESOURCE_MEM, "PCI2 host bridge");
pci_init_resource(&hose_b->io_resource,
MPC85XX_PCI2_LOWER_IO,
MPC85XX_PCI2_UPPER_IO,
IORESOURCE_IO, "PCI2 host bridge");
hose_b->last_busno = pciauto_bus_scan(hose_b, hose_b->first_busno);
/* let board code know what the last bus number was on PCI1 */
mpc85xx_pci1_last_busno = hose_a->last_busno;
#endif
return;
}
static void __init
yucca_setup_hoses(void)
{
struct pci_controller *hose;
char name[20];
enum yucca_hoses hs;
int bus_no = 0;
for (hs = HOSE_PCIX; hs < HOSE_MAX; ++hs) {
if (is_pcie_hose(hs)) {
if (!yucca_pcie_card_present(pcie_hose_num(hs)))
continue;
pr_debug("PCIE%d: card present\n", pcie_hose_num(hs));
yucca_setup_pcie_fpga_root_or_endpoint(pcie_hose_num(hs));
if (ppc440spe_init_pcie_root_or_endport(pcie_hose_num(hs))) {
printk(KERN_ERR "PCIE%d: initialization "
"failed\n", pcie_hose_num(hs));
continue;
}
}
hose = pcibios_alloc_controller();
if (!hose)
return;
sprintf(name, "PCI%s%d host bridge",
is_pcix_hose(hs) ? "X" : "E",
is_pcie_hose(hs) ? pcie_hose_num(hs) : 0
);
pci_init_resource(&hose->io_resource,
YUCCA_PCIX_LOWER_IO,
YUCCA_PCIX_UPPER_IO,
IORESOURCE_IO,
name);
if (is_pcix_hose(hs)) {
hose->mem_space.start = YUCCA_PCIX_LOWER_MEM;
hose->mem_space.end = hose->mem_space.start +
YUCCA_PCIX_MEM_SIZE - 1;
} else {
hose->mem_space.start = YUCCA_PCIE_LOWER_MEM +
pcie_hose_num(hs) * YUCCA_PCIE_MEM_SIZE;
hose->mem_space.end = hose->mem_space.start +
YUCCA_PCIE_MEM_SIZE - 1;
}
pci_init_resource(&hose->mem_resources[0],
hose->mem_space.start,
hose->mem_space.end,
IORESOURCE_MEM,
name);
hose->first_busno = bus_no;
hose->last_busno = 0xFF;
hose_type[hose->index] = hs;
if (is_pcix_hose(hs)) {
hose->io_space.start = YUCCA_PCIX_LOWER_IO;
hose->io_space.end = YUCCA_PCIX_UPPER_IO;
isa_io_base =
(unsigned long)
ioremap64(PCIX0_IO_BASE, PCIX_IO_SIZE);
hose->io_base_virt = (void *)isa_io_base;
ppc440spe_setup_pcix(hose);
setup_indirect_pci(hose, PCIX0_CFGA, PCIX0_CFGD);
hose->set_cfg_type = 1;
} else {
if(ppc440spe_setup_pcie(hose, pcie_hose_num(hs)) != 0)
{
printk(KERN_WARNING"PCIE setup failed for hose no %d\n",
pcie_hose_num(hs));
continue;
}
}
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
bus_no = hose->last_busno + 1;
pr_debug("%s: resources allocated\n", name);
}
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = yucca_map_irq;
}
void __init
mpc83xx_setup_hose(void)
{
u32 val32;
volatile immr_clk_t * clk;
volatile law_t * pci_law;
struct pci_controller * hose1;
#ifdef CONFIG_MPC83xx_PCI2
struct pci_controller * hose2;
#endif
bd_t * binfo = (bd_t *)__res;
u8 val8;
clk = ioremap(binfo->bi_immr_base + 0xA00, sizeof(immr_clk_t));
pci_law = ioremap(binfo->bi_immr_base + 0x60, sizeof(law_t));
/* Configure PCI clock drivers */
val32 = clk->occr;
udelay(2000);
#ifdef CONFIG_CLK_DIV_ENABLE
clk->occr = 0xffff0003;
#else
clk->occr = 0xff000000;
#endif
udelay(2000);
iounmap(clk);
/*
* Configure PCI Local Access Windows
*/
pci_law[0].bar = MPC83xx_PCI1_LOWER_MEM & LAWBAR_BAR;
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
pci_law[1].bar = MPC83xx_PCI1_IO_BASE & LAWBAR_BAR;
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;
iounmap(pci_law);
#ifndef CONFIG_MPC834x_ITX
/*
* Configure PMC <-> PCI by I2C bus
*/
early_i2c_init(CFG_I2C_SPD,CFG_I2C_SLV);
val8 = 0;
early_i2c_write(0x23,0x6,1,&val8,1);
early_i2c_write(0x23,0x7,1,&val8,1);
val8 = 0xff;
early_i2c_write(0x23,0x2,1,&val8,1);
early_i2c_write(0x23,0x3,1,&val8,1);
val8 = 0;
early_i2c_write(0x26,0x6,1,&val8,1);
val8 = 0x34;
early_i2c_write(0x26,0x7,1,&val8,1);
#ifdef CONFIG_PCI_64BIT
val8 = 0xf4; /* 64bit PMC2<->PCI1 */
#elif defined(CONFIG_PCI_ONE_PCI1) || defined(CONFIG_MPC832XE_MDS)
val8 = 0xf9; /* 32bit PMC1<->PCI1,PMC2<->PCI2,PMC3<->PCI2 */
#elif defined(CONFIG_PCI_TWO_PCI1) || defined(CONFIG_MPC8360E_PB)
val8 = 0xf7; /* 32bit PMC1<->PCI1,PMC2<->PCI1 PCM3<->PCI2 disabled*/
#else
val8 = 0xf3; /* 32bit PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI1 */
#endif
early_i2c_write(0x26,0x2,1,&val8,1);
val8 = 0xff;
early_i2c_write(0x26,0x3,1,&val8,1);
val8 = 0;
early_i2c_write(0x27,0x6,1,&val8,1);
early_i2c_write(0x27,0x7,1,&val8,1);
val8 = 0xff;
early_i2c_write(0x27,0x2,1,&val8,1);
val8 = 0xef;
early_i2c_write(0x27,0x3,1,&val8,1);
asm("eieio");
#endif /* CONFIG_MPC834x_ITX */
hose1 = pcibios_alloc_controller();
if(!hose1)
return;
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = mpc83xx_map_irq;
hose1->bus_offset = 0;
hose1->first_busno = 0;
hose1->last_busno = 0xff;
setup_indirect_pci(hose1, binfo->bi_immr_base + PCI1_CFG_ADDR_OFFSET,
binfo->bi_immr_base + PCI1_CFG_DATA_OFFSET);
hose1->ops = &mpc83xx_indirect_pci_ops;
mpc83xx_setup_pci1(hose1);
hose1->pci_mem_offset = MPC83xx_PCI1_MEM_OFFSET;
hose1->mem_space.start = MPC83xx_PCI1_LOWER_MEM;
hose1->mem_space.end = MPC83xx_PCI1_UPPER_MEM;
hose1->io_base_phys = MPC83xx_PCI1_IO_BASE;
hose1->io_space.start = MPC83xx_PCI1_LOWER_IO;
hose1->io_space.end = MPC83xx_PCI1_UPPER_IO;
#ifdef CONFIG_MPC83xx_PCI2
isa_io_base = (unsigned long)ioremap(MPC83xx_PCI1_IO_BASE,
MPC83xx_PCI1_IO_SIZE + MPC83xx_PCI2_IO_SIZE);
#else
isa_io_base = (unsigned long)ioremap(MPC83xx_PCI1_IO_BASE,
MPC83xx_PCI1_IO_SIZE);
#endif /* CONFIG_MPC83xx_PCI2 */
hose1->io_base_virt = (void *)isa_io_base;
/* setup resources */
pci_init_resource(&hose1->io_resource,
MPC83xx_PCI1_LOWER_IO,
MPC83xx_PCI1_UPPER_IO,
IORESOURCE_IO, "PCI host bridge 1");
pci_init_resource(&hose1->mem_resources[0],
MPC83xx_PCI1_LOWER_MEM,
MPC83xx_PCI1_UPPER_MEM,
IORESOURCE_MEM, "PCI host bridge 1");
ppc_md.pci_exclude_device = mpc83xx_exclude_device;
hose1->last_busno = pciauto_bus_scan(hose1, hose1->first_busno);
#ifdef CONFIG_MPC83xx_PCI2
hose2 = pcibios_alloc_controller();
if(!hose2)
return;
hose2->bus_offset = hose1->last_busno + 1;
hose2->first_busno = hose1->last_busno + 1;
hose2->last_busno = 0xff;
setup_indirect_pci(hose2, binfo->bi_immr_base + PCI2_CFG_ADDR_OFFSET,
binfo->bi_immr_base + PCI2_CFG_DATA_OFFSET);
hose2->ops = &mpc83xx_indirect_pci_ops;
mpc83xx_setup_pci2(hose2);
hose2->pci_mem_offset = MPC83xx_PCI2_MEM_OFFSET;
hose2->mem_space.start = MPC83xx_PCI2_LOWER_MEM;
hose2->mem_space.end = MPC83xx_PCI2_UPPER_MEM;
hose2->io_base_phys = MPC83xx_PCI2_IO_BASE;
hose2->io_space.start = MPC83xx_PCI2_LOWER_IO;
hose2->io_space.end = MPC83xx_PCI2_UPPER_IO;
hose2->io_base_virt = (void *)(isa_io_base + MPC83xx_PCI1_IO_SIZE);
/* setup resources */
pci_init_resource(&hose2->io_resource,
MPC83xx_PCI2_LOWER_IO,
MPC83xx_PCI2_UPPER_IO,
IORESOURCE_IO, "PCI host bridge 2");
pci_init_resource(&hose2->mem_resources[0],
MPC83xx_PCI2_LOWER_MEM,
MPC83xx_PCI2_UPPER_MEM,
IORESOURCE_MEM, "PCI host bridge 2");
hose2->last_busno = pciauto_bus_scan(hose2, hose2->first_busno);
#endif /* CONFIG_MPC83xx_PCI2 */
}
void __init
mcpn765_find_bridges(void)
{
struct pci_controller *hose;
hose = pcibios_alloc_controller();
if (!hose)
return;
hose->first_busno = 0;
hose->last_busno = 0xff;
hose->pci_mem_offset = MCPN765_PCI_PHY_MEM_OFFSET;
pci_init_resource(&hose->io_resource,
MCPN765_PCI_IO_START,
MCPN765_PCI_IO_END,
IORESOURCE_IO,
"PCI host bridge");
pci_init_resource(&hose->mem_resources[0],
MCPN765_PCI_MEM_START,
MCPN765_PCI_MEM_END,
IORESOURCE_MEM,
"PCI host bridge");
hose->io_space.start = MCPN765_PCI_IO_START;
hose->io_space.end = MCPN765_PCI_IO_END;
hose->mem_space.start = MCPN765_PCI_MEM_START;
hose->mem_space.end = MCPN765_PCI_MEM_END - HAWK_MPIC_SIZE;
if (hawk_init(hose,
MCPN765_HAWK_PPC_REG_BASE,
MCPN765_PROC_PCI_MEM_START,
MCPN765_PROC_PCI_MEM_END - HAWK_MPIC_SIZE,
MCPN765_PROC_PCI_IO_START,
MCPN765_PROC_PCI_IO_END,
MCPN765_PCI_MEM_END - HAWK_MPIC_SIZE + 1) != 0) {
printk("Could not initialize HAWK bridge\n");
}
/* VIA IDE BAR decoders are only 16-bits wide. PCI Auto Config
* will reassign the bars outside of 16-bit I/O space, which will
* "break" things. To prevent this, we'll set the IDE chip into
* legacy mode and seed the bars with their legacy addresses (in 16-bit
* I/O space). The Auto Config code will skip the IDE contoller in
* legacy mode, so our bar values will stick.
*/
mcpn765_set_VIA_IDE_legacy();
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
/* Now that we've got 16-bit addresses in the bars, we can switch the
* IDE controller back into native mode so we can do "modern" resource
* and interrupt management.
*/
mcpn765_set_VIA_IDE_native();
ppc_md.pcibios_fixup = mcpn765_pcibios_fixup;
ppc_md.pcibios_fixup_bus = NULL;
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = mcpn765_map_irq;
return;
}
