static void shpc_interrupt_update(PCIDevice *d) { SHPCDevice *shpc = d->shpc; int slot; int level = 0; uint32_t serr_int; uint32_t int_locator = 0; /* Update interrupt locator register */ for (slot = 0; slot < shpc->nslots; ++slot) { uint8_t event = shpc->config[SHPC_SLOT_EVENT_LATCH(slot)]; uint8_t disable = shpc->config[SHPC_SLOT_EVENT_SERR_INT_DIS(d, slot)]; uint32_t mask = 1U << SHPC_IDX_TO_LOGICAL(slot); if (event & ~disable) { int_locator |= mask; } } serr_int = pci_get_long(shpc->config + SHPC_SERR_INT); if ((serr_int & SHPC_CMD_DETECTED) && !(serr_int & SHPC_CMD_INT_DIS)) { int_locator |= SHPC_INT_COMMAND; } pci_set_long(shpc->config + SHPC_INT_LOCATOR, int_locator); level = (!(serr_int & SHPC_INT_DIS) && int_locator) ? 1 : 0; if (msi_enabled(d) && shpc->msi_requested != level) msi_notify(d, 0); else pci_set_irq(d, level); shpc->msi_requested = level; }
static void edu_raise_irq(EduState *edu, uint32_t val) { edu->irq_status |= val; if (edu->irq_status) { pci_set_irq(&edu->pdev, 1); } }
static void ivshmem_update_irq(IVShmemState *s) { PCIDevice *d = PCI_DEVICE(s); uint32_t isr = s->intrstatus & s->intrmask; /* * Do nothing unless the device actually uses INTx. Here's how * the device variants signal interrupts, what they put in PCI * config space: * Device variant Interrupt Interrupt Pin MSI-X cap. * ivshmem-plain none 0 no * ivshmem-doorbell MSI-X 1 yes(1) * ivshmem,msi=off INTx 1 no * ivshmem,msi=on MSI-X 1(2) yes(1) * (1) if guest enabled MSI-X * (2) the device lies * Leads to the condition for doing nothing: */ if (ivshmem_has_feature(s, IVSHMEM_MSI) || !d->config[PCI_INTERRUPT_PIN]) { return; } /* don't print ISR resets */ if (isr) { IVSHMEM_DPRINTF("Set IRQ to %d (%04x %04x)\n", isr ? 1 : 0, s->intrstatus, s->intrmask); } pci_set_irq(d, isr != 0); }
static void edu_lower_irq(EduState *edu, uint32_t val) { edu->irq_status &= ~val; if (!edu->irq_status) { pci_set_irq(&edu->pdev, 0); } }
static void vigs_update_irq(VIGSState *s) { bool raise = false; if ((s->reg_con & VIGS_REG_CON_VBLANK_ENABLE) && (s->reg_int & VIGS_REG_INT_VBLANK_PENDING)) { raise = true; } if (s->reg_int & VIGS_REG_INT_FENCE_ACK_PENDING) { raise = true; } if (raise) { pci_set_irq(&s->dev.pci_dev, 1); } else { pci_set_irq(&s->dev.pci_dev, 0); } }
/* Update IRQ levels */ static inline void ohci_intr_update(OHCIState *ohci) { int level = 0; if ((ohci->intr & OHCI_INTR_MIE) && (ohci->intr_status & ohci->intr)) level = 1; pci_set_irq(&ohci->pci_dev, 0, level); }
static void edu_raise_irq(EduState *edu, uint32_t val) { edu->irq_status |= val; if (edu->irq_status) { if (edu_msi_enabled(edu)) { msi_notify(&edu->pdev, 0); } else { pci_set_irq(&edu->pdev, 1); } } }
/* XXX: call it also when the MRDMODE is changed from the PCI config registers */ static void cmd646_update_irq(PCIIDEState *d) { PCIDevice *pd = PCI_DEVICE(d); int pci_level; pci_level = ((pd->config[MRDMODE] & MRDMODE_INTR_CH0) && !(pd->config[MRDMODE] & MRDMODE_BLK_CH0)) || ((pd->config[MRDMODE] & MRDMODE_INTR_CH1) && !(pd->config[MRDMODE] & MRDMODE_BLK_CH1)); pci_set_irq(pd, pci_level); }
void bx_piix3_c::pci_unregister_irq(unsigned pirq) { Bit8u irq = BX_P2I_THIS s.pci_conf[0x60 + pirq]; if (irq < 16) { BX_P2I_THIS s.irq_registry[irq] &= ~(1 << pirq); if (!BX_P2I_THIS s.irq_registry[irq]) { BX_P2I_THIS pci_set_irq(0x08, pirq+1, 0); DEV_unregister_irq(irq, "PIIX3 IRQ routing"); } BX_P2I_THIS s.pci_conf[0x60 + pirq] = 0x80; } }
static void multi_serial_irq_mux(void *opaque, int n, int level) { PCIMultiSerialState *pci = opaque; int i, pending = 0; pci->level[n] = level; for (i = 0; i < pci->ports; i++) { if (pci->level[i]) { pending = 1; } } pci_set_irq(&pci->dev, pending); }
/* accessing registers - based on rtl8139 */ static void ivshmem_update_irq(IVShmemState *s, int val) { PCIDevice *d = PCI_DEVICE(s); int isr; isr = (s->intrstatus & s->intrmask) & 0xffffffff; /* don't print ISR resets */ if (isr) { IVSHMEM_DPRINTF("Set IRQ to %d (%04x %04x)\n", isr ? 1 : 0, s->intrstatus, s->intrmask); } pci_set_irq(d, (isr != 0)); }
static void vigs_device_reset(DeviceState *d) { VIGSState *s = container_of(d, VIGSState, dev.pci_dev.qdev); vigs_server_reset(s->server); vigs_fenceman_reset(s->fenceman); pci_set_irq(&s->dev.pci_dev, 0); s->reg_con = 0; s->reg_int = 0; VIGS_LOG_INFO("VIGS reset"); }
void bx_piix3_c::reset(unsigned type) { BX_P2I_THIS s.pci_conf[0x05] = 0x00; BX_P2I_THIS s.pci_conf[0x06] = 0x00; BX_P2I_THIS s.pci_conf[0x07] = 0x02; BX_P2I_THIS s.pci_conf[0x4c] = 0x4d; BX_P2I_THIS s.pci_conf[0x4e] = 0x03; BX_P2I_THIS s.pci_conf[0x4f] = 0x00; BX_P2I_THIS s.pci_conf[0x69] = 0x02; BX_P2I_THIS s.pci_conf[0x70] = 0x80; BX_P2I_THIS s.pci_conf[0x76] = 0x0c; BX_P2I_THIS s.pci_conf[0x77] = 0x0c; BX_P2I_THIS s.pci_conf[0x78] = 0x02; BX_P2I_THIS s.pci_conf[0x79] = 0x00; BX_P2I_THIS s.pci_conf[0x80] = 0x00; BX_P2I_THIS s.pci_conf[0x82] = 0x00; BX_P2I_THIS s.pci_conf[0xa0] = 0x08; BX_P2I_THIS s.pci_conf[0xa2] = 0x00; BX_P2I_THIS s.pci_conf[0xa3] = 0x00; BX_P2I_THIS s.pci_conf[0xa4] = 0x00; BX_P2I_THIS s.pci_conf[0xa5] = 0x00; BX_P2I_THIS s.pci_conf[0xa6] = 0x00; BX_P2I_THIS s.pci_conf[0xa7] = 0x00; BX_P2I_THIS s.pci_conf[0xa8] = 0x0f; BX_P2I_THIS s.pci_conf[0xaa] = 0x00; BX_P2I_THIS s.pci_conf[0xab] = 0x00; BX_P2I_THIS s.pci_conf[0xac] = 0x00; BX_P2I_THIS s.pci_conf[0xae] = 0x00; for (unsigned i = 0; i < 4; i++) { pci_set_irq(0x08, i+1, 0); pci_unregister_irq(i); } BX_P2I_THIS s.elcr1 = 0x00; BX_P2I_THIS s.elcr2 = 0x00; BX_P2I_THIS s.pci_reset = 0x00; BX_P2I_THIS s.apms = 0x00; BX_P2I_THIS s.apmc = 0x00; }
static void hotplug_event_notify(PCIDevice *dev) { bool prev = dev->exp.hpev_notified; hotplug_event_update_event_status(dev); if (prev == dev->exp.hpev_notified) { return; } /* Note: the logic above does not take into account whether interrupts * are masked. The result is that interrupt will be sent when it is * subsequently unmasked. This appears to be legal: Section 6.7.3.4: * The Port may optionally send an MSI when there are hot-plug events that * occur while interrupt generation is disabled, and interrupt generation is * subsequently enabled. */ if (msix_enabled(dev)) { msix_notify(dev, pcie_cap_flags_get_vector(dev)); } else if (msi_enabled(dev)) { msi_notify(dev, pcie_cap_flags_get_vector(dev)); } else { pci_set_irq(dev, dev->exp.hpev_notified); } }