int __init pci_visws_init(void)
{
if (!is_visws_box())
return -1;
pcibios_enable_irq = &pci_visws_enable_irq;
pcibios_disable_irq = &pci_visws_disable_irq;
/* The VISWS supports configuration access type 1 only */
pci_probe = (pci_probe | PCI_PROBE_CONF1) &
~(PCI_PROBE_BIOS | PCI_PROBE_CONF2);
pci_bus0 = li_pcib_read16(LI_PCI_BUSNUM) & 0xff;
pci_bus1 = li_pcia_read16(LI_PCI_BUSNUM) & 0xff;
printk(KERN_INFO "PCI: Lithium bridge A bus: %u, "
"bridge B (PIIX4) bus: %u\n", pci_bus1, pci_bus0);
raw_pci_ops = &pci_direct_conf1;
pci_scan_bus_with_sysdata(pci_bus0);
pci_scan_bus_with_sysdata(pci_bus1);
pci_fixup_irqs(visws_swizzle, visws_map_irq);
pcibios_resource_survey();
return 0;
}
static int __init l4vpci_x86_init(void)
{
struct pci_dev *dev = NULL;
struct pci_bus *bus;
struct pci_sysdata *sd = kzalloc(sizeof(*sd), GFP_KERNEL);
if (!sd)
return -ENOMEM;
bus = pci_scan_bus(0, &l4vpci_ops, sd);
if (!bus) {
pr_err("Failed to scan PCI bus\n");
return -ENODEV;
}
pci_bus_add_devices(bus);
pr_info("l4vPCI: Using L4-IO for IRQ routing\n");
for_each_pci_dev(dev)
l4vpci_irq_enable(dev);
pcibios_resource_survey();
return 0;
}
/*
* Initialization. Try all known PCI access methods. Note that we support
* using both PCI BIOS and direct access: in such cases, we use I/O ports
* to access config space, but we still keep BIOS order of cards to be
* compatible with 2.0.X. This should go away some day.
*/
static int __init pcibios_init(void)
{
ioport_resource.start = 0xA0000000;
ioport_resource.end = 0xDFFFFFFF;
iomem_resource.start = 0xA0000000;
iomem_resource.end = 0xDFFFFFFF;
if (insert_resource(&iomem_resource, &pci_iomem_resource) < 0)
panic("Unable to insert PCI IOMEM resource\n");
if (insert_resource(&ioport_resource, &pci_ioport_resource) < 0)
panic("Unable to insert PCI IOPORT resource\n");
if (!pci_probe)
return 0;
if (pci_check_direct() < 0) {
printk(KERN_WARNING "PCI: No PCI bus detected\n");
return 0;
}
printk(KERN_INFO "PCI: Probing PCI hardware [mempage %08x]\n",
MEM_PAGING_REG);
pci_root_bus = pci_scan_bus(0, &pci_direct_ampci, NULL);
pcibios_irq_init();
pcibios_fixup_irqs();
pcibios_resource_survey();
return 0;
}
static int __init l4vpci_init(void)
{
struct pci_dev *dev = NULL;
#ifdef CONFIG_ARM
struct pci_sys_data *sd;
#else
struct pci_sysdata *sd;
#endif
int err;
L4XV_V(f);
vbus = l4re_get_env_cap("vbus");
if (l4_is_invalid_cap(vbus))
return -ENOENT;
L4XV_L(f);
err = l4vbus_get_device_by_hid(vbus, 0, &root_bridge, "PNP0A03", 0, 0);
if (err < 0) {
printk(KERN_INFO "PCI: no root bridge found, no PCI\n");
L4XV_U(f);
return err;
}
L4XV_U(f);
printk(KERN_INFO "PCI: L4 root bridge is device %lx\n", root_bridge);
sd = kzalloc(sizeof(*sd), GFP_KERNEL);
if (!sd)
return -ENOMEM;
pci_scan_bus(0, &l4vpci_ops, sd);
printk(KERN_INFO "PCI: Using L4-IO for IRQ routing\n");
for_each_pci_dev(dev)
l4vpci_irq_enable(dev);
#ifdef CONFIG_X86
pcibios_resource_survey();
#endif
return 0;
}
static int __init pcibios_init(void)
{
/* The VISWS supports configuration access type 1 only */
pci_probe = (pci_probe | PCI_PROBE_CONF1) &
~(PCI_PROBE_BIOS | PCI_PROBE_CONF2);
pci_bus0 = li_pcib_read16(LI_PCI_BUSNUM) & 0xff;
pci_bus1 = li_pcia_read16(LI_PCI_BUSNUM) & 0xff;
printk(KERN_INFO "PCI: Lithium bridge A bus: %u, "
"bridge B (PIIX4) bus: %u\n", pci_bus1, pci_bus0);
raw_pci_ops = &pci_direct_conf1;
pci_scan_bus(pci_bus0, &pci_root_ops, NULL);
pci_scan_bus(pci_bus1, &pci_root_ops, NULL);
pci_fixup_irqs(visws_swizzle, visws_map_irq);
pcibios_resource_survey();
return 0;
}
/*
* Initialization. Try all known PCI access methods. Note that we support
* using both PCI BIOS and direct access: in such cases, we use I/O ports
* to access config space, but we still keep BIOS order of cards to be
* compatible with 2.0.X. This should go away some day.
*/
static int __init pcibios_init(void)
{
resource_size_t io_offset, mem_offset;
LIST_HEAD(resources);
struct pci_bus *bus;
ioport_resource.start = 0xA0000000;
ioport_resource.end = 0xDFFFFFFF;
iomem_resource.start = 0xA0000000;
iomem_resource.end = 0xDFFFFFFF;
if (insert_resource(&iomem_resource, &pci_iomem_resource) < 0)
panic("Unable to insert PCI IOMEM resource\n");
if (insert_resource(&ioport_resource, &pci_ioport_resource) < 0)
panic("Unable to insert PCI IOPORT resource\n");
if (!pci_probe)
return 0;
if (pci_check_direct() < 0) {
printk(KERN_WARNING "PCI: No PCI bus detected\n");
return 0;
}
printk(KERN_INFO "PCI: Probing PCI hardware [mempage %08x]\n",
MEM_PAGING_REG);
io_offset = pci_ioport_resource.start -
(pci_ioport_resource.start & 0x00ffffff);
mem_offset = pci_iomem_resource.start -
((pci_iomem_resource.start & 0x03ffffff) | MEM_PAGING_REG);
pci_add_resource_offset(&resources, &pci_ioport_resource, io_offset);
pci_add_resource_offset(&resources, &pci_iomem_resource, mem_offset);
bus = pci_scan_root_bus(NULL, 0, &pci_direct_ampci, NULL, &resources);
if (!bus)
return 0;
pcibios_resource_survey();
pci_bus_add_devices(bus);
return 0;
}
/*
* Initialization. Try all known PCI access methods. Note that we support
* using both PCI BIOS and direct access: in such cases, we use I/O ports
* to access config space, but we still keep BIOS order of cards to be
* compatible with 2.0.X. This should go away some day.
*/
static int __init pcibios_init(void)
{
ioport_resource.start = 0xA0000000;
ioport_resource.end = 0xDFFFFFFF;
iomem_resource.start = 0xA0000000;
iomem_resource.end = 0xDFFFFFFF;
if (!pci_probe)
return 0;
if (pci_check_direct() < 0) {
printk(KERN_WARNING "PCI: No PCI bus detected\n");
return 0;
}
printk(KERN_INFO "PCI: Probing PCI hardware [mempage %08x]\n",
MEM_PAGING_REG);
{
#if 0
static struct pci_bus am33_root_bus = {
.children = LIST_HEAD_INIT(am33_root_bus.children),
.devices = LIST_HEAD_INIT(am33_root_bus.devices),
.number = 0,
.secondary = 0,
.resource = { &ioport_resource, &iomem_resource },
};
am33_root_bus.ops = pci_root_ops;
list_add_tail(&am33_root_bus.node, &pci_root_buses);
am33_root_bus.subordinate = pci_do_scan_bus(0);
pci_root_bus = &am33_root_bus;
#else
pci_root_bus = pci_scan_bus(0, &pci_direct_ampci, NULL);
#endif
}
pcibios_irq_init();
pcibios_fixup_irqs();
#if 0
pcibios_resource_survey();
#endif
return 0;
}
arch_initcall(pcibios_init);
char *__init pcibios_setup(char *str)
{
if (!strcmp(str, "off")) {
pci_probe = 0;
return NULL;
} else if (!strncmp(str, "lastbus=", 8)) {
pcibios_last_bus = simple_strtol(str+8, NULL, 0);
return NULL;
}
return str;
}
int pcibios_enable_device(struct pci_dev *dev, int mask)
{
int err;
err = pcibios_enable_resources(dev, mask);
if (err == 0)
pcibios_enable_irq(dev);
return err;
}