static int isp_open(struct inode *inode, struct file *filp)
{
int ret = 0;
struct isp_t *dev = kmalloc(sizeof(struct isp_t), GFP_KERNEL);
if (!dev)
return -ENOMEM;
filp->private_data = dev;
spin_lock_init(&dev->lock);
dev->isp_status.status = 0;
init_completion(&dev->irq_sem);
ret =
pi_mgr_dfs_add_request(&isp_dfs_node, "isp", PI_MGR_PI_ID_MM,
PI_MGR_DFS_MIN_VALUE);
if (ret) {
printk(KERN_ERR "%s: failed to register PI DFS request\n",
__func__);
goto err;
}
ret = pi_mgr_qos_add_request(&isp_qos_node, "isp",
PI_MGR_PI_ID_ARM_CORE,
PI_MGR_QOS_DEFAULT_VALUE);
if (ret) {
printk(KERN_ERR "%s: failed to register PI QOS request\n",
__func__);
ret = -EIO;
goto qos_request_fail;
}
enable_isp_clock();
pi_mgr_qos_request_update(&isp_qos_node, 0);
scu_standby(0);
ret =
request_irq(IRQ_ISP, isp_isr, IRQF_DISABLED | IRQF_SHARED,
ISP_DEV_NAME, dev);
if (ret) {
err_print("request_irq failed ret = %d\n", ret);
goto err;
}
/* Ensure that only one CORE handles interrupt for the MM block. */
irq_set_affinity(IRQ_ISP, cpumask_of(0));
disable_irq(IRQ_ISP);
return 0;
qos_request_fail:
pi_mgr_dfs_request_remove(&isp_dfs_node);
err:
kfree(dev);
return ret;
}
static int hawaii_camera_power(struct device *dev, int on)
{
static struct pi_mgr_dfs_node unicam_dfs_node;
int ret;
printk(KERN_INFO "%s:camera power %s, %d\n", __func__,
(on ? "on" : "off"), unicam_dfs_node.valid);
if (!unicam_dfs_node.valid) {
ret = pi_mgr_dfs_add_request(&unicam_dfs_node, "unicam",
PI_MGR_PI_ID_MM,
PI_MGR_DFS_MIN_VALUE);
if (ret) {
printk(
KERN_ERR "%s: failed to register PI DFS request\n",
__func__
);
return -1;
}
}
if (on) {
if (pi_mgr_dfs_request_update(&unicam_dfs_node, PI_OPP_TURBO)) {
printk(
KERN_ERR "%s:failed to update dfs request for unicam\n",
__func__
);
return -1;
}
}
if (!camdrv_ss_power(0, (bool)on)) {
printk(
KERN_ERR "%s,camdrv_ss_power failed for MAIN CAM!!\n",
__func__
);
return -1;
}
if (!on) {
if (pi_mgr_dfs_request_update(&unicam_dfs_node,
PI_MGR_DFS_MIN_VALUE)) {
printk(
KERN_ERR"%s: failed to update dfs request for unicam\n",
__func__);
}
}
return 0;
}
static int _power_on(void)
{
int ret;
/* Platform specific power-on procedure. May be that this
*should be in a separate file? TODO: REVIEWME */
ret =
pi_mgr_dfs_add_request(&vce_state.dfs_node, "vce", PI_MGR_PI_ID_MM,
PI_OPP_TURBO);
if (ret) {
err_print("Failed to add dfs request for VCE\n");
return -EIO;
}
return 0;
}
static int unicam_get_clocks(struct unicam_device *unicam)
{
int ret;
/* dfs request */
ret = pi_mgr_dfs_add_request(&unicam->dfs_client, "kona-unicam-mc",
PI_MGR_PI_ID_MM, PI_MGR_DFS_MIN_VALUE);
if (ret < 0) {
dev_err(unicam->dev, "cound not register pi dfs client\n");
return ret;
}
unicam->csi2_axi_clk = clk_get(unicam->dev, "csi0_axi_clk");
if (IS_ERR(unicam->csi2_axi_clk)) {
dev_err(unicam->dev, "unable to get clock csi0_axi_clk\n");
unicam_put_clocks(unicam);
return PTR_ERR(unicam->csi2_axi_clk);
}
return 0;
}
static int camdrv_ss_sr030pc50_sensor_power(int on)
{
unsigned int value;
int ret = -1;
struct clk *clock;
struct clk *axi_clk;
static struct pi_mgr_dfs_node unicam_dfs_node;
CAM_INFO_PRINTK("%s:camera power %s\n", __func__, (on ? "on" : "off"));
if (!unicam_dfs_node.valid) {
ret = pi_mgr_dfs_add_request(&unicam_dfs_node, "unicam", PI_MGR_PI_ID_MM,
PI_MGR_DFS_MIN_VALUE);
if (ret) {
CAM_ERROR_PRINTK("%s: failed to register PI DFS request\n",__func__);
return -1;
}
}
clock = clk_get(NULL, SENSOR_0_CLK);
if (!clock) {
CAM_ERROR_PRINTK("%s: unable to get clock %s\n", __func__, SENSOR_0_CLK);
return -1;
}
axi_clk = clk_get(NULL, "csi0_axi_clk");
if (!axi_clk) {
CAM_ERROR_PRINTK("%s:unable to get clock csi0_axi_clk\n", __func__);
return -1;
}
VCAM_A_2_8_V = regulator_get(NULL,"cam");
if(IS_ERR(VCAM_A_2_8_V))
{
CAM_ERROR_PRINTK("can not get VCAM_A_2_8_V.8V\n");
return -1;
}
VCAM_IO_1_8_V = regulator_get(NULL,"hv9");
if(IS_ERR(VCAM_IO_1_8_V))
{
CAM_ERROR_PRINTK("can not get VCAM_IO_1.8V\n");
return -1;
}
#ifdef CONFIG_SOC_CAMERA_POWER_USE_ASR //for hw rev 0.3
VCAM_CORE_1_2_V = regulator_get(NULL,"asr_nm_uc");
if(IS_ERR(VCAM_CORE_1_2_V))
{
CAM_ERROR_PRINTK("can not get VCAM_CORE_1_2_V\n");
return -1;
}
#else
gpio_request(CAM_CORE_EN, "cam_1_2v");
gpio_direction_output(CAM_CORE_EN,0);
#endif
CAM_INFO_PRINTK("set cam_rst cam_stnby to low\n");
gpio_request(CAM0_RESET, "cam0_rst");
gpio_direction_output(CAM0_RESET,0);
gpio_request(CAM0_STNBY, "cam0_stnby");
gpio_direction_output(CAM0_STNBY,0);
gpio_request(CAM1_RESET, "cam1_rst");
gpio_direction_output(CAM1_RESET,0);
gpio_request(CAM1_STNBY, "cam1_stnby");
gpio_direction_output(CAM1_STNBY,0);
if(on)
{
CAM_INFO_PRINTK("power on the sensor \n"); //@HW
regulator_set_voltage(VCAM_A_2_8_V,2800000,2800000);
regulator_set_voltage(VCAM_IO_1_8_V,1800000,1800000);
#ifdef CONFIG_SOC_CAMERA_POWER_USE_ASR //for hw rev 0.3
regulator_set_voltage(VCAM_CORE_1_2_V,1200000,1200000);
#endif
value = clk_enable(axi_clk);
if (value) {
CAM_ERROR_PRINTK("%s:failed to enable csi2 axi clock\n", __func__);
return -1;
}
msleep(100);
CAM_INFO_PRINTK("power on the sensor's power supply\n"); //@HW
regulator_enable(VCAM_A_2_8_V);
msleep(1);
regulator_enable(VCAM_IO_1_8_V);
msleep(5);
#ifdef CONFIG_SOC_CAMERA_POWER_USE_ASR //for hw rev 0.3
regulator_enable(VCAM_CORE_1_2_V);
#else
gpio_set_value(CAM_CORE_EN,1);
#endif
msleep(2);
#ifdef CONFIG_SOC_CAMERA_POWER_USE_ASR //for hw rev 0.3
regulator_disable(VCAM_CORE_1_2_V);
#else
gpio_set_value(CAM_CORE_EN,0);
#endif
msleep(12); //changed by aska for delay MCLK on time
value = clk_enable(clock);
if (value) {
CAM_ERROR_PRINTK("%s: failed to enable clock %s\n", __func__,SENSOR_0_CLK);
return -1;
}
CAM_INFO_PRINTK("enable camera clock\n");
value = clk_set_rate(clock, SENSOR_0_CLK_FREQ);
if (value) {
CAM_ERROR_PRINTK("%s: failed to set the clock %s to freq %d\n",__func__, SENSOR_0_CLK, SENSOR_0_CLK_FREQ);
return -1;
}
CAM_INFO_PRINTK("set rate\n");
msleep(5);
gpio_set_value(CAM1_STNBY,1);
msleep(5);
gpio_set_value(CAM1_RESET,1);
msleep(50);
}
else
{
printk("power off the sensor \n"); //@HW
/* enable reset gpio */
gpio_set_value(CAM1_RESET,0);
msleep(1);
gpio_set_value(CAM1_STNBY,0);
msleep(1);
clk_disable(clock);
clk_disable(axi_clk);
msleep(1);
/* enable power down gpio */
regulator_disable(VCAM_IO_1_8_V);
regulator_disable(VCAM_A_2_8_V);
}
return 0;
}
static int hawaii_camera_power_front(struct device *dev, int on)
{
unsigned int value;
int ret = -1;
struct clk *clock;
struct clk *axi_clk;
struct clk *axi_clk_0;
struct clk *lp_clock_0;
struct clk *lp_clock_1;
static struct pi_mgr_dfs_node unicam_dfs_node;
struct soc_camera_device *icd = to_soc_camera_dev(dev);
struct soc_camera_link *icl = to_soc_camera_link(icd);
printk(KERN_INFO "%s:camera power %s\n", __func__, (on ? "on" : "off"));
struct cameraCfg_s *thisCfg = getCameraCfg(icl->module_name);
if (NULL == thisCfg) {
printk(KERN_ERR "No cfg for [%s]\n", icl->module_name);
return -1;
}
if (!unicam_dfs_node.valid) {
ret = pi_mgr_dfs_add_request(&unicam_dfs_node, "unicam",
PI_MGR_PI_ID_MM,
PI_MGR_DFS_MIN_VALUE);
if (ret) {
return -1;
}
if (gpio_request_one(SENSOR_1_GPIO_PWRDN, GPIOF_DIR_OUT |
(thisCfg->pwdn_active<<1), "Cam1PWDN")) {
printk(KERN_ERR "Unable to get CAM1PWDN\n");
return -1;
}
if (gpio_request_one(SENSOR_1_GPIO_RST, GPIOF_DIR_OUT |
(thisCfg->rst_active<<1), "Cam1RST")) {
printk(KERN_ERR "Unable to get Cam1RST\n");
return -1;
}
d_lvldo2_cam1_1v8 = regulator_get(NULL,
icl->regulators[0].supply);
if (IS_ERR_OR_NULL(d_lvldo2_cam1_1v8))
printk(KERN_ERR "Failed to get d_lvldo2_cam1_1v8\n");
if (d_1v8_mmc1_vcc == NULL) {
d_1v8_mmc1_vcc = regulator_get(NULL,
icl->regulators[1].supply);
if (IS_ERR_OR_NULL(d_1v8_mmc1_vcc))
printk(KERN_ERR "Err d_1v8_mmc1_vcc\n");
}
if (d_3v0_mmc1_vcc == NULL) {
d_3v0_mmc1_vcc = regulator_get(NULL,
icl->regulators[2].supply);
if (IS_ERR_OR_NULL(d_3v0_mmc1_vcc))
printk(KERN_ERR "d_3v0_mmc1_vcc");
}
if (d_gpsr_cam0_1v8 == NULL) {
d_gpsr_cam0_1v8 = regulator_get(NULL,
icl->regulators[3].supply);
if (IS_ERR_OR_NULL(d_gpsr_cam0_1v8))
printk(KERN_ERR "Fl d_gpsr_cam0_1v8 get fail");
}
}
ret = -1;
lp_clock_0 = clk_get(NULL, CSI0_LP_PERI_CLK_NAME_STR);
if (IS_ERR_OR_NULL(lp_clock_0)) {
printk(KERN_ERR "Unable to get %s clock\n",
CSI0_LP_PERI_CLK_NAME_STR);
goto e_clk_get;
}
lp_clock_1 = clk_get(NULL, CSI1_LP_PERI_CLK_NAME_STR);
if (IS_ERR_OR_NULL(lp_clock_1)) {
printk(KERN_ERR "Unable to get %s clock\n",
CSI1_LP_PERI_CLK_NAME_STR);
goto e_clk_get;
}
clock = clk_get(NULL, SENSOR_1_CLK);
if (IS_ERR_OR_NULL(clock)) {
printk(KERN_ERR "Unable to get SENSOR_1 clock\n");
goto e_clk_get;
}
axi_clk_0 = clk_get(NULL, "csi0_axi_clk");
if (IS_ERR_OR_NULL(axi_clk_0)) {
printk(KERN_ERR "Unable to get AXI clock 0\n");
goto e_clk_get;
}
axi_clk = clk_get(NULL, "csi1_axi_clk");
if (IS_ERR_OR_NULL(axi_clk)) {
printk(KERN_ERR "Unable to get AXI clock 1\n");
goto e_clk_get;
}
if (on) {
if (pi_mgr_dfs_request_update(&unicam_dfs_node, PI_OPP_TURBO))
printk("DVFS for UNICAM failed\n");
gpio_set_value(SENSOR_1_GPIO_PWRDN, thisCfg->pwdn_active);
gpio_set_value(SENSOR_1_GPIO_RST, thisCfg->rst_active);
usleep_range(5000, 5010);
regulator_enable(d_lvldo2_cam1_1v8);
usleep_range(1000, 1010);
regulator_enable(d_1v8_mmc1_vcc);
usleep_range(1000, 1010);
/* Secondary cam addition */
regulator_enable(d_gpsr_cam0_1v8);
usleep_range(1000, 1010);
regulator_enable(d_3v0_mmc1_vcc);
usleep_range(1000, 1010);
gpio_set_value(SENSOR_1_GPIO_RST,
thisCfg->rst_active ? 0 : 1);
if (mm_ccu_set_pll_select(CSI1_BYTE1_PLL, 8)) {
pr_err("failed to set BYTE1\n");
goto e_clk_pll;
}
if (mm_ccu_set_pll_select(CSI1_BYTE0_PLL, 8)) {
pr_err("failed to set BYTE0\n");
goto e_clk_pll;
}
if (mm_ccu_set_pll_select(CSI1_CAMPIX_PLL, 8)) {
pr_err("failed to set PIXPLL\n");
goto e_clk_pll;
}
value = clk_enable(lp_clock_0);
if (value) {
printk(KERN_ERR "Failed to enable lp clock 0\n");
goto e_clk_lp0;
}
value = clk_set_rate(lp_clock_0, CSI0_LP_FREQ);
if (value) {
pr_err("Failed to set lp clock 0\n");
goto e_clk_set_lp0;
}
value = clk_enable(lp_clock_1);
if (value) {
pr_err(KERN_ERR "Failed to enable lp clock 1\n");
goto e_clk_lp1;
}
value = clk_set_rate(lp_clock_1, CSI1_LP_FREQ);
if (value) {
pr_err("Failed to set lp clock 1\n");
goto e_clk_set_lp1;
}
value = clk_enable(axi_clk_0);
if (value) {
printk(KERN_ERR "Failed to enable axi clock 0\n");
goto e_clk_axi_clk_0;
}
value = clk_enable(axi_clk);
if (value) {
printk(KERN_ERR "Failed to enable axi clock 1\n");
goto e_clk_axi;
}
value = clk_enable(clock);
if (value) {
printk("Failed to enable sensor 1 clock\n");
goto e_clk_clock;
}
value = clk_set_rate(clock, thisCfg->clk);
if (value) {
printk("Failed to set sensor 1 clock\n");
goto e_clk_set_clock;
}
usleep_range(10000, 10100);
gpio_set_value(SENSOR_1_GPIO_PWRDN,
thisCfg->pwdn_active ? 0 : 1);
msleep(30);
} else {
gpio_set_value(SENSOR_1_GPIO_PWRDN, thisCfg->pwdn_active);
usleep_range(1000, 1010);
gpio_set_value(SENSOR_1_GPIO_RST, thisCfg->rst_active);
clk_disable(lp_clock_0);
clk_disable(lp_clock_1);
clk_disable(clock);
clk_disable(axi_clk);
clk_disable(axi_clk_0);
regulator_disable(d_lvldo2_cam1_1v8);
regulator_disable(d_1v8_mmc1_vcc);
regulator_disable(d_gpsr_cam0_1v8);
regulator_disable(d_3v0_mmc1_vcc);
if (pi_mgr_dfs_request_update
(&unicam_dfs_node, PI_MGR_DFS_MIN_VALUE)) {
printk("Failed to set DVFS for unicam\n");
}
}
return 0;
e_clk_set_clock:
clk_disable(clock);
e_clk_clock:
clk_disable(axi_clk);
e_clk_axi:
clk_disable(axi_clk_0);
e_clk_axi_clk_0:
e_clk_set_lp1:
clk_disable(lp_clock_1);
e_clk_lp1:
e_clk_set_lp0:
clk_disable(lp_clock_0);
e_clk_lp0:
e_clk_pll:
e_clk_get:
return ret;
}
static int hawaii_camera_power(struct device *dev, int on)
{
unsigned int value;
int ret = -1;
struct clk *clock;
struct clk *prediv_clock;
struct clk *lp_clock;
struct clk *axi_clk;
static struct pi_mgr_dfs_node unicam_dfs_node;
struct soc_camera_device *icd = to_soc_camera_dev(dev);
struct soc_camera_link *icl = to_soc_camera_link(icd);
printk(KERN_INFO "%s:camera power %s\n", __func__, (on ? "on" : "off"));
struct cameraCfg_s *thisCfg = getCameraCfg(icl->module_name);
if (NULL == thisCfg) {
printk(KERN_ERR "No cfg for [%s]\n", icl->module_name);
return -1;
}
if (!unicam_dfs_node.valid) {
ret = pi_mgr_dfs_add_request(&unicam_dfs_node, "unicam",
PI_MGR_PI_ID_MM,
PI_MGR_DFS_MIN_VALUE);
if (ret) {
return -1;
}
if (gpio_request_one(SENSOR_0_GPIO_RST, GPIOF_DIR_OUT |
(thisCfg->rst_active<<1), "Cam0Rst")) {
printk(KERN_ERR "Unable to get cam0 RST GPIO\n");
return -1;
}
if (gpio_request_one(SENSOR_0_GPIO_PWRDN, GPIOF_DIR_OUT |
(thisCfg->pwdn_active<<1), "Cam0PWDN")) {
printk(KERN_ERR "Unable to get cam0 PWDN GPIO\n");
return -1;
}
#if defined(CONFIG_MACH_JAVA_C_LC1) \
|| defined(CONFIG_MACH_JAVA_C_5609A) \
|| defined(CONFIG_MACH_JAVA_C_5606)
if (gpio_request_one(MAIN_CAM_AF_ENABLE, GPIOF_DIR_OUT |
GPIOF_INIT_LOW, "Cam0_af_enable")) {
printk(KERN_ERR "Unable to get cam0 af enable GPIO\n");
return -1;
}
if (gpio_request_one(TORCH_EN, GPIOF_DIR_OUT |
GPIOF_INIT_LOW, "cam0_torch_enable")) {
printk(KERN_ERR "Unable to get cam0 torch enable GPIO\n");
return -1;
}
if (gpio_request_one(FLASH_EN, GPIOF_DIR_OUT |
GPIOF_INIT_LOW, "cam0_flash_enable")) {
printk(KERN_ERR "Unable to get cam0 torch enable GPIO\n");
return -1;
}
#endif
/*MMC1 VCC */
d_1v8_mmc1_vcc = regulator_get(NULL, icl->regulators[1].supply);
if (IS_ERR_OR_NULL(d_1v8_mmc1_vcc))
printk(KERN_ERR "Failed to get d_1v8_mmc1_vcc\n");
d_3v0_mmc1_vcc = regulator_get(NULL, icl->regulators[2].supply);
if (IS_ERR_OR_NULL(d_3v0_mmc1_vcc))
printk(KERN_ERR "Failed to get d_3v0_mmc1_vcc\n");
d_gpsr_cam0_1v8 = regulator_get(NULL,
icl->regulators[0].supply);
if (IS_ERR_OR_NULL(d_gpsr_cam0_1v8))
printk(KERN_ERR "Failed to get d_gpsr_cam0_1v8\n");
if (d_lvldo2_cam1_1v8 == NULL) {
d_lvldo2_cam1_1v8 = regulator_get(NULL,
icl->regulators[3].supply);
if (IS_ERR_OR_NULL(d_lvldo2_cam1_1v8))
printk(KERN_ERR "Fd_lvldo2_cam1_1v8 cam\n");
}
}
ret = -1;
lp_clock = clk_get(NULL, CSI0_LP_PERI_CLK_NAME_STR);
if (IS_ERR_OR_NULL(lp_clock)) {
printk(KERN_ERR "Unable to get %s clock\n",
CSI0_LP_PERI_CLK_NAME_STR);
goto e_clk_get;
}
prediv_clock = clk_get(NULL, SENSOR_PREDIV_CLK);
if (IS_ERR_OR_NULL(prediv_clock)) {
printk(KERN_ERR "Unable to get SENSOR_PREDIV_CLK clock\n");
goto e_clk_get;
}
clock = clk_get(NULL, SENSOR_0_CLK);
if (IS_ERR_OR_NULL(clock)) {
printk(KERN_ERR "Unable to get SENSOR_0 clock\n");
goto e_clk_get;
}
axi_clk = clk_get(NULL, "csi0_axi_clk");
if (IS_ERR_OR_NULL(axi_clk)) {
printk(KERN_ERR "Unable to get AXI clock\n");
goto e_clk_get;
}
if (on) {
if (pi_mgr_dfs_request_update(&unicam_dfs_node, PI_OPP_TURBO))
printk("DVFS for UNICAM failed\n");
regulator_enable(d_gpsr_cam0_1v8);
usleep_range(1000, 1010);
regulator_enable(d_1v8_mmc1_vcc);
usleep_range(1000, 1010);
regulator_enable(d_lvldo2_cam1_1v8);
usleep_range(1000, 1010);
if (mm_ccu_set_pll_select(CSI0_BYTE1_PLL, 8)) {
pr_err("failed to set BYTE1\n");
goto e_clk_pll;
}
if (mm_ccu_set_pll_select(CSI0_BYTE0_PLL, 8)) {
pr_err("failed to set BYTE0\n");
goto e_clk_pll;
}
if (mm_ccu_set_pll_select(CSI0_CAMPIX_PLL, 8)) {
pr_err("failed to set PIXPLL\n");
goto e_clk_pll;
}
value = clk_enable(axi_clk);
if (value) {
pr_err(KERN_ERR "Failed to enable axi clock\n");
goto e_clk_axi;
}
value = clk_enable(lp_clock);
if (value) {
pr_err(KERN_ERR "Failed to enable lp clock\n");
goto e_clk_lp;
}
value = clk_set_rate(lp_clock, CSI0_LP_FREQ);
if (value) {
pr_err("Failed to set lp clock\n");
goto e_clk_set_lp;
}
value = clk_enable(prediv_clock);
if (value) {
pr_err("Failed to enable prediv clock\n");
goto e_clk_prediv;
}
value = clk_enable(clock);
if (value) {
pr_err("Failed to enable sensor 0 clock\n");
goto e_clk_sensor;
}
value = clk_set_rate(prediv_clock, thisCfg->prediv_clk);
if (value) {
pr_err("Failed to set prediv clock\n");
goto e_clk_set_prediv;
}
value = clk_set_rate(clock, thisCfg->clk);
if (value) {
pr_err("Failed to set sensor0 clock\n");
goto e_clk_set_sensor;
}
usleep_range(10000, 10100);
gpio_set_value(SENSOR_0_GPIO_RST, thisCfg->rst_active);
usleep_range(10000, 10100);
gpio_set_value(SENSOR_0_GPIO_PWRDN,
thisCfg->pwdn_active ? 0 : 1);
usleep_range(5000, 5100);
gpio_set_value(SENSOR_0_GPIO_RST,
thisCfg->rst_active ? 0 : 1);
msleep(30);
regulator_enable(d_3v0_mmc1_vcc);
usleep_range(1000, 1010);
#if defined(CONFIG_MACH_JAVA_C_LC1) || defined(CONFIG_MACH_JAVA_C_5609A) \
|| defined(CONFIG_MACH_JAVA_C_5606)
set_af_enable(1);
#endif
#ifdef CONFIG_VIDEO_A3907
a3907_enable(1);
#endif
#ifdef CONFIG_VIDEO_DW9714
dw9714_enable(1);
#endif
} else {
#ifdef CONFIG_VIDEO_A3907
a3907_enable(0);
#endif
#ifdef CONFIG_VIDEO_DW9714
dw9714_enable(0);
#endif
#if defined(CONFIG_MACH_JAVA_C_LC1) || defined(CONFIG_MACH_JAVA_C_5609A) \
|| defined(CONFIG_MACH_JAVA_C_5606)
set_af_enable(0);
#endif
usleep_range(5000, 5100);
gpio_set_value(SENSOR_0_GPIO_PWRDN, thisCfg->pwdn_active);
usleep_range(1000, 1100);
gpio_set_value(SENSOR_0_GPIO_RST, thisCfg->rst_active);
clk_disable(prediv_clock);
clk_disable(clock);
clk_disable(lp_clock);
clk_disable(axi_clk);
regulator_disable(d_3v0_mmc1_vcc);
regulator_disable(d_lvldo2_cam1_1v8);
regulator_disable(d_1v8_mmc1_vcc);
regulator_disable(d_gpsr_cam0_1v8);
if (pi_mgr_dfs_request_update
(&unicam_dfs_node, PI_MGR_DFS_MIN_VALUE)) {
printk("Failed to set DVFS for unicam\n");
}
}
return 0;
e_clk_set_sensor:
clk_disable(clock);
e_clk_sensor:
e_clk_set_prediv:
clk_disable(prediv_clock);
e_clk_prediv:
e_clk_set_lp:
clk_disable(lp_clock);
e_clk_lp:
clk_disable(axi_clk);
e_clk_axi:
e_clk_pll:
e_clk_get:
return ret;
}
static int hawaii_camera_power(struct device *dev, int on)
{
unsigned int value;
int ret = -1;
struct clk *clock;
struct clk *lp_clock;
struct clk *axi_clk;
static struct pi_mgr_dfs_node unicam_dfs_node;
struct soc_camera_device *icd = to_soc_camera_dev(dev);
struct soc_camera_link *icl = to_soc_camera_link(icd);
printk(KERN_INFO "%s:camera power %s\n", __func__, (on ? "on" : "off"));
if (!unicam_dfs_node.valid) {
ret = pi_mgr_dfs_add_request(&unicam_dfs_node, "unicam",
PI_MGR_PI_ID_MM,
PI_MGR_DFS_MIN_VALUE);
if (ret) {
return -1;
}
if (gpio_request_one(SENSOR_0_GPIO_RST, GPIOF_DIR_OUT |
GPIOF_INIT_LOW, "Cam0Rst")) {
printk(KERN_ERR "Unable to get cam0 RST GPIO\n");
return -1;
}
if (gpio_request_one(SENSOR_0_GPIO_PWRDN, GPIOF_DIR_OUT |
GPIOF_INIT_LOW, "CamPWDN")) {
printk(KERN_ERR "Unable to get cam0 PWDN GPIO\n");
return -1;
}
/*MMC1 VCC */
d_1v8_mmc1_vcc = regulator_get(NULL, icl->regulators[1].supply);
if (IS_ERR_OR_NULL(d_1v8_mmc1_vcc))
printk(KERN_ERR "Failed to get d_1v8_mmc1_vcc\n");
d_3v0_mmc1_vcc = regulator_get(NULL, icl->regulators[2].supply);
if (IS_ERR_OR_NULL(d_3v0_mmc1_vcc))
printk(KERN_ERR "Failed to get d_3v0_mmc1_vcc\n");
d_gpsr_cam0_1v8 = regulator_get(NULL,
icl->regulators[0].supply);
if (IS_ERR_OR_NULL(d_gpsr_cam0_1v8))
printk(KERN_ERR "Failed to get d_gpsr_cam0_1v8\n");
if (d_lvldo2_cam1_1v8 == NULL) {
d_lvldo2_cam1_1v8 = regulator_get(NULL,
icl->regulators[3].supply);
if (IS_ERR_OR_NULL(d_lvldo2_cam1_1v8))
printk(KERN_ERR "Fd_lvldo2_cam1_1v8 cam\n");
}
}
ret = -1;
lp_clock = clk_get(NULL, CSI0_LP_PERI_CLK_NAME_STR);
if (IS_ERR_OR_NULL(lp_clock)) {
printk(KERN_ERR "Unable to get %s clock\n",
CSI0_LP_PERI_CLK_NAME_STR);
goto e_clk_get;
}
clock = clk_get(NULL, SENSOR_0_CLK);
if (IS_ERR_OR_NULL(clock)) {
printk(KERN_ERR "Unable to get SENSOR_0 clock\n");
goto e_clk_get;
}
axi_clk = clk_get(NULL, "csi0_axi_clk");
if (IS_ERR_OR_NULL(axi_clk)) {
printk(KERN_ERR "Unable to get AXI clock\n");
goto e_clk_get;
}
if (on) {
if (pi_mgr_dfs_request_update(&unicam_dfs_node, PI_OPP_TURBO))
printk("DVFS for UNICAM failed\n");
regulator_enable(d_3v0_mmc1_vcc);
usleep_range(1000, 1010);
regulator_enable(d_1v8_mmc1_vcc);
usleep_range(1000, 1010);
regulator_enable(d_gpsr_cam0_1v8);
usleep_range(1000, 1010);
regulator_enable(d_lvldo2_cam1_1v8);
usleep_range(1000, 1010);
if (mm_ccu_set_pll_select(CSI0_BYTE1_PLL, 8)) {
pr_err("failed to set BYTE1\n");
goto e_clk_pll;
}
if (mm_ccu_set_pll_select(CSI0_BYTE0_PLL, 8)) {
pr_err("failed to set BYTE0\n");
goto e_clk_pll;
}
if (mm_ccu_set_pll_select(CSI0_CAMPIX_PLL, 8)) {
pr_err("failed to set PIXPLL\n");
goto e_clk_pll;
}
value = clk_enable(axi_clk);
if (value) {
pr_err(KERN_ERR "Failed to enable axi clock\n");
goto e_clk_axi;
}
value = clk_enable(lp_clock);
if (value) {
pr_err(KERN_ERR "Failed to enable lp clock\n");
goto e_clk_lp;
}
value = clk_set_rate(lp_clock, CSI0_LP_FREQ);
if (value) {
pr_err("Failed to set lp clock\n");
goto e_clk_set_lp;
}
value = clk_enable(clock);
if (value) {
pr_err("Failed to enable sensor 0 clock\n");
goto e_clk_sensor;
}
value = clk_set_rate(clock, SENSOR_0_CLK_FREQ);
if (value) {
pr_err("Failed to set sensor0 clock\n");
goto e_clk_set_sensor;
}
usleep_range(10000, 10100);
gpio_set_value(SENSOR_0_GPIO_RST, 0);
usleep_range(10000, 10100);
gpio_set_value(SENSOR_0_GPIO_PWRDN, 0);
usleep_range(5000, 5100);
gpio_set_value(SENSOR_0_GPIO_RST, 1);
msleep(30);
} else {
gpio_set_value(SENSOR_0_GPIO_RST, 0);
usleep_range(1000, 1100);
gpio_set_value(SENSOR_0_GPIO_PWRDN, 1);
clk_disable(clock);
clk_disable(lp_clock);
clk_disable(axi_clk);
regulator_disable(d_lvldo2_cam1_1v8);
regulator_disable(d_3v0_mmc1_vcc);
regulator_disable(d_1v8_mmc1_vcc);
regulator_disable(d_gpsr_cam0_1v8);
if (pi_mgr_dfs_request_update
(&unicam_dfs_node, PI_MGR_DFS_MIN_VALUE)) {
printk("Failed to set DVFS for unicam\n");
}
}
return 0;
e_clk_set_sensor:
clk_disable(clock);
e_clk_sensor:
e_clk_set_lp:
clk_disable(lp_clock);
e_clk_lp:
clk_disable(axi_clk);
e_clk_axi:
e_clk_pll:
e_clk_get:
return ret;
}
static int h264_open(struct inode *inode, struct file *filp)
{
int ret = 0;
struct h264_t *dev = kmalloc(sizeof(struct h264_t), GFP_KERNEL);
if (!dev) {
printk("\n Returning from no memory");
return -ENOMEM;
}
mutex_lock(&h264_mutex);
filp->private_data = dev;
spin_lock_init(&dev->lock);
dev->dev_status.cbc_intr = 0x00;
dev->dev_status.mcin_intr = 0x00;
init_completion(&dev->irq_sem);
/*
Add a request for DFS.
Add a request for QOS (with default value)
Enable the clock for H.264 block.
*/
#ifdef H264_CLK_MGMT
ret =
pi_mgr_dfs_add_request(&h264_dfs_node, "h264", PI_MGR_PI_ID_MM,
PI_MGR_DFS_MIN_VALUE);
if (ret) {
printk(KERN_ERR "%s: failed to register PI DFS request\n",
__func__);
goto err;
}
#ifdef H264_QOS_MGMT
ret =
pi_mgr_qos_add_request(&h264_qos_node, "h264",
PI_MGR_PI_ID_ARM_CORE,
PI_MGR_QOS_DEFAULT_VALUE);
if (ret) {
printk(KERN_ERR "%s: failed to register PI QOS request\n",
__func__);
ret = -EIO;
goto qos_request_fail;
}
#endif
enable_h264_clock();
/* Access to root reset manager register block. */
writel(0xa5a501, IOMEM(HW_IO_PHYS_TO_VIRT(0x35001f00)));
usleep_range(10, 20);
/* Enable multimedia power domain. */
/* Test 0x3d should be sufficient for MM. */
writel(0xfd, IOMEM(HW_IO_PHYS_TO_VIRT(0x35001f08)));
usleep_range(10, 20);
/* Enable H264 Slave interface control register. */
writel(0x00, IOMEM(HW_IO_PHYS_TO_VIRT(0x3C00F004)));
usleep_range(10, 20);
/* Enable H264 Master interface control register. */
writel(0x00, IOMEM(HW_IO_PHYS_TO_VIRT(0x3C00F008)));
usleep_range(10, 20);
#ifdef H264_QOS_MGMT
ret = pi_mgr_qos_request_update(&h264_qos_node, 0);
if (ret) {
printk(KERN_ERR "%s: failed to register PI QOS request\n",
__func__);
ret = -EIO;
}
scu_standby(0);
#endif
#endif
usleep_range(50, 100); /* buffer to ensure everything above are done. */
#ifdef ENABLE_H264_INT
/* Register for the interrupts */
ret =
request_irq(H264_AOB_IRQ, h264_isr, IRQF_DISABLED | IRQF_SHARED |
IRQF_NO_SUSPEND, H264_DEV_NAME, dev);
if (ret) {
err_print("request_irq failed for AOB ret = %d\n", ret);
goto err;
}
/* Ensure that only one CORE handles interrupt for the MM block. */
irq_set_affinity(H264_AOB_IRQ, cpumask_of(0));
ret =
request_irq(H264_CME_IRQ, h264_isr, IRQF_DISABLED | IRQF_SHARED |
IRQF_NO_SUSPEND, H264_DEV_NAME, dev);
if (ret) {
err_print("request_irq failed for CME ret = %d\n", ret);
goto err;
}
/* Ensure that only one CORE handles interrupt for the MM block. */
irq_set_affinity(H264_CME_IRQ, cpumask_of(0));
ret =
request_irq(H264_MCIN_CBC_IRQ, h264_isr, IRQF_DISABLED | IRQF_SHARED
| IRQF_NO_SUSPEND, H264_DEV_NAME, dev);
if (ret) {
err_print("request_irq failed for MCIN_CBC ret = %d\n", ret);
goto err;
}
/* Ensure that only one CORE handles interrupt for the MM block. */
irq_set_affinity(H264_MCIN_CBC_IRQ, cpumask_of(0));
disable_irq(H264_AOB_IRQ);
disable_irq(H264_CME_IRQ);
disable_irq(H264_MCIN_CBC_IRQ);
#endif
return 0;
#ifdef H264_QOS_MGMT
qos_request_fail:
pi_mgr_dfs_request_remove(&h264_dfs_node);
#endif
err:
kfree(dev);
printk(KERN_ERR "\nError in the h264_open\n");
mutex_unlock(&h264_mutex);
return ret;
}
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++
*
* Function Name: PcmPlaybackOpen
*
* Description: Open PCM playback device
*
*------------------------------------------------------------
*/
static int PcmPlaybackOpen(struct snd_pcm_substream *substream)
{
AUDIO_DRIVER_HANDLE_t drv_handle;
BRCM_AUDIO_Param_Open_t param_open;
brcm_alsa_chip_t *chip = snd_pcm_substream_chip(substream);
struct snd_pcm_runtime *runtime = substream->runtime;
int err = 0;
int substream_number = substream->number;
aTrace
(LOG_ALSA_INTERFACE, "ALSA-CAPH %lx:playback_open stream=%d,"
"PCM_TOTAL_BUF_BYTES=%d chip->iEnablePhoneCall=%d,"
"speaker=%d\n",
jiffies, substream_number, PCM_TOTAL_BUF_BYTES,
(unsigned int)chip->iEnablePhoneCall,
chip->streamCtl[substream_number].iLineSelect[0]);
if (!dfs_node_created)
{
int err = 0;
err = pi_mgr_dfs_add_request(&dfs_node, audio_dfs,
PI_MGR_PI_ID_ARM_CORE,
PI_MGR_DFS_MIN_VALUE);
/* Check if the request was handled or not */
if (err) {
aWarn("%s : Warning: could not create audio dfs_node\n", __func__);
}
dfs_node_created = TRUE;
}
#ifdef CONFIG_HAS_EARLYSUSPEND
if (!early_suspend_registered) {
register_early_suspend(&audio_early_suspend_desc);
early_suspend_registered = TRUE;
}
#endif /* CONFIG_HAS_EARLYSUSPEND */
param_open.drv_handle = NULL;
param_open.pdev_prop = &chip->streamCtl[substream_number].dev_prop;
param_open.stream = substream_number;
aTrace(LOG_ALSA_INTERFACE,
"\n %lx:playback_open route the playback to CAPH\n", jiffies);
/*route the playback to CAPH */
runtime->hw = brcm_playback_hw;
chip->streamCtl[substream_number].dev_prop.p[0].drv_type =
AUDIO_DRIVER_PLAY_AUDIO;
chip->streamCtl[substream_number].pSubStream = substream;
#if defined(DYNAMIC_DMA_PLAYBACK)
runtime->hw.periods_max = 8;
#endif
/*open the playback device */
AUDIO_Ctrl_Trigger(ACTION_AUD_OpenPlay, ¶m_open, NULL, 1);
drv_handle = param_open.drv_handle;
if (drv_handle == NULL) {
aError("\n %lx:playback_open stream=%d failed\n",
jiffies, substream_number);
return -1;
}
substream->runtime->private_data = drv_handle;
aTrace(LOG_ALSA_INTERFACE,
"chip-0x%lx substream-0x%lx drv_handle-0x%lx\n",
(UInt32) chip, (UInt32) substream, (UInt32) drv_handle);
return err;
}
static int hawaii_camera_power_front(struct device *dev, int on)
{
unsigned int value;
int ret = -1;
struct clk *clock;
struct clk *axi_clk;
struct clk *axi_clk_0;
struct clk *lp_clock_0;
struct clk *lp_clock_1;
static struct pi_mgr_dfs_node unicam_dfs_node;
printk(KERN_INFO "%s:camera power %s\n", __func__, (on ? "on" : "off"));
if (!unicam_dfs_node.valid) {
ret = pi_mgr_dfs_add_request(&unicam_dfs_node, "unicam",
PI_MGR_PI_ID_MM,
PI_MGR_DFS_MIN_VALUE);
if (ret) {
return -1;
}
if (gpio_request_one(SENSOR_1_GPIO_PWRDN, GPIOF_DIR_OUT |
GPIOF_INIT_LOW, "Cam1PWDN")) {
printk(KERN_ERR "Unable to get CAM1PWDN\n");
return -1;
}
d_lvldo2_cam1_1v8 = regulator_get(NULL, "lvldo2_uc");
if (IS_ERR_OR_NULL(d_lvldo2_cam1_1v8))
printk(KERN_ERR "Failed to get d_lvldo2_cam1_1v8\n");
if (d_1v8_mmc1_vcc == NULL) {
d_1v8_mmc1_vcc = regulator_get(NULL, "mmc1_vcc");
if (IS_ERR_OR_NULL(d_1v8_mmc1_vcc))
printk(KERN_ERR "Err d_1v8_mmc1_vcc\n");
}
}
ret = -1;
lp_clock_0 = clk_get(NULL, CSI0_LP_PERI_CLK_NAME_STR);
if (IS_ERR_OR_NULL(lp_clock_0)) {
printk(KERN_ERR "Unable to get %s clock\n",
CSI0_LP_PERI_CLK_NAME_STR);
goto e_clk_get;
}
lp_clock_1 = clk_get(NULL, CSI1_LP_PERI_CLK_NAME_STR);
if (IS_ERR_OR_NULL(lp_clock_1)) {
printk(KERN_ERR "Unable to get %s clock\n",
CSI1_LP_PERI_CLK_NAME_STR);
goto e_clk_get;
}
clock = clk_get(NULL, SENSOR_1_CLK);
if (IS_ERR_OR_NULL(clock)) {
printk(KERN_ERR "Unable to get SENSOR_1 clock\n");
goto e_clk_get;
}
axi_clk_0 = clk_get(NULL, "csi0_axi_clk");
if (IS_ERR_OR_NULL(axi_clk_0)) {
printk(KERN_ERR "Unable to get AXI clock 0\n");
goto e_clk_get;
}
axi_clk = clk_get(NULL, "csi1_axi_clk");
if (IS_ERR_OR_NULL(axi_clk)) {
printk(KERN_ERR "Unable to get AXI clock 1\n");
goto e_clk_get;
}
if (on) {
if (pi_mgr_dfs_request_update(&unicam_dfs_node, PI_OPP_TURBO))
printk("DVFS for UNICAM failed\n");
gpio_set_value(SENSOR_1_GPIO_PWRDN, 1);
usleep_range(5000, 5010);
regulator_enable(d_lvldo2_cam1_1v8);
usleep_range(1000, 1010);
regulator_enable(d_1v8_mmc1_vcc);
usleep_range(1000, 1010);
if (mm_ccu_set_pll_select(CSI1_BYTE1_PLL, 8)) {
pr_err("failed to set BYTE1\n");
goto e_clk_pll;
}
if (mm_ccu_set_pll_select(CSI1_BYTE0_PLL, 8)) {
pr_err("failed to set BYTE0\n");
goto e_clk_pll;
}
if (mm_ccu_set_pll_select(CSI1_CAMPIX_PLL, 8)) {
pr_err("failed to set PIXPLL\n");
goto e_clk_pll;
}
value = clk_enable(lp_clock_0);
if (value) {
printk(KERN_ERR "Failed to enable lp clock 0\n");
goto e_clk_lp0;
}
value = clk_set_rate(lp_clock_0, CSI0_LP_FREQ);
if (value) {
pr_err("Failed to set lp clock 0\n");
goto e_clk_set_lp0;
}
value = clk_enable(lp_clock_1);
if (value) {
pr_err(KERN_ERR "Failed to enable lp clock 1\n");
goto e_clk_lp1;
}
value = clk_set_rate(lp_clock_1, CSI1_LP_FREQ);
if (value) {
pr_err("Failed to set lp clock 1\n");
goto e_clk_set_lp1;
}
value = clk_enable(axi_clk_0);
if (value) {
printk(KERN_ERR "Failed to enable axi clock 0\n");
goto e_clk_axi_clk_0;
}
value = clk_enable(axi_clk);
if (value) {
printk(KERN_ERR "Failed to enable axi clock 1\n");
goto e_clk_axi;
}
value = clk_enable(clock);
if (value) {
printk("Failed to enable sensor 1 clock\n");
goto e_clk_clock;
}
value = clk_set_rate(clock, SENSOR_1_CLK_FREQ);
if (value) {
printk("Failed to set sensor 1 clock\n");
goto e_clk_set_clock;
}
usleep_range(10000, 10100);
gpio_set_value(SENSOR_1_GPIO_PWRDN, 0);
msleep(30);
} else {
gpio_set_value(SENSOR_1_GPIO_PWRDN, 1);
clk_disable(lp_clock_0);
clk_disable(lp_clock_1);
clk_disable(clock);
clk_disable(axi_clk);
clk_disable(axi_clk_0);
regulator_disable(d_lvldo2_cam1_1v8);
regulator_disable(d_1v8_mmc1_vcc);
if (pi_mgr_dfs_request_update
(&unicam_dfs_node, PI_MGR_DFS_MIN_VALUE)) {
printk("Failed to set DVFS for unicam\n");
}
}
return 0;
e_clk_set_clock:
clk_disable(clock);
e_clk_clock:
clk_disable(axi_clk);
e_clk_axi:
clk_disable(axi_clk_0);
e_clk_axi_clk_0:
e_clk_set_lp1:
clk_disable(lp_clock_1);
e_clk_lp1:
e_clk_set_lp0:
clk_disable(lp_clock_0);
e_clk_lp0:
e_clk_pll:
e_clk_get:
return ret;
}
