static void
serial_init(void) {
volatile unsigned char *uart = (unsigned char*)COM1;
if(serial_exists)
return ;
serial_exists = 1;
#ifdef MACH_QEMU
// Turn off the FIFO
outb(COM1 + COM_FCR, 0);
// Set speed; requires DLAB latch
outb(COM1 + COM_LCR, COM_LCR_DLAB);
outb(COM1 + COM_DLL, (uint8_t) (115200 / 9600));
outb(COM1 + COM_DLM, 0);
// 8 data bits, 1 stop bit, parity off; turn off DLAB latch
outb(COM1 + COM_LCR, COM_LCR_WLEN8 & ~COM_LCR_DLAB);
// No modem controls
outb(COM1 + COM_MCR, 0);
// Enable rcv interrupts
outb(COM1 + COM_IER, COM_IER_RDI);
#elif defined MACH_FPGA
//TODO
#endif
pic_enable(COM1_IRQ);
pic_enable(KEYBOARD_IRQ);
}
void timer_init() {
jiffies = 0;
outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
outb(IO_TIMER1, TIMER_DIV(100) % 256);
outb(IO_TIMER1, TIMER_DIV(100) / 256);
pic_enable(IRQ_TIMER);
//FIXME: gecici olarak burda
pic_enable(IRQ_KBD);
}
void interrupt_enable(int i) {
if (i < 32) {
/* do nothing */
} else {
pic_enable(i - 32);
}
}
/*
* Handle external (asynchronous) interrupts.
* For now, only the timer interrupt is virtualized, all other
* interrupts are forwarded to the I/O (controller) partition.
*/
void
interrupt(struct cpu_thread *thread, uval32 vector)
{
uval irq = vector - BASE_IRQ_VECTOR;
pic_mask_and_ack(irq);
if (likely(irq == TIMER_IRQ)) { /* timer */
/* update clock ticks */
ticks++;
/* keep track of decrementer and reschedule if necessary */
if (unlikely(decrementer-- == 0)) {
decrementer = DECREMENTER;
thread->preempt = CT_PREEMPT_RESCHEDULE;
} else {
thread->preempt = CT_PREEMPT_CEDE;
}
pic_enable(irq);
} else {
struct cpu_thread *ct = &ctrl_os->cpu[0]->thread[0];
struct mailbox *mbox = ct->mbox;
if (mbox) {
mbox->irq_pending |= 1 << irq;
if (ct->preempt == 0) /* schedule interrupt */
ct->preempt = CT_PREEMPT_CEDE;
}
}
}
static void
serial_init(void) {
// Turn off the FIFO
outb(COM1 + COM_FCR, 0);
// Set speed; requires DLAB latch
outb(COM1 + COM_LCR, COM_LCR_DLAB);
outb(COM1 + COM_DLL, (uint8_t) (115200 / 9600));
outb(COM1 + COM_DLM, 0);
// 8 data bits, 1 stop bit, parity off; turn off DLAB latch
outb(COM1 + COM_LCR, COM_LCR_WLEN8 & ~COM_LCR_DLAB);
// No modem controls
outb(COM1 + COM_MCR, 0);
// Enable rcv interrupts
outb(COM1 + COM_IER, COM_IER_RDI);
// Clear any preexisting overrun indications and interrupts
// Serial port doesn't exist if COM_LSR returns 0xFF
serial_exists = (inb(COM1 + COM_LSR) != 0xFF);
(void) inb(COM1+COM_IIR);
(void) inb(COM1+COM_RX);
if (serial_exists) {
pic_enable(IRQ_COM1);
}
}
/* *
* clock_init - initialize 8253 clock to interrupt 100 times per second,
* and then enable IRQ_TIMER.
* */
void clock_init(void)
{
//lapic_timer_set(100);
//percpu timer has been inited in lapic_init
kprintf("++ setup timer interrupts\n");
pic_enable(IRQ_TIMER);
}
void
timer_init(void)
{
// Interrupt 100 times/sec.
outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
outb(IO_TIMER1, TIMER_DIV(100) % 256);
outb(IO_TIMER1, TIMER_DIV(100) / 256);
pic_enable(IRQ_TIMER);
}
void
serial_intenable(void)
{
// Enable serial interrupts
if (serial_exists) {
pic_enable(IRQ_SERIAL);
ioapic_enable(IRQ_SERIAL);
}
}
static void
serial_init(void) {
serial_exists = 1;
if (serial_exists) {
// Do NOT response to serial int now. TODO
pic_enable(IRQ_COM1);
}
}
void clock_init_arm(uint32_t base, int irq)
{
//TODO
timer_base = base;
outw(timer_base + TIMER_LOAD, LOAD_VALUE);
outw(timer_base + TIMER_CONTROL, TIMER_CONTROL_VAL);
register_irq(irq, clock_int_handler, 0);
pic_enable(irq);
}
static void
kbd_init(void) {
serial_exists = 1;
if (serial_exists) {
// Do NOT response to keyboard int now. TODO
pic_enable(IRQ_KBD);
}
}
void pit_reset(void)
{
/* Calculate the correct divisor. */
uint divisor = TICKS_DIVISOR;
/* Write the divisor (low) */
outb(PORT_PIT_CHANNEL_0_DATA, (uchar)divisor);
/* Write the divisor (high) */
outb(PORT_PIT_CHANNEL_0_DATA, (uchar)(divisor >> 8));
pic_enable(INT_PIC_TIMER);
}
/* irq */
int request_irq(unsigned int irq, irq_handler_t handler,
unsigned long irqflags, const char *devname, void *dev_id)
{
if (irq > 31)
return -EINVAL;
printk(KERN_DEBUG "request_irq %d\n", irq);
register_irq(irq, handler, dev_id);
pic_enable(irq);
return 0;
}
void serial_init(void)
{
if (serial_exists)
return;
serial_exists = 1;
/* turn on recv interrput */
outw(VERSATILEPB_UART0 + UARTIMSC, UART_RXIM);
//serial_clear();
pic_enable(UART_IRQ);
}
void
console_init(void)
{
initlock(&console_lock, "console");
initlock(&input.lock, "console input");
devsw[CONSOLE].write = console_write;
devsw[CONSOLE].read = console_read;
use_console_lock = 1;
pic_enable(IRQ_KBD);
ioapic_enable(IRQ_KBD, 0);
}
/* *
* clock_init - initialize 8253 clock to interrupt 100 times per second,
* and then enable IRQ_TIMER.
* */
void clock_init(void)
{
// set 8253 timer-chip
outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
outb(IO_TIMER1, TIMER_DIV(100) % 256);
outb(IO_TIMER1, TIMER_DIV(100) / 256);
// initialize time counter 'ticks' to zero
ticks = 0;
kprintf("++ setup timer interrupts\n");
pic_enable(IRQ_TIMER);
register_irq(I_TIMER, timer_handler, NULL);
}
void clock_init_arm(uint32_t base, int irq)
{
// ARM_TIMER_DIV: pre-divider: clock = apb_clock / (x+1), 1MHz
outw(ARM_TIMER_DIV,0x000000F9);
// ARM_TIMER_CTL: control:
// 1: 23-bit counter, 5: interrupt on, 7: timer on
// 3..2: prescale off, 23..16: prescale, freq = clock / (x+1)
outw(ARM_TIMER_CTL,0x003E00A2);
clock_clear();
reload_timer();
register_irq(TIMER0_IRQ, clock_int_handler, 0);
pic_enable(TIMER0_IRQ);
}
/*
* Initialize keyboard
*/
void
kbdinit()
{
#ifndef NDEBUG
if ((kbd_debug = kernel_option("kbd")) == 0)
kbd_debug = KBD_DEBUG;
if ((i386_debug = kernel_option("i386")) == 0)
i386_debug = I386_DEBUG;
#endif
setirq(KBD_IRQ, kbdintr);
pic_enable(KBD_IRQ);
numlock = 1; /* num-lock is on */
capslock = 0; /* caps-lock is off */
scrollock = 0; /* scroll-lock is off */
kbd_leds();
}
void
serial_init(uint32_t base, uint32_t irq) {
if(serial_exists)
return ;
serial_exists = 1;
uart_base = base;
/* buffer size = 1 */
outw(uart_base+TTY_DATA_LEN, 1);
outw(uart_base+TTY_DATA_PTR, (uint32_t)tty_buffer);
/* turn on recv interrput */
outw(uart_base+TTY_CMD, TTY_CMD_INT_ENABLE);
//serial_clear();
register_irq(irq, serial_int_handler, NULL);
pic_enable(irq);
}
/* *
* clock_init - initialize 8253 clock to interrupt 100 times per second,
* and then enable IRQ_TIMER.
* */
void
clock_init(void) {
#if 0
// set 8253 timer-chip
outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
outb(IO_TIMER1, TIMER_DIV(100) % 256);
outb(IO_TIMER1, TIMER_DIV(100) / 256);
pic_enable(IRQ_TIMER);
#else
lapic_timer_set(100);
#endif
// initialize time counter 'ticks' to zero
ticks = 0;
cprintf("++ setup timer interrupts\n");
}
void pit_init(void)
{
/* The command we will send */
uchar command = 0;
/* Set the channel */
command |= 0 << 6; /* Channel 0 */
/* Access mode */
command |= 3 << 4; /* Lo/Hi mode */
/* Output mode */
command |= 2 << 1; /* Rate generator */
/* BCD / Binary */
command |= 0; /* Input is binary, not BCD */
/* Write the command */
outb(PORT_PIT_COMMAND, command);
/* Calculate the correct divisor. */
uint divisor = TICKS_DIVISOR;
/* Write the divisor (low) */
outb(PORT_PIT_CHANNEL_0_DATA, (uchar)divisor);
/* Write the divisor (high) */
outb(PORT_PIT_CHANNEL_0_DATA, (uchar)(divisor >> 8));
pic_enable(INT_PIC_TIMER);
}
static void
kbd_init(void) {
// drain the kbd buffer
kbd_intr();
pic_enable(IRQ_KBD);
}
void _main(void)
{
uint32_t i;
/**
*
* Basic setup
*/
/* enable the A20 line */
/* disable the PIC (8259A chip) */
pic_enable(false);
/* disable the local APIC */
//apic_enable(false);
//apic_local_enable(false)
/**
*
* Protection
*/
/* init and enable segmentation */
//gdt_init();
seg_init();
// INFINITE_LOOP();
/* init and enable paging */
//mmu_init();
console_clear();
mmu_init();
/* init the system-call facilities */
sc_init();
/**
*
* Interrupts
*/
// INFINITE_LOOP();
/* init and enable interrupts */
idt_init();
//INFINITE_LOOP();
/* bind stage2 isrs */
//isr_init();
int_init();
ex_init();
//INFINITE_LOOP();
/* configure the Local-APIC timer */
//apic_local_timer_init(0x2ffffff);
//apic_local_timer_init(0xffffff);
/* configure the PIT timer */
pit_init();
printf("Local-APIC init...\n");
/* Init the Local-APIC. */
apic_local_init();
apic_local_set_task_priority(0);
printf("Local-APIC timer config...\n");
apic_local_timer_config(0x2ffffff);
printf("IO-APIC init...\n");
apic_io_init();
/* enable the local APIC */
//apic_enable(true);
apic_local_enable(true);
printf("OK\n");
/* configure the I/O APIC in charge of the PIT, keyboard, ... */
//apic_io_init();
/* STI(); */
/* INFINITE_LOOP(); */
/* clear the screen */
console_clear();
console_init();
/* init the basic I/O services */
stdio_init();
//tty_init();
//tty_activate(0);
/* sysenter(); */
/* vmx_supported(1); */
test_malloc();
/* init the serial number facility */
serial_init();
/* printf("UID %d\n", serial_generate()); */
/* printf("UID %d\n", serial_generate()); */
/* printf("UID %d\n", serial_generate()); */
/* init the task manager */
thread_init();
/* init the scheduler manager */
sched_init();
/* dump the memory */
mem_dump();
/* test the mmu. */
//mmu_test();
/* while (1) */
/* ; */
//video_init();
/* msr = rdmsr(MSR_IA32_APIC_BASE); */
/* printf("msr hi: %x\n", (uint32_t)(msr >> 32)); */
/* printf("msr lo: %x\n", (uint32_t) msr); */
/* msr = rdmsr(MSR_IA32_CR_PAT); */
/* printf("msr hi: %x\n", (uint32_t)(msr >> 32)); */
/* printf("msr lo: %x\n", (uint32_t) msr); */
/* msr = rdmsr(MSR_IA32_PERF_GLOBAL_STATUS); */
/* printf("msr hi: %x\n", (uint32_t)(msr >> 32)); */
/* printf("msr lo: %x\n", (uint32_t) msr); */
/* msr = rdmsr(MSR_IA32_PLATFORM_ID); */
/* printf("msr hi: %x\n", (uint32_t)(msr >> 32)); */
/* printf("msr lo: %x\n", (uint32_t) msr); */
/* printf("Macrotest\n"); */
/* MACROTEST(&msr); */
/* printf("msr hi: %x\n", (uint32_t)(msr >> 32)); */
/* printf("apic-io ver: %x\n", apic_io_get_version()); */
/* printf("apic-io id: %x\n", apic_io_get_id()); */
/* printf("New GDT:\n"); */
/* seg_init(); */
/* printf("Old GDT:\n"); */
/* for (i = 0; i < SEG_DESC_N; i++) */
/* { */
/* printf("%x - %x\n", gdt[i].high, gdt[i].low); */
/* } */
//INFINITE_LOOP();
i = 1 << 5 | 1 << 9;
printf("bsf(i) = %d\n", bsf(i));
printf("bsr(i) = %d\n", bsr(i));
i = 0;
printf("bsr(i) = %d\n", bsr(i));
printf("MSR_IA32_SYSENTER_CS high = %x\n", (uint32_t)(rdmsr(MSR_IA32_SYSENTER_CS) >> 32));
printf("MSR_IA32_SYSENTER_CS low = %x\n", (uint32_t) rdmsr(MSR_IA32_SYSENTER_CS));
printf("IA32_CR_PAT high = %x\n", (uint32_t)(rdmsr(MSR_IA32_CR_PAT) >> 32));
printf("IA32_CR_PAT low = %x\n", (uint32_t) rdmsr(MSR_IA32_CR_PAT));
/* jump to background task - code after this function is never reached */
sched_launch();
/* test_multiline(); */
/* test_println(); */
/* test_interrupts(); */
/* test_itoa(); */
/* test_msr(); */
//test_apic();
//test_ide_dma();
//printf("+ Bus 0\n", BG_BLACK | FG_RED | FG_INTENSITY);
//pci_list(0, 2, 64);
/* printf("Bus 1\n", BG_BLACK | FG_RED | FG_INTENSITY); */
/* pci_list(1); */
//test_ide_dma();
//test_apic();
//fprintf(0, "Protos v%d.%d - id:%x\n", 0, 12, 0xbe01);
//fprintf(0, "\tid reg:\t%r\n", 0xbe01);
//fprintf(0, "Ok!\n");
// printf("Helo %% %d-%x-%r\n", 45, 0xabc78, 0xabc78);
//printf("Helo %r\n", 0xbe01);
//r = fprintf(stdout, "Almost %x years :)\n", 26);
//fprintf(stdout, "size:%d\n", strlen("hello!"));
//printf("fprintf result = %d\n", r);
//printf(&((&stdio_filedes[0])->buffer[0]));
//__asm__ ("rdtsc");
// Halt the system
while (1)
HLT();
}
void
clock_init(void) {
reload_timer();
pic_enable(TIMER0_IRQ);
kprintf("++setup timer interrupts\n");
}
void timer_enable(void)
{
pic_enable(PIC_IRQ_TIMER); /* Allow PIT(TIMER) */
}
void timer_overflow_thread(void *arg)
{
/*
* We will now redirect ISR activity here.
*/
timer_isr_ctx = current_context;
isr_disable();
isr_spinlock_lock(&timer_isr_lock);
/*
* initialise 8254 (or 8253) channel 0. We set the timer to
* generate an interrupt every time we have done enough ticks.
* The output format is command, LSByte, MSByte. Note that the
* lowest the value of HZ can be is 19 - otherwise the
* calculations get screwed up,
*/
out8(PIT_CTRL, CMD_SQR_WAVE);
out8(PIT_CH0, (PIT_LATCH - 1) & 0x00ff);
out8(PIT_CH0, ((PIT_LATCH - 1) & 0xff00) >> 8);
/*
* Unmask timer interrupts - we don't need to worry yet though as
* the CPU interrupts are masked.
*/
pic_enable(IRQ_TIMER);
while (1) {
u8_t runnable;
u16_t ticks;
(*((u8_t *)0xb8000 + 142))++;
debug_set_lights(0x0c);
while (!isr_ticks) {
isr_context_wait(&timer_isr_lock);
}
ticks = isr_ticks;
isr_ticks = 0;
runnable = ldavg_runnable;
isr_spinlock_unlock(&timer_isr_lock);
isr_enable();
spinlock_lock(&timer_lock);
/*
* Update the wall-clock!
*/
jiffies += (u32_t)ticks;
/*
* Check if we need to run a load average calculation.
*/
if (ldavg_ticks <= ticks) {
u32_t run_fixp;
run_fixp = (runnable - 1) * LDAV_1;
avenrun[0] *= LDAV_EXP_1;
avenrun[0] += run_fixp * (LDAV_1 - LDAV_EXP_1);
avenrun[0] >>= LDAV_FSHIFT;
avenrun[1] *= LDAV_EXP_5;
avenrun[1] += run_fixp * (LDAV_1 - LDAV_EXP_5);
avenrun[1] >>= LDAV_FSHIFT;
avenrun[2] *= LDAV_EXP_15;
avenrun[2] += run_fixp * (LDAV_1 - LDAV_EXP_15);
avenrun[2] >>= LDAV_FSHIFT;
ldavg_ticks = LDAV_TICKS;
} else {
