/**
* \brief Set an interrupt handler for the provided pins.
* The provided handler will be called with the triggering pin as its parameter
* as soon as an interrupt is detected.
*
* \param p_pio PIO controller base address.
* \param ul_id PIO ID.
* \param ul_mask Pins (bit mask) to configure.
* \param ul_attr Pins attribute to configure.
* \param p_handler Interrupt handler function pointer.
*
* \return 0 if successful, 1 if the maximum number of sources has been defined.
*/
uint32_t pio_handler_set(Pio *p_pio, uint32_t ul_id, uint32_t ul_mask,
uint32_t ul_attr, void (*p_handler) (uint32_t, uint32_t))
{
uint8_t i;
struct s_interrupt_source *pSource;
if (gs_ul_nb_sources >= MAX_INTERRUPT_SOURCES)
return 1;
/* Check interrupt for this pin, if already defined, redefine it. */
for (i = 0; i <= gs_ul_nb_sources; i++) {
pSource = &(gs_interrupt_sources[i]);
if (pSource->id == ul_id && pSource->mask == ul_mask) {
break;
}
}
/* Define new source */
pSource->id = ul_id;
pSource->mask = ul_mask;
pSource->attr = ul_attr;
pSource->handler = p_handler;
if (i == gs_ul_nb_sources + 1) {
gs_ul_nb_sources++;
}
/* Configure interrupt mode */
pio_configure_interrupt(p_pio, ul_mask, ul_attr);
return 0;
}
OSStatus gpio_irq_enable( gpio_port_t gpio_port, gpio_pin_number_t gpio_pin_number, gpio_irq_trigger_t trigger, gpio_irq_handler_t handler, void* arg )
{
//gpio_irq_data_t *pSource;
uint32_t ul_attr;
if (gs_ul_nb_sources >= MAX_INTERRUPT_SOURCES)
return 1;
//Pio *p_pio = (Pio *)ioport_port_to_base(gpio_port);
Pio *p_pio = arch_ioport_port_to_base(gpio_port);
//ioport_pin_t pin = CREATE_IOPORT_PIN(gpio_port, gpio_pin_number);
ioport_port_mask_t ul_mask = ioport_pin_to_mask(CREATE_IOPORT_PIN(gpio_port, gpio_pin_number));
if ( gpio_irq_management_initted == 0 )
{
memset( (void*)gpio_irq_data, 0, sizeof( gpio_irq_data ) );
gpio_irq_management_initted = 1;
}
if (trigger == IRQ_TRIGGER_RISING_EDGE ) {
ul_attr = PIO_IT_RISE_EDGE;
} else if (trigger == IRQ_TRIGGER_FALLING_EDGE ) {
ul_attr = PIO_IT_FALL_EDGE;
} else if (trigger == IRQ_TRIGGER_BOTH_EDGES ) {
ul_attr = PIO_IT_EDGE;
}
//pSource = &(gpio_irq_data[gs_ul_nb_sources]);
gpio_irq_data[gs_ul_nb_sources].owner_port = gpio_port;
if ( gpio_port == PORTA) {
gpio_irq_data[gs_ul_nb_sources].id = ID_PIOA;
// pmc_enable_periph_clk(ID_PIOA);
} else if (gpio_port == PORTB) {
gpio_irq_data[gs_ul_nb_sources].id = ID_PIOB;
// pmc_enable_periph_clk(ID_PIOB);
}
gpio_irq_data[gs_ul_nb_sources].mask = ul_mask;
gpio_irq_data[gs_ul_nb_sources].handler = handler;
gpio_irq_data[gs_ul_nb_sources].arg = arg;
gs_ul_nb_sources++;
/* Configure interrupt mode */
pio_configure_interrupt(p_pio, ul_mask, ul_attr);
if ( gpio_port == PORTA){
NVIC_EnableIRQ( PIOA_IRQn );
pio_handler_set_priority(PIOA, PIOA_IRQn, IRQ_PRIORITY_PIO);
} else if (gpio_port == PORTB) {
NVIC_EnableIRQ( PIOB_IRQn);
pio_handler_set_priority(PIOB, PIOB_IRQn, IRQ_PRIORITY_PIO);
}
pio_enable_interrupt(p_pio, ul_mask);
return kGeneralErr;
}
int initMPU60X0(void)
{
twi_options_t twi_options;
twi_options.master_clk = BOARD_MCK;
twi_options.speed = MPU60X0_SPEED;
twi_options.chip = MPU60X0_BASE_ADDRESS;
// Enable External Interrupt Controller Line.
// Enable interrupts with priority higher than USB.
pio_set_input(PIOA, MPU60X0_BODY_INT_PIN, MPU60X0_BODY_INT_FUNCTION);
pio_configure_interrupt(PIOA, MPU60X0_BODY_INT_PIN, MPU60X0_BODY_INT_FUNCTION);
pio_handler_set(PIOA, ID_PIOA, MPU60X0_BODY_INT_PIN, PIO_IT_RISE_EDGE, MPU60X0BodyInterrupt);
pio_set_input(PIOA, MPU60X0_HEAD_INT_PIN, MPU60X0_HEAD_INT_FUNCTION);
pio_configure_interrupt(PIOA, MPU60X0_HEAD_INT_PIN, MPU60X0_HEAD_INT_FUNCTION);
pio_handler_set(PIOA, ID_PIOA, MPU60X0_HEAD_INT_PIN, PIO_IT_RISE_EDGE, MPU60X0HeadInterrupt);
NVIC_EnableIRQ(PIOA_IRQn);
pio_enable_interrupt(PIOA, MPU60X0_BODY_INT_PIN);
pio_enable_interrupt(PIOA, MPU60X0_HEAD_INT_PIN);
// Initialize TWI driver with options.
if (TWI_SUCCESS != twi_master_init(TWI0, &twi_options))
{
// Disable the interrupts.
pio_disable_interrupt(PIOA, MPU60X0_BODY_INT_PIN);
pio_disable_interrupt(PIOA, MPU60X0_HEAD_INT_PIN);
return(-1);
}
// Enable both RX and TX
TWI0->TWI_IER = TWI_IER_TXRDY | TWI_IER_RXRDY;
return(0);
}
/**
* \brief Set an interrupt handler for the provided pins.
* The provided handler will be called with the triggering pin as its parameter
* as soon as an interrupt is detected.
*
* \param p_pio PIO controller base address.
* \param ul_id PIO ID.
* \param ul_mask Pins (bit mask) to configure.
* \param ul_attr Pins attribute to configure.
* \param p_handler Interrupt handler function pointer.
*
* \return 0 if successful, 1 if the maximum number of sources has been defined.
*/
uint32_t pio_handler_set(Pio *p_pio, uint32_t ul_id, uint32_t ul_mask,
uint32_t ul_attr, void (*p_handler) (uint32_t, uint32_t))
{
struct s_interrupt_source *pSource;
if (gs_ul_nb_sources >= MAX_INTERRUPT_SOURCES)
return 1;
/* Define new source */
pSource = &(gs_interrupt_sources[gs_ul_nb_sources]);
pSource->id = ul_id;
pSource->mask = ul_mask;
pSource->attr = ul_attr;
pSource->handler = p_handler;
gs_ul_nb_sources++;
/* Configure interrupt mode */
pio_configure_interrupt(p_pio, ul_mask, ul_attr);
return 0;
}
