static void
sb_intr_init(int cpuid)
{
int intrnum, intsrc;
/*
* Disable all sources to the interrupt mapper and setup the mapping
* between an interrupt source and the mips hard interrupt number.
*/
for (intsrc = 0; intsrc < NUM_INTSRC; ++intsrc) {
intrnum = sb_route_intsrc(intsrc);
sb_disable_intsrc(cpuid, intsrc);
sb_write_intmap(cpuid, intsrc, intrnum);
#ifdef SMP
/*
* Set up the mailbox interrupt mapping.
*
* The mailbox interrupt is "special" in that it is not shared
* with any other interrupt source.
*/
if (intsrc == INTSRC_MAILBOX3) {
intrnum = platform_ipi_hardintr_num();
sb_write_intmap(cpuid, INTSRC_MAILBOX3, intrnum);
sb_enable_intsrc(cpuid, INTSRC_MAILBOX3);
}
#endif
}
}
void
platform_init_secondary(int cpuid)
{
device_t ic;
int ipi;
ipi = platform_ipi_hardintr_num();
/* XXX: single core/pic */
ic = SLIST_FIRST(&fdt_ic_list_head)->dev;
FDT_IC_SETUP_IPI(ic, cpuid, ipi);
picmap[cpuid] = ic;
/* Unmask the interrupt */
if (cpuid != 0)
mips_wr_status(mips_rd_status() | (((1 << ipi) << 8) << 2));
}
void
platform_init_ap(int cpuid)
{
unsigned reg;
/*
* Clear any pending IPIs.
*/
mips_wr_xburst_core_sts(~(JZ_CORESTS_MIRQ0P << cpuid));
/* Allow IPI mbox for this core */
reg = mips_rd_xburst_reim();
reg |= (JZ_REIM_MIRQ0M << cpuid);
mips_wr_xburst_reim(reg);
/*
* Unmask the ipi interrupts.
*/
reg = hard_int_mask(platform_ipi_hardintr_num());
set_intr_mask(reg);
}
void
platform_init_ap(int cpuid)
{
int ipi_int_mask, clock_int_mask;
KASSERT(cpuid == 1, ("AP has an invalid cpu id %d", cpuid));
/*
* Make sure that kseg0 is mapped cacheable-coherent
*/
kseg0_map_coherent();
sb_intr_init(cpuid);
/*
* Unmask the clock and ipi interrupts.
*/
clock_int_mask = hard_int_mask(5);
ipi_int_mask = hard_int_mask(platform_ipi_hardintr_num());
set_intr_mask(ipi_int_mask | clock_int_mask);
}
