// (spi-setup 'num 'num 'num 'num 'num 'num) -> num any plisp_spi_setup(any ex) { unsigned id, cpol, cpha, is_master, databits; u32 clock, res; any x, y; x = cdr(ex); NeedNum(ex, y = EVAL(car(x))); id = unBox(y); // get id. MOD_CHECK_ID(ex, spi, id); x = cdr(x); NeedNum(ex, y = EVAL(car(x))); is_master = unBox(y); // get type. if (!is_master) err(ex, y, "invalid type - only *spi-master* is supported"); x = cdr(x); NeedNum(ex, y = EVAL(car(x))); clock = unBox(y); // get clock. x = cdr(x); NeedNum(ex, y = EVAL(car(x))); cpol = unBox(y); // clock polarity. if ((cpol != 0) && (cpol != 1)) err(ex, y, "invalid clock polarity."); x = cdr(x); NeedNum(ex, y = EVAL(car(x))); cpha = unBox(y); // clock phase. if ((cpha != 0) && (cpha != 1)) err(ex, y, "invalid clock phase."); x = cdr(x); NeedNum(ex, y = EVAL(car(x))); databits = unBox(y); // get databits. res = platform_spi_setup(id, is_master, clock, cpol, cpha, databits); return box(res); }
LUALIB_API int luaopen_mcu( lua_State *L ) { platform_spi_setup( 1, PLATFORM_SPI_MASTER, PLATFORM_SPI_CPOL_LOW, PLATFORM_SPI_CPHA_LOW, PLATFORM_SPI_DATABITS_8, 0); platform_gpio_mode( PIN_GPIO2, PLATFORM_GPIO_INPUT, PLATFORM_GPIO_PULLUP ); //GPIO2 => pin = 4 /* int i; for(i=0;i<4;i++){ gpio_cb_ref[i] = LUA_NOREF; } platform_gpio_init(intr_callback); //luaL_register( L, AUXLIB_MCU, mcu_map ); // Add constants MOD_REG_NUMBER( L, "PUMP_IN", OUT_PUMP_IN ); MOD_REG_NUMBER( L, "PUMP_OUT", OUT_PUMP_OUT ); MOD_REG_NUMBER( L, "PUMP1", OUT_PUMP1 ); MOD_REG_NUMBER( L, "PUMP2", OUT_PUMP2 ); MOD_REG_NUMBER( L, "PUMP3", OUT_PUMP3 ); MOD_REG_NUMBER( L, "HEATER", OUT_HEATER ); MOD_REG_NUMBER( L, "FAN", OUT_FAN ); MOD_REG_NUMBER( L, "SPRAY", OUT_SPRAY ); MOD_REG_NUMBER( L, "LCD", OUT_LCD ); MOD_REG_NUMBER( L, "LED", OUT_LED ); MOD_REG_NUMBER( L, "PWLED", OUT_PWLED ); MOD_REG_NUMBER( L, "BTN1", IN_BTN1 ); MOD_REG_NUMBER( L, "BTN2", IN_BTN2 ); MOD_REG_NUMBER( L, "BTN3", IN_BTN3 ); MOD_REG_NUMBER( L, "BTN4", IN_BTN4 ); MOD_REG_NUMBER( L, "TEMP", IN_TEMP ); MOD_REG_NUMBER( L, "HUM", IN_HUM ); MOD_REG_NUMBER( L, "PH", IN_PH ); MOD_REG_NUMBER( L, "EC", IN_EC ); MOD_REG_NUMBER( L, "WATER", IN_WATER ); MOD_REG_NUMBER( L, "CAM", IN_CAM ); return 1; */ return 0; }
void initMAC( const u8* bytMacAddress ) { pdata = bytMacAddress; // Initialize the SPI and the CS pin theclock = platform_spi_setup( ENC28J60_SPI_ID, PLATFORM_SPI_MASTER, ENC28J60_SPI_CLOCK, 0, 0, 8 ); platform_pio_op( ENC28J60_CS_PORT, 1 << ENC28J60_CS_PIN, PLATFORM_IO_PIN_SET ); platform_pio_op( ENC28J60_CS_PORT, 1 << ENC28J60_CS_PIN, PLATFORM_IO_PIN_DIR_OUTPUT ); #if defined( ENC28J60_RESET_PORT ) && defined( ENC28J60_RESET_PIN ) platform_pio_op( ENC28J60_RESET_PORT, 1 << ENC28J60_RESET_PIN, PLATFORM_IO_PIN_CLEAR ); platform_pio_op( ENC28J60_RESET_PORT, 1 << ENC28J60_RESET_PIN, PLATFORM_IO_PIN_DIR_OUTPUT ); platform_timer_delay( 0, 30000 ); platform_pio_op( ENC28J60_RESET_PORT, 1 << ENC28J60_RESET_PIN, PLATFORM_IO_PIN_SET ); #endif ResetMac(); // erm. Resets the MAC. // setup memory by defining ERXST and ERXND platform_timer_delay( 0, 20000 ); BankSel(0); // select bank 0 WriteCtrReg(ERXSTL,(u08)( RXSTART & 0x00ff)); WriteCtrReg(ERXSTH,(u08)((RXSTART & 0xff00)>> 8)); WriteCtrReg(ERXNDL,(u08)( RXEND & 0x00ff)); WriteCtrReg(ERXNDH,(u08)((RXEND & 0xff00)>>8)); // Make sure Rx Read ptr is at the start of Rx segment WriteCtrReg(ERXRDPTL, (u08)( RXSTART & 0x00ff)); WriteCtrReg(ERXRDPTH, (u08)((RXSTART & 0xff00)>> 8)); BankSel(1); // select bank 1 WriteCtrReg(ERXFCON,( ERXFCON_UCEN + ERXFCON_CRCEN + ERXFCON_BCEN)); // Initialise the MAC registers BankSel(2); // select bank 2 SetBitField(MACON1, MACON1_MARXEN); // Enable reception of frames WriteCtrReg(MACLCON2, 63); WriteCtrReg(MACON3, MACON3_FRMLNEN + // Type / len field will be checked MACON3_TXCRCEN + // MAC will append valid CRC MACON3_PADCFG0); // All small packets will be padded SetBitField(MACON4, MACON4_DEFER); WriteCtrReg(MAMXFLL, (u08)( MAXFRAMELEN & 0x00ff)); // set max frame len WriteCtrReg(MAMXFLH, (u08)((MAXFRAMELEN & 0xff00)>>8)); WriteCtrReg(MABBIPG, 0x12); // back to back interpacket gap. set as per data sheet WriteCtrReg(MAIPGL , 0x12); // non back to back interpacket gap. set as per data sheet WriteCtrReg(MAIPGH , 0x0C); //Program our MAC address BankSel(3); WriteCtrReg(MAADR1,bytMacAddress[0]); WriteCtrReg(MAADR2,bytMacAddress[1]); WriteCtrReg(MAADR3,bytMacAddress[2]); WriteCtrReg(MAADR4,bytMacAddress[3]); WriteCtrReg(MAADR5,bytMacAddress[4]); WriteCtrReg(MAADR6,bytMacAddress[5]); // Initialise the PHY registes WritePhyReg(PHCON1, 0x00); WritePhyReg(PHCON2, PHCON2_HDLDIS); WriteCtrReg(ECON1, ECON1_RXEN); //Enable the chip for reception of packets SetBitField(EIE, EIE_INTIE); WritePhyReg(PHIE, PHIE_PGEIE|PHIE_PLNKIE); ReadPhyReg(PHIR); }