/*{{{ set_regs*/
static int set_regs(char regs[])
{
int i;
port_out(0x00,GRA_I);
port_out(0x00,GRA_D); /* set/reset */
port_in(IS1_R); /* clear flip-flop */
port_out(0x00,SEQ_I);
port_out(0x01,SEQ_D); /* synchronous reset on */
port_out(regs[MIS+0], MIS_W); /* update misc output register */
port_out(0x1, SEQ_I);
port_out(regs[SEQ+1], SEQ_D); /* update clocking mode */
for (i = 2; i < SEQ_C; i++) { /* sequencer registers */
port_out(i, SEQ_I);
port_out(regs[SEQ+i], SEQ_D);
}
port_out(0x11, CRT_I);
port_out(regs[CRT+0x11]&0x7F, CRT_D); /* deprotect registers 0-7 */
for (i = 0; i < CRT_C; i++) { /* CRT controller registers */
port_out(i, CRT_I);
port_out(regs[CRT+i], CRT_D);
}
for (i = 0; i < GRA_C; i++) { /* graphics controller registers */
port_out(i, GRA_I);
port_out(regs[GRA+i], GRA_D);
}
for (i = 0; i < ATT_C; i++) { /* attribute controller registers */
port_in(IS1_R); /* reset flip-flop */
port_out(i, ATT_IW);
port_out(regs[ATT+i],ATT_IW);
}
port_out(0x00, SEQ_I);
port_out(0x03, SEQ_D); /* synchronous reset off */
return 0;
}
static int att20c490_probe(void)
{
unsigned char oldcomm, notcomm, oldpel, v;
int flag = 0;
_ramdac_dactocomm();
oldcomm = port_in(PEL_MSK);
_ramdac_dactopel();
oldpel = port_in(PEL_MSK);
notcomm = ~oldcomm;
port_out_r(PEL_MSK, notcomm);
_ramdac_dactocomm();
v = port_in(PEL_MSK);
if (v != notcomm) {
if ((_ramdac_setcomm(0xe0) & 0xe0) == 0xe0) {
if ((_ramdac_setcomm(0x60) & 0xe0) == 0) {
if ((_ramdac_setcomm(2) & 2) > 0)
flag = 1; /* 20c490 */
else
flag = 1; /* 20c493 */
} else {
_ramdac_setcomm(oldcomm);
if (port_in(PEL_MSK) == notcomm)
if (_ramdac_setcomm(0xFF) == 0xFF)
flag = 1; /* 20c491/20c492 */
}
}
}
_ramdac_dactocomm();
port_out_r(PEL_MSK, oldcomm);
_ramdac_dactopel();
port_out_r(PEL_MSK, oldpel);
return flag;
}
/* None found. */
return NULL;
if (dac->probe()) {
dac->initialize();
return dac;
}
dacs_to_probe++;
}
}
int __svgalib_setDacSpeed(int dacspeed, int defspeed)
{
if (!dacspeed) {
if (__svgalib_driver_report)
fprintf(stderr,"svgalib: Assuming %dMHz DAC.\n", defspeed / 1000);
dacspeed = defspeed;
} else {
if (__svgalib_driver_report)
fprintf(stderr,"svgalib: DAC speed set to %dMHz.\n", dacspeed / 1000);
}
return dacspeed;
}
#ifndef __OPTIMIZE__ /* otherwise inlined from ramdac.h */
void _ramdac_dactocomm(void)
{
port_in(PEL_IW);
port_in(PEL_MSK);
port_in(PEL_MSK);
port_in(PEL_MSK);
port_in(PEL_MSK);
}
static void tvga8900_setpage(int page)
{
port_out(0x0b, SEQ_I);
port_out(port_in(SEQ_D), SEQ_D);
port_in(SEQ_D); /* select new mode regs */
port_out(0x0e, SEQ_I);
port_out(page ^ 0x02, SEQ_D); /* select the page */
}
static int GENDAC_probe(void)
{
int i;
port_in(0x3c6);
port_in(0x3c6);
port_in(0x3c6);
i=port_in(0x3c6);
if(i==177) return 1;
return 0;
}
static void att20c490_init(void)
{
if (__svgalib_driver_report)
fprintf(stderr,"svgalib: Using AT&T20C490-compatible truecolor DAC.\n");
#if 0
dactocomm();
port_in(PEL_MSK); /* Skip command register. */
fprintf(stderr,"svgalib: DAC Manufacturer ID = 0x%02X, ", port_in(PEL_MSK));
fprintf(stderr,"Device ID = 0x%02X.\n", port_in(PEL_MSK));
#endif
}
int set_regs(u_char regs[])
{
int i;
/* port_out(dosemu_regs->regs[FCR], FCR_W); */
/* update misc output register */
port_out(regs[MIS], MIS_W);
/* write sequencer registers */
/* synchronous reset on */
port_out(0x00, SEQ_I);
port_out(0x01, SEQ_D);
port_out(0x01, SEQ_I);
port_out(regs[SEQ + 1] | 0x20, SEQ_D);
/* synchronous reset off */
port_out(0x00, SEQ_I);
port_out(0x03, SEQ_D);
for (i = 2; i < SEQ_C; i++) {
port_out(i, SEQ_I);
port_out(regs[SEQ + i], SEQ_D);
}
/* deprotect CRT registers 0-7 */
port_out(0x11, CRT_I);
port_out(port_in(CRT_D) & 0x7F, CRT_D);
/* write CRT registers */
for (i = 0; i < CRT_C; i++) {
port_out(i, CRT_I);
port_out(regs[CRT + i], CRT_D);
}
/* write graphics controller registers */
for (i = 0; i < GRA_C; i++) {
port_out(i, GRA_I);
port_out(regs[GRA + i], GRA_D);
}
/* write attribute controller registers */
for (i = 0; i < ATT_C; i++) {
port_in(IS1_R); /* reset flip-flop */
port_out(i, ATT_IW);
port_out(regs[ATT + i], ATT_IW);
}
/* port_out(dosemu_regs->regs[CRTI], CRT_I);
port_out(dosemu_regs->regs[GRAI], GRA_I);
port_out(dosemu_regs->regs[SEQI], SEQ_I); */
/* debug_vid("CRTI=0x%02x\n",dosemu_regs->regs[CRTI]);
debug_vid("GRAI=0x%02x\n",dosemu_regs->regs[GRAI]);
debug_vid("SEQI=0x%02x\n",dosemu_regs->regs[SEQI]); */
return (0);
}
void trident_allow_svga(void)
{
u_char dummy;
trident_set_old_regs();
port_out(0x0d, SEQ_I);
dummy = port_in(SEQ_D);
v_printf("Dummy then = 0x%02x\n", dummy);
port_out(((dummy & ~0x20) | 0x10), SEQ_D);
dummy = port_in(SEQ_D);
v_printf("Dummy now = 0x%02x\n", dummy);
trident_set_new_regs();
return;
}
static int ICW_probe(void)
{
unsigned char mi, di;
_ramdac_dactocomm();
port_in(PEL_MSK); /* Control register 0. */
mi = port_in(PEL_MSK); /* Manufacturer ID. */
di = port_in(PEL_MSK); /* Device ID. */
if (mi == 0x84) {
if (di == 0x98)
return 1;
fprintf(stderr,"svgalib: ICW_probe: Unknown IC Works DAC.\n");
}
return 0;
}
static int saveregs(unsigned char *regs)
{
/* We can't read the registers from an EGA card. */
/* We just report the expected values. */
const unsigned char *r;
int i;
if (lastmode == TEXT)
r = text_regs;
else
r = LOOKUPMODE(ega_modes, lastmode);
if (r == NULL) {
printf("svgalib: egadrv.c/saveregs(): internal error\n");
exit(-1);
}
memcpy(regs, r, CRT_C + ATT_C + GRA_C + SEQ_C + MIS_C);
/* save all readable EGA registers; others are default */
/* is this correct (even in graphics mode) ?? */
for (i = 0x0C; i < 0x10; i++) {
port_out(i, __svgalib_CRT_I);
regs[CRT + i] = port_in(__svgalib_CRT_D);
}
return CRT_C + ATT_C + GRA_C + SEQ_C + MIS_C;
}
unsigned char _ramdac_setcomm(unsigned char data)
{
_ramdac_dactocomm();
port_out_r(PEL_MSK, data);
_ramdac_dactocomm();
return port_in(PEL_MSK);
}
void trident_restore_ext_regs(u_char xregs[], u_short xregs16[])
{
trident_set_old_regs();
port_out(0x0d, SEQ_I);
port_out(xregs[1], SEQ_D);
port_out(0x0e, SEQ_I);
port_out(xregs[2], SEQ_D);
trident_set_new_regs();
port_out(0x0e, SEQ_I);
port_out(0x82, SEQ_D);
port_out(0x0c, SEQ_I);
port_out(xregs[0], SEQ_D);
v_printf("Check for change in 0x%02x\n", port_in(SEQ_D));
port_out(0x0d, SEQ_I);
port_out(xregs[3], SEQ_D);
port_out(0x0e, SEQ_I);
port_out(xregs[4] ^ 0x02, SEQ_D);
port_out(0x0f, SEQ_I);
port_out(xregs[5], SEQ_D);
port_out(0x1e, CRT_I);
port_out(xregs[6], CRT_D);
port_out(0x1f, CRT_I);
port_out(xregs[7], CRT_D);
port_out(0x0f, GRA_I);
port_out(xregs[8], GRA_D);
port_out(0x0c, SEQ_I);
port_out(xregs[0], SEQ_D);
return;
}
static void ark_setregs(const unsigned char regs[], int mode)
{
ark_unlock();
/* Write extended registers. */
__svgalib_outCR(0x46, __svgalib_inCR(0x46) | 0x20); /* Disable Clock Select Latch. */
__svgalib_outSR(0x10, regs[ARK_SR10]);
__svgalib_outSR(0x11, regs[ARK_SR11]);
__svgalib_outSR(0x12, regs[ARK_SR12]);
__svgalib_outSR(0x13, regs[ARK_SR13]);
__svgalib_outSR(0x14, regs[ARK_SR14]);
__svgalib_outSR(0x15, regs[ARK_SR15]);
__svgalib_outSR(0x16, regs[ARK_SR16]);
__svgalib_outSR(0x18, regs[ARK_SR18]);
__svgalib_outSR(0x1C, regs[ARK_SR1C]);
__svgalib_outSR(0x1D, regs[ARK_SR1D]);
__svgalib_outCR(0x40, regs[ARK_CR40]);
__svgalib_outCR(0x41, regs[ARK_CR41]);
__svgalib_outCR(0x42, regs[ARK_CR42]);
__svgalib_outCR(0x44, regs[ARK_CR44]);
port_in(0x3C8);
port_out_r(0x3C6, regs[ARK_PELMASK]);
dac_used->restoreState(regs + ARK_DAC_OFFSET);
__svgalib_outCR(0x46, regs[ARK_CR46]);
}
static int get_lut(int index, int *red, int *green, int *blue)
{
if (__svgalib_novga) return 0;
/* prevents lockups on mach64 */
if ((__svgalib_chipset == MACH64)) {
port_out_r(0x02ec+0x5c00,index);
*red=port_in(0x02ec+0x5c01);
*green=port_in(0x02ec+0x5c01);
*blue=port_in(0x02ec+0x5c01);
return 0;
}
__svgalib_inpal(index,red,green,blue);
return 0;
}
/**
* Write bytes to the parallel port.
*
* Timing can be modified by inserting additional delays according to the
* \c PortWait setting in \c LCDd.conf: \n
* Portwait = 0; no delays, only BUSY bit checked\n
* Portwait = 1; additional WR off to check BUSY delay\n
* Portwait = 2; as 1 + additional WR pulse width\n
* Portwait = 3; as 2 + additional WR setup delay\n
* Portwait >= 4; as 3 + additional wait delay to next command
*
* \param drvthis Pointer to driver
* \param dat Pointer to array storing the data
* \param length Number of bytes to write
*/
void
serialVFD_write_parallel (Driver *drvthis, unsigned char *dat, size_t length)
{
#ifdef HAVE_PCSTYLE_LPT_CONTROL
PrivateData *p = drvthis->private_data;
int i_para, j_para;
if (length <= 0)
return;
for (i_para = 0; i_para < length; i_para++) {
port_out(p->port, dat[i_para]);
/* data to WR enable delay */
if (p->para_wait > 2)
port_in(p->port+1);
port_out(p->port+2, WR_on);
/* additional WR pulse width */
if (p->para_wait > 1)
port_in(p->port+1);
port_out(p->port+2, WR_off);
/* additional BUSY delay time */
if (p->para_wait > 0)
port_in(p->port+1);
/*
* Check MAXBUSY times if the BUSY bit is set. Note: BUSY bit
* on parallel port is hardware inverted, but VFD is ready
* if its BUSY bit is cleared (thus high on PC).
*/
for (j_para = 0; j_para < MAXBUSY; j_para++) {
if ((port_in(p->port+1)) & BUSY)
break;
}
/* wait time of next WR */
for (j_para = 3; j_para < p->para_wait; j_para++)
port_in(p->port+1);
}
#endif
}
/////////////////////////////////////////////////////////////////
// This function returns true if a powered and working STV5730
// hardware is present at p->port
static int
stv5730_detect (unsigned int port)
{
int i;
for (i = 0; i < 10; i++) {
port_out(port, STV5730_TEST_O);
stv5730_upause(IODELAY);
if ((port_in(port + 1) & STV5730_TEST_I) == 0)
return -1;
port_out(port, 0);
stv5730_upause(IODELAY);
if ((port_in(port + 1) & STV5730_TEST_I) != 0)
return -1;
}
return 0;
}
void trident_set_new_regs(void)
{
u_char dummy;
port_out(0x0b, SEQ_I);
port_out(0x00, SEQ_D);
dummy = port_in(SEQ_D);
return;
}
//读数据
u8 lcd1602_read_data(void)
{
RS_SET;
RW_SET;
EN_CLR;
EN_CLR;
EN_SET;
port_in();
return port_read();
}
u_char trident_get_svga(void)
{
u_char dummy;
trident_set_old_regs();
port_out(0x0d, SEQ_I);
dummy = port_in(SEQ_D) & 0x10;
trident_set_new_regs();
v_printf("Trident get SVGA, dummy = 0x%02x\n", dummy);
return (dummy);
}
/**
* API: Get key from keypad. This routine implements the polling of the
* keypad. This is not part of the SDEC LCD, but is wired through the
* parallel port as well. It seems natural to include it in this driver.
* Different boxes have different mapping to keys, but all codes are
* fortunately unique. As this routine is called periodically by the server,
* this is where we added the logic to turn off the backlight after some
* time.
*/
MODULE_EXPORT const char *
sdeclcd_get_key(Driver *drvthis)
{
PrivateData *p = (PrivateData *)drvthis->private_data;
unsigned kbd;
/*
* check backlight timer. It is important to make sure we turn the
* light off when there is no activity. With a half life of only
* 3,000 hours, we need to preserve it.
*/
if (time(NULL) - p->bklgt_lasttime >= p->bklgt_timer)
p->bklgt = BACKLIGHT_OFF;
else
p->bklgt = BACKLIGHT_ON;
/* read keyboard status */
kbd = port_in(LPT_STATUS) & LPT_STUS_MASK;
/* check if keyboard changed */
if (kbd == p->lastkbd)
return NULL;
/* reset backlight counter */
p->bklgt_lasttime = time(NULL);
p->lastkbd = kbd;
/*-
* Return key text according to status reg mapping:
* X-e U:70 R:F8 D:68 L:58 Rel:78
* X-peak U:C8 R:E0 D:C0 L:E8 Rel: 88,80,A8,A0
*/
switch (kbd) {
case 0x70:
case 0xC8:
return ("Up");
case 0xF8:
case 0xE0:
return ("Right");
case 0x68:
case 0xC0:
return ("Down");
case 0x58:
case 0xE8:
return ("Left");
case 0x78: /* button Releases */
case 0x88:
case 0x80:
case 0xA8:
case 0xA0:
return (NULL);
default: /* Code not mapped: */
report(RPT_DEBUG, "LCDd sdeclcd.c/sdeclcd_get_key() %2x unmapped", kbd);
return (NULL);
}
}
void
serialVFD_write_parallel (Driver *drvthis, unsigned char *dat, size_t length)
{
#ifdef HAVE_PCSTYLE_LPT_CONTROL
PrivateData *p = drvthis->private_data;
int i_para, j_para;
for (i_para = 0; i_para < length; i_para++) {
port_out(p->port, dat[i_para]);
// port_in(p->port+1);
port_out(p->port+2, WR_on);
port_in(p->port+1);
port_out(p->port+2, WR_off);
port_in(p->port+1);
for (j_para = 0; j_para < MAXBUSY; j_para++) {
if ((port_in(p->port+1)) & Busy)
break;
}
}
#endif
}
void trident_disallow_svga(void)
{
u_char dummy;
trident_set_old_regs();
port_out(0x0d, SEQ_I);
dummy = port_in(SEQ_D);
port_out(((dummy | 0x20) & ~0x10), SEQ_D);
trident_set_new_regs();
v_printf("Disallow SVGA Modes = 0x%02x\n", dummy & ~0x10);
return;
}
static int set_vga_perm(int flag)
{
/* get I/O permissions for VGA registers */
if (ioperm(CRT_IC, 1, flag)) {
printf("VGAlib: can't get I/O permissions \n");
exit (-1);
}
ioperm(CRT_IM, 1, flag);
ioperm(ATT_IW, 1, flag);
ioperm(GRA_I, 1, flag);
ioperm(SEQ_I, 1, flag);
ioperm(PEL_IW, 1, flag);
ioperm(PEL_IR, 1, flag);
ioperm(CRT_DC, 1, flag);
ioperm(CRT_DM, 1, flag);
ioperm(ATT_R, 1, flag);
ioperm(GRA_D, 1, flag);
ioperm(SEQ_D, 1, flag);
ioperm(MIS_R, 1, flag);
ioperm(MIS_W, 1, flag);
ioperm(IS1_RC, 1, flag);
ioperm(IS1_RM, 1, flag);
ioperm(PEL_D, 1, flag);
/* ET4000 registers */
ioperm(0x3bf, 1, flag);
ioperm(0x3cc, 1, flag);
ioperm(0x3d8, 1, flag);
ioperm(0x3b8, 1, flag);
ioperm(0x3c3, 1, flag);
ioperm(0x3cd, 1, flag);
if (flag)
{
/* color or monochrome text emulation? */
color_text = port_in(MIS_R)&0x01;
/* chose registers for color/monochrome emulation */
if (color_text) {
CRT_I = CRT_IC;
CRT_D = CRT_DC;
IS1_R = IS1_RC;
} else {
CRT_I = CRT_IM;
CRT_D = CRT_DM;
IS1_R = IS1_RM;
}
}
}
/* get ioperms to allow havoc to occur */
int get_perm(void)
{
permissions++;
if (permissions > 1) {
return 0;
}
if (config.vga) { /* hope this will not lead to problems with ega/cga */
/* get I/O permissions for VGA registers */
if (set_ioperm(0x3b0, 0x3df - 0x3b0 + 1, 1)) {
debug_vid("VGA: can't get I/O permissions \n");
leaveemu(ERR);
}
if (((config.chipset == S3) || (config.chipset == CIRRUS)) &&
(set_ioperm(0x102, 1, 1) || set_ioperm(0x2ea, 4, 1))) {
debug_vid("S3/CIRRUS: can't get I/O permissions \n");
leaveemu(ERR);
}
if (config.chipset == ATI && (set_ioperm(0x102, 1, 1) || set_ioperm(0x1ce, 2, 1) || set_ioperm(0x2ec, 4, 1))) {
debug_vid("ATI: can't get I/O permissions \n");
leaveemu(ERR);
}
/* color or monochrome text emulation? */
color_text = port_in(MIS_R) & 0x01;
/* chose registers for color/monochrome emulation */
if (color_text) {
CRT_I = CRT_IC;
CRT_D = CRT_DC;
IS1_R = IS1_RC;
FCR_W = FCR_WC;
} else {
CRT_I = CRT_IM;
CRT_D = CRT_DM;
IS1_R = IS1_RM;
FCR_W = FCR_WM;
}
} else if (config.usesX || (config.console_video && (config.cardtype == CARD_MDA))) {
if (set_ioperm(0x3b4, 1, 1) ||
set_ioperm(0x3b5, 1, 1) ||
set_ioperm(0x3b8, 1, 1) ||
set_ioperm(0x3ba, 1, 1) ||
set_ioperm(0x3bf, 1, 1)) {
debug_vid("HGC: can't get I/O permissions \n");
leaveemu(ERR);
}
}
debug_vid("Permission allowed\n");
return 0;
}
int cmos_read(int port)
{
unsigned char holder;
h_printf("CMOS read. from add: 0x%02x\n", cmos.address);
switch(cmos.address)
{
case 0: /* RTC seconds */
case 2: /* minutes */
case 4: /* hours */
case 6: /* day of week */
case 7: /* day of month */
case 8: /* month */
case 9: /* year */
return (cmos_date(cmos.address));
case 1: /* RTC seconds alarm */
case 3: /* minutes alarm */
case 5: /* hours alarm */
h_printf("CMOS alarm read %d...UNIMPLEMENTED!\n", cmos.address);
return cmos.subst[cmos.address];
}
/* date functions return, so hereafter all values should be static
* after boot time...
*/
if (cmos.flag[cmos.address]) /* this reg has been written to */
{
holder=cmos.subst[cmos.address];
h_printf("CMOS: substituting written value 0x%02x for read\n",holder);
}
#ifdef DANGEROUS_CMOS
else if (!ioperm(0x70,2,1))
{
h_printf("CMOS: really reading!\n");
port_out((cmos.address & ~0xc0)|0x80, 0x70);
holder=port_in(0x71);
ioperm(0x70,2,0);
}
#endif
else error("CMOS: Can't get permissions for true I/O to 0x70, 0x71\n");
h_printf("CMOS read. add: 0x%02x = 0x%02x\n", cmos.address, holder);
return holder;
}
//读状态
u8 lcd1602_busy(void)
{
u8 result;
port_write(0xff);
RS_CLR;
RW_SET;
EN_CLR;
EN_CLR;
EN_SET;
asm("nop");
// asm("nop");
//delay_ms(5);
port_in();
while(port_read() & 0x80);
//EN_CLR;
return port_read();
}
void trident_save_ext_regs(u_char xregs[], u_short xregs16[])
{
port_out(0x0c, SEQ_I);
xregs[0] = port_in(SEQ_D) & 0xff;
trident_set_old_regs();
port_out(0x0d, SEQ_I);
xregs[1] = port_in(SEQ_D) & 0xff;
port_out(0x0e, SEQ_I);
xregs[2] = port_in(SEQ_D) & 0xff;
trident_set_new_regs();
port_out(0x0d, SEQ_I);
xregs[3] = port_in(SEQ_D) & 0xff;
port_out(0x0e, SEQ_I);
xregs[4] = port_in(SEQ_D) & 0xff;
port_out(0x0f, SEQ_I);
xregs[5] = port_in(SEQ_D) & 0xff;
port_out(0x1e, CRT_I);
xregs[6] = port_in(CRT_D) & 0xff;
port_out(0x1f, CRT_I);
xregs[7] = port_in(CRT_D) & 0xff;
port_out(0x0f, GRA_I);
xregs[8] = port_in(GRA_D) & 0xff;
return;
}
unsigned char read_port(unsigned short port)
{
unsigned char r;
int i = find_port(port, IO_READ);
/* FIXME: stuff does/should check find_port first, so don't waste
time checking again! ASSERT!! */
if (i == -1)
return (0xff);
if (!video_port_io)
enter_priv_on();
if (port <= 0x3ff)
set_ioperm(port, 1, 1);
else
priv_iopl(3);
if (!video_port_io)
leave_priv_setting();
r = port_in(port);
if (!video_port_io)
enter_priv_on();
if (port <= 0x3ff)
set_ioperm(port, 1, 0);
else
priv_iopl(0);
if (!video_port_io)
leave_priv_setting();
if (!video_port_io) {
r &= ports[i].andmask;
r |= ports[i].ormask;
} else
video_port_io = 0;
LOG_IO(port, r, '>', 0xff);
i_printf("read port 0x%x gave %02x at %04x:%04x\n",
port, r, LWORD(cs), LWORD(eip));
return (r);
}
char safe_port_in_byte(const unsigned short port)
{
unsigned char value = 0;
if (i_am_root) {
int result;
result = set_ioperm(port, 1, 1);
if (result)
error("failed to enable port %x\n", port);
value = port_in(port);
result = set_ioperm(port, 1, 0);
if (result)
error("failed to disable port %x\n", port);
} else
i_printf("want to ");
i_printf("in(%x)", port);
if (i_am_root)
i_printf(" = 0x%x", value);
i_printf("\n");
return value;
}
static void GENDAC_savestate(unsigned char *regs)
{
unsigned char tmp;
tmp = __svgalib_inSR(0x1c);
__svgalib_outSR(0x1c, tmp | 0x80);
regs[SDAC_COMMAND] = port_in(0x3c6);
regs[SDAC_PLL_WRITEINDEX] = port_in(0x3c8); /* PLL write index */
regs[SDAC_PLL_READINDEX] = port_in(0x3c7); /* PLL read index */
port_out_r(0x3c7, 2); /* index to f2 reg */
regs[SDAC_PLL_M] = port_in(0x3c9); /* f2 PLL M divider */
regs[SDAC_PLL_N1_N2] = port_in(0x3c9); /* f2 PLL N1/N2 divider */
port_out_r(0x3c7, 0x0e); /* index to PLL control */
regs[SDAC_PLL_CONTROL] = port_in(0x3c9); /* PLL control */
__svgalib_outSR(0x1c, tmp & ~0x80);
}
