static void print_ddr3_memory_setup(void)
{
#if CONFIG_DEBUG_RAM_SETUP
print_debug("DDR3 Timing Reg 0-3:\n");
print_debug("NB 6e : ");
print_debug_hex16(pci_read_config16(NB, 0x6e));
print_debug("\nNB 74 : ");
print_debug_hex32(pci_read_config32(NB, 0x74));
print_debug("\nNB 78 : ");
print_debug_hex32(pci_read_config32(NB, 0x78));
print_debug("\nNB 7c : ");
print_debug_hex32(pci_read_config32(NB, 0x7c));
u16 mbr = pci_read_config16(NB, 0x6c);
print_debug("\nNB 6c(MBR) : ");
print_debug_hex16(mbr);
const char *s;
u8 col = get_ddr3_mem_reg_col(mbr);
if (col == DDR3_COL_10BIT)
s = " (COL=10";
else
s = " (COL=11";
print_debug(s);
u8 row = get_ddr3_mem_reg_row(mbr);
switch (row) {
case DDR3_ROW_13BIT:
s = ", ROW = 13";
break;
case DDR3_ROW_14BIT:
s = ", ROW = 14";
break;
case DDR3_ROW_15BIT:
s = ", ROW = 15";
break;
default:
s = ", ROW = 16";
break;
}
print_debug(s);
u8 size = get_ddr3_mem_reg_size(mbr);
switch (size) {
case DDR3_SIZE_64M:
s = ", 64M";
break;
case DDR3_SIZE_128M:
s = ", 128M";
break;
case DDR3_SIZE_256M:
s = ", 256M";
break;
case DDR3_SIZE_512M:
s = ", 512M";
break;
case DDR3_SIZE_1GB:
s = ", 1GB";
break;
case DDR3_SIZE_2GB:
s = ", 2GB";
break;
}
print_debug(s);
u8 mask = get_ddr3_mem_reg_c1m(mbr);
if (mask == DDR3_C1M_ACTIVE)
s = ", CS MASK Enable)\n";
else
s = ", CS Mask Disable)\n";
print_debug(s);
#endif
}
/*
* Logical device 4, 5 and 7 are being deactivated. Logical Device 1 seems to
* be another serial (?), it is also deactivated on the HP machine.
*/
static void pilot_early_init(device_t dev)
{
unsigned port = dev >> 8;
print_debug("Using port: ");
print_debug_hex16(port);
print_debug("\n");
pilot_disable_serial(PNP_DEV(port, 0x1));
print_debug("disable serial 1\n");
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(PNP_DEV(port, 0x3));
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, 0x60, 0x0b00);
pnp_set_iobase(dev, 0x62, 0x0b80);
pnp_set_iobase(dev, 0x64, 0x0b84);
pnp_set_iobase(dev, 0x66, 0x0b86);
pnp_set_enable(dev, 1);
pnp_exit_ext_func_mode(dev);
/*
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(PNP_DEV(port, 0x3));
pnp_exit_ext_func_mode(dev);
pnp_enter_ext_func_mode(dev);
pnp_set_enable(PNP_DEV(port, 0x3), 0);
pnp_exit_ext_func_mode(dev);
*/
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(PNP_DEV(port, 0x4));
pnp_exit_ext_func_mode(dev);
pnp_enter_ext_func_mode(dev);
pnp_set_enable( PNP_DEV(port, 0x4), 0);
pnp_exit_ext_func_mode(dev);
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(PNP_DEV(port, 0x5));
pnp_exit_ext_func_mode(dev);
pnp_enter_ext_func_mode(dev);
pnp_set_enable(PNP_DEV(port, 0x5), 0);
pnp_exit_ext_func_mode(dev);
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(PNP_DEV(port, 0x6));
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0x60);
pnp_set_iobase(dev, PNP_IDX_IO1, 0x64);
pnp_set_irq(dev, PNP_IDX_IRQ0, 1);
pnp_set_drq(dev, 0x71, 3);
pnp_set_enable(dev, 0);
pnp_exit_ext_func_mode(dev);
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(PNP_DEV(port, 0xe));
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0x70);
pnp_set_iobase(dev, PNP_IDX_IO1, 0x72);
pnp_set_irq(dev, PNP_IDX_IRQ0, 8);
pnp_set_drq(dev, 0x71, 3);
pnp_set_enable(dev, 0);
pnp_exit_ext_func_mode(dev);
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(PNP_DEV(port, 0x7));
pnp_exit_ext_func_mode(dev);
pnp_enter_ext_func_mode(dev);
pnp_set_enable(PNP_DEV(port, 0x7), 0);
pnp_exit_ext_func_mode(dev);
/*
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(PNP_DEV(port, 0x8));
pnp_exit_ext_func_mode(dev);
pnp_enter_ext_func_mode(dev);
pnp_set_enable(PNP_DEV(port, 0x8), 0);
pnp_exit_ext_func_mode(dev);
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(PNP_DEV(port, 0x9));
pnp_exit_ext_func_mode(dev);
pnp_enter_ext_func_mode(dev);
pnp_set_enable(PNP_DEV(port, 0x9), 0);
pnp_exit_ext_func_mode(dev);
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(PNP_DEV(port, 0x10));
pnp_exit_ext_func_mode(dev);
pnp_enter_ext_func_mode(dev);
pnp_set_enable(PNP_DEV(port, 0x10), 0);
pnp_exit_ext_func_mode(dev);
*/
}
