void print_dbg_ulong(unsigned long n)
{
// Redirection to the debug USART.
USART_BEGIN_DBG_TX;
print_ulong(DBG_USART, n);
USART_END_DBG_TX;
}
/*! \brief Toggle LED
*/
int32_t toggle_led(uint32_t number_of_toggles)
{
volatile uint32_t start_count, end_count;
int32_t result = 0;
start_count = Get_system_register(AVR32_COUNT);
for (uint32_t i = 0; i < number_of_toggles; i++) {
LED_Toggle(LED0);
}
end_count = Get_system_register(AVR32_COUNT);
result = end_count - start_count;
print(EXAMPLE_USART, " - Number of cycles: ");
print_ulong(EXAMPLE_USART, result);
print(EXAMPLE_USART, "\r\n");
return result;
}
void print_dbg_ulong(unsigned long n)
{
// Redirection to the debug USART.
print_ulong(DBG_USART, n);
}
static int print_uconstant(const struct conf_variable *cp, const char *pathname)
{
print_ulong(cp->name, (unsigned long) cp->value);
return 0;
}
/*! \brief The main function.
*/
int main(void)
{
int32_t result;
#if UC3L /* UC3L series only */
// Note: on the AT32UC3L-EK board, there is no crystal/external clock connected
// to the OSC0 pinout XIN0/XOUT0. We shall then program the DFLL and switch the
// main clock source to the DFLL.
pcl_configure_clocks(&pcl_dfll_freq_param);
// Note: since it is dynamically computing the appropriate field values of the
// configuration registers from the parameters structure, this function is not
// optimal in terms of code size. For a code size optimal solution, it is better
// to create a new function from pcl_configure_clocks_dfll0() and modify it
// to use preprocessor computation from pre-defined target frequencies.
#else // else for all other series
// Configure Osc0 in crystal mode (i.e. use of an external crystal source, with
// frequency FOSC0) with an appropriate startup time then switch the main clock
// source to Osc0.
pcl_switch_to_osc(PCL_OSC0, FOSC0, OSC0_STARTUP);
#endif
const gpio_map_t usart_gpio_map =
{
{EXAMPLE_USART_RX_PIN, EXAMPLE_USART_RX_FUNCTION},
{EXAMPLE_USART_TX_PIN, EXAMPLE_USART_TX_FUNCTION}
};
// Assign GPIO to USART.
gpio_enable_module(usart_gpio_map,
sizeof(usart_gpio_map) / sizeof(usart_gpio_map[0]));
static const usart_options_t usart_options =
{
.baudrate = 57600,
.charlength = 8,
.paritytype = USART_NO_PARITY,
.stopbits = USART_1_STOPBIT,
.channelmode = 0
};
// Initialize USART in RS232 mode.
usart_init_rs232(EXAMPLE_USART, &usart_options, FPBA);
usart_write_line(EXAMPLE_USART, "\x1B[2J\x1B[H\r\nATMEL\r\n");
usart_write_line(EXAMPLE_USART, "AVR UC3 - HMATRIX example\r\n\r\n");
// First test with AVR32_HMATRIX_DEFMSTR_TYPE_NO_DEFAULT
print(EXAMPLE_USART, "- Test 1 ----------------------------------------\r\n");
print(EXAMPLE_USART, "------ All Slave Default Master Types are: ------\r\n");
print(EXAMPLE_USART, " - No Default Master\r\n");
print(EXAMPLE_USART, " - leds Toggle: ");
print_ulong(EXAMPLE_USART, NB_TOGGLE);
print(EXAMPLE_USART, " times\r\n");
#if defined(AVR32_HMATRIX)
configure_hmatrix(AVR32_HMATRIX_DEFMSTR_TYPE_NO_DEFAULT);
#elif defined(AVR32_HMATRIXB)
configure_hmatrix(AVR32_HMATRIXB_DEFMSTR_TYPE_NO_DEFAULT);
#endif
result = toggle_led(NB_TOGGLE);
// Second test with AVR32_HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT
print(EXAMPLE_USART, "- Test 2 ----------------------------------------\r\n");
print(EXAMPLE_USART, "------ All Slave Default Master Types are: ------\r\n");
print(EXAMPLE_USART, " - Last Default Master\r\n");
print(EXAMPLE_USART, " - No Default Master\r\n");
print(EXAMPLE_USART, " - leds Toggle: ");
print_ulong(EXAMPLE_USART, NB_TOGGLE);
print(EXAMPLE_USART, " times\r\n");
#if defined(AVR32_HMATRIX)
configure_hmatrix(AVR32_HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT);
#elif defined(AVR32_HMATRIXB)
configure_hmatrix(AVR32_HMATRIXB_DEFMSTR_TYPE_LAST_DEFAULT);
#endif
result -= toggle_led(NB_TOGGLE);
print(EXAMPLE_USART, "--------------------------------------------------\r\n");
print_ulong(EXAMPLE_USART, result);
print(EXAMPLE_USART, " Cycles saved between test 1 and test 2\r\nDone!");
//*** Sleep mode
// This program won't be doing anything else from now on, so it might as well
// sleep.
// Modules communicating with external circuits should normally be disabled
// before entering a sleep mode that will stop the module operation.
// Make sure the USART dumps the last message completely before turning it off.
while(!usart_tx_empty(EXAMPLE_USART));
pcl_disable_module(EXAMPLE_USART_CLOCK_MASK);
// Since we're going into a sleep mode deeper than IDLE, all HSB masters must
// be stopped before entering the sleep mode: none is acting currently in this
// example so nothing to do for this example.
// If there is a chance that any PB write operations are incomplete, the CPU
// should perform a read operation from any register on the PB bus before
// executing the sleep instruction.
AVR32_INTC.ipr[0]; // Dummy read
// Go to STATIC sleep mode.
SLEEP(AVR32_PM_SMODE_STATIC);
while (true);
}
//! 1) Configure two DMACA channels:
//! - RAM -> AES
//! - AES -> RAM
//! 2) Set the AES cryptographic key and init vector.
//! 3) Start the process
//! 4) Check the result on the first 16 Words.
void test_ram_aes_ram(unsigned short int u16BufferSize, unsigned int *pSrcBuf, unsigned int *pDstBuf)
{
unsigned int i;
unsigned char TestResult = true;
//====================
// Configure the DMACA.
//====================
// Enable the DMACA
AVR32_DMACA.dmacfgreg = 1 << AVR32_DMACA_DMACFGREG_DMA_EN_OFFSET;
//*
//* Configure the DMA RAM -> AES channel.
//*
// ------------+--------+------+------------+--------+-------+----------------
// Transfer | Source | Dest | Flow | Width | Chunk | Buffer
// type | | | controller | (bits) | size | Size
// ------------+--------+------+------------+--------+-------+----------------
// | | | | | |
// Mem-to-Per | RAM | AES | DMACA | 32 | 4 | u16BufferSize
// | | | | | |
// ------------+--------+------+------------+--------+-------+----------------
// NOTE: We arbitrarily choose to use channel 0 for this datapath
// Src Address: the InputData[] array
AVR32_DMACA.sar0 = (unsigned long)pSrcBuf;
// Dst Address: the AES_IDATAXR registers.
AVR32_DMACA.dar0 = (AVR32_AES_ADDRESS | AVR32_AES_IDATA1R);
// Linked list ptrs: not used.
AVR32_DMACA.llp0 = 0x00000000;
// Channel 0 Ctrl register low
AVR32_DMACA.ctl0l =
(0 << AVR32_DMACA_CTL0L_INT_EN_OFFSET) | // Do not enable interrupts
(2 << AVR32_DMACA_CTL0L_DST_TR_WIDTH_OFFSET) | // Dst transfer width: 32 bits
(2 << AVR32_DMACA_CTL0L_SRC_TR_WIDTH_OFFSET) | // Src transfer width: 32 bits
(2 << AVR32_DMACA_CTL0L_DINC_OFFSET) | // Dst address increment: none
(0 << AVR32_DMACA_CTL0L_SINC_OFFSET) | // Src address increment: increment
(1 << AVR32_DMACA_CTL0L_DST_MSIZE_OFFSET) | // Dst burst transaction len: 4 data items
(1 << AVR32_DMACA_CTL0L_SRC_MSIZE_OFFSET) | // Src burst transaction len: 4 data items
(0 << AVR32_DMACA_CTL0L_S_GATH_EN_OFFSET) | // Source gather: disabled
(0 << AVR32_DMACA_CTL0L_D_SCAT_EN_OFFSET) | // Destination scatter: disabled
(1 << AVR32_DMACA_CTL0L_TT_FC_OFFSET) | // transfer type:M2P, flow controller: DMACA
(0 << AVR32_DMACA_CTL0L_DMS_OFFSET) | // Dest master: HSB master 1
(1 << AVR32_DMACA_CTL0L_SMS_OFFSET) | // Source master: HSB master 2
(0 << AVR32_DMACA_CTL0L_LLP_D_EN_OFFSET) | // Not used
(0 << AVR32_DMACA_CTL0L_LLP_S_EN_OFFSET) // Not used
;
// Channel 0 Ctrl register high
AVR32_DMACA.ctl0h =
(u16BufferSize << AVR32_DMACA_CTL0H_BLOCK_TS_OFFSET) | // Block transfer size
(0 << AVR32_DMACA_CTL0H_DONE_OFFSET) // Not done
;
// Channel 0 Config register low
AVR32_DMACA.cfg0l =
(0 << AVR32_DMACA_CFG0L_HS_SEL_DST_OFFSET) | // Destination handshaking: hw handshaking
(0 << AVR32_DMACA_CFG0L_HS_SEL_SRC_OFFSET) // Source handshaking: ignored because the src is memory.
; // All other bits set to 0.
// Channel 0 Config register high
AVR32_DMACA.cfg0h =
(AVR32_DMACA_CH_AES_TX << AVR32_DMACA_CFG0H_DEST_PER_OFFSET) | // Dest hw handshaking itf:
(0 << AVR32_DMACA_CFG0H_SRC_PER_OFFSET) // Source hw handshaking itf: ignored because the src is memory.
; // All other bits set to 0.
//*
//* Configure the DMA AES -> RAM channel.
//*
// ------------+--------+------+------------+--------+-------+----------------
// Transfer | Source | Dest | Flow | Width | Chunk | Buffer
// type | | | controller | (bits) | size | Size
// ------------+--------+------+------------+--------+-------+----------------
// | | | | | |
// Per-to-Mem | AES | RAM | DMACA | 32 | 4 | u16BufferSize
// | | | | | |
// ------------+--------+------+------------+--------+-------+----------------
// NOTE: We arbitrarily choose to use channel 1 for this datapath
// Src Address: the AES_ODATAXR registers.
AVR32_DMACA.sar1 = (AVR32_AES_ADDRESS | AVR32_AES_ODATA1R);
// Dst Address: the OutputData[] array.
AVR32_DMACA.dar1 = (unsigned long)pDstBuf;
// Linked list ptrs: not used.
AVR32_DMACA.llp1 = 0x00000000;
// Channel 1 Ctrl register low
AVR32_DMACA.ctl1l =
(0 << AVR32_DMACA_CTL1L_INT_EN_OFFSET) | // Do not enable interrupts
(2 << AVR32_DMACA_CTL1L_DST_TR_WIDTH_OFFSET) | // Dst transfer width: 32 bits
(2 << AVR32_DMACA_CTL1L_SRC_TR_WIDTH_OFFSET) | // Src transfer width: 32 bits
(0 << AVR32_DMACA_CTL1L_DINC_OFFSET) | // Dst address increment: increment
(2 << AVR32_DMACA_CTL1L_SINC_OFFSET) | // Src address increment: none
(1 << AVR32_DMACA_CTL1L_DST_MSIZE_OFFSET) | // Dst burst transaction len: 4 data items
(1 << AVR32_DMACA_CTL1L_SRC_MSIZE_OFFSET) | // Src burst transaction len: 4 data items
(0 << AVR32_DMACA_CTL1L_S_GATH_EN_OFFSET) | // Source gather: disabled
(0 << AVR32_DMACA_CTL1L_D_SCAT_EN_OFFSET) | // Destination scatter: disabled
(2 << AVR32_DMACA_CTL1L_TT_FC_OFFSET) | // transfer type:P2M, flow controller: DMACA
(1 << AVR32_DMACA_CTL1L_DMS_OFFSET) | // Dest master: HSB master 2
(0 << AVR32_DMACA_CTL1L_SMS_OFFSET) | // Source master: HSB master 1
(0 << AVR32_DMACA_CTL1L_LLP_D_EN_OFFSET) | // Not used
(0 << AVR32_DMACA_CTL1L_LLP_S_EN_OFFSET) // Not used
;
// Channel 1 Ctrl register high
AVR32_DMACA.ctl1h =
(u16BufferSize << AVR32_DMACA_CTL1H_BLOCK_TS_OFFSET) | // Block transfer size
(0 << AVR32_DMACA_CTL1H_DONE_OFFSET) // Not done
;
// Channel 1 Config register low
AVR32_DMACA.cfg1l =
(0 << AVR32_DMACA_CFG1L_HS_SEL_DST_OFFSET) | // Destination handshaking: hw handshaking
(0 << AVR32_DMACA_CFG1L_HS_SEL_SRC_OFFSET) // Source handshaking: ignored because the src is memory.
; // All other bits set to 0.
// Channel 1 Config register high
AVR32_DMACA.cfg1h =
(0 << AVR32_DMACA_CFG1H_DEST_PER_OFFSET) | // Dest hw handshaking itf: ignored because the dst is memory.
(AVR32_DMACA_CH_AES_RX << AVR32_DMACA_CFG1H_SRC_PER_OFFSET) // Source hw handshaking itf:
; // All other bits set to 0.
//*
//* Set the AES cryptographic key and init vector.
//*
// Set the cryptographic key.
aes_set_key(&AVR32_AES, CipherKey);
// Set the initialization vector.
aes_set_initvector(&AVR32_AES, InitVector);
//*
//* Start the process
//*
ccountt0 = Get_system_register(AVR32_COUNT);
// Enable Channel 0 & 1 : start the process.
AVR32_DMACA.chenreg = ((3<<AVR32_DMACA_CHENREG_CH_EN_OFFSET) | (3<<AVR32_DMACA_CHENREG_CH_EN_WE_OFFSET));
// Wait for the end of the AES->RAM transfer (channel 1).
while(AVR32_DMACA.chenreg & (2<<AVR32_DMACA_CHENREG_CH_EN_OFFSET));
ccountt1 = Get_system_register(AVR32_COUNT);
// Check the results of the encryption.
for(i=0; i<DMACA_AES_EVAL_REFBUF_SIZE; i++)
{
if(OutputData[i] != RefOutputData[i])
{
TestResult = false;
break;
}
}
if(false == TestResult)
print(DMACA_AES_EVAL_USART, "KO!!!\r\n");
else
{
print(DMACA_AES_EVAL_USART, "OK!!! Nb of cycles: ");
print_ulong(DMACA_AES_EVAL_USART, ccountt1 - ccountt0);
}
}
/*! \brief The main function.
*
*/
int main(void)
{
aes_config_t AesConf; // AES config structure
int i;
static const gpio_map_t USART_GPIO_MAP = // USART GPIO map
{
{DMACA_AES_EVAL_USART_RX_PIN, DMACA_AES_EVAL_USART_RX_FUNCTION},
{DMACA_AES_EVAL_USART_TX_PIN, DMACA_AES_EVAL_USART_TX_FUNCTION}
};
static const usart_options_t USART_OPTIONS = // USART options.
{
.baudrate = DMACA_AES_EVAL_USART_BAUDRATE,
.charlength = 8,
.paritytype = USART_NO_PARITY,
.stopbits = USART_1_STOPBIT,
.channelmode = USART_NORMAL_CHMODE
};
#if BOARD == EVK1104
if( PM_FREQ_STATUS_FAIL==pm_configure_clocks(&pm_freq_param) )
while(1);
#endif
init_hmatrix();
// Assign GPIO to USART.
gpio_enable_module(USART_GPIO_MAP,
sizeof(USART_GPIO_MAP) / sizeof(USART_GPIO_MAP[0]));
// Initialize USART in RS232 mode.
usart_init_rs232(DMACA_AES_EVAL_USART, &USART_OPTIONS, DMACA_AES_EVAL_CPU_FREQ);
print(DMACA_AES_EVAL_USART, "\x1B[2J\x1B[H.: Using the AES with the DMACA at ");
print_ulong(DMACA_AES_EVAL_USART, DMACA_AES_EVAL_CPU_FREQ);
print(DMACA_AES_EVAL_USART, "Hz :.\r\n\r\n");
//****************************************************************************
// CIPHER IN DMA MODE: RAM -> AES -> RAM
// - 256bit cryptographic key
// - CBC cipher mode
// - No counter measures
//****************************************************************************
// Init the input array.
for(i=0; i<DMACA_AES_EVAL_BUF_SIZE; i+=DMACA_AES_EVAL_REFBUF_SIZE)
{
memcpy(InputData+i, RefInputData, DMACA_AES_EVAL_REFBUF_SIZE*sizeof(unsigned int));
}
//====================
// Configure the AES.
//====================
AesConf.ProcessingMode = AES_PMODE_CIPHER; // Cipher
AesConf.ProcessingDelay = 0; // No delay: best performance
AesConf.StartMode = AES_START_MODE_DMA; // DMA mode
AesConf.KeySize = AES_KEY_SIZE_256; // 256bit cryptographic key
AesConf.OpMode = AES_CBC_MODE; // CBC cipher mode
AesConf.LodMode = 0; // LODMODE == 0 : the end of the
// encryption is notified by the DMACA transfer complete interrupt. The output
// is available in the OutputData[] buffer.
AesConf.CFBSize = 0; // Don't-care because we're using the CBC mode.
AesConf.CounterMeasureMask = 0; // Disable all counter measures.
aes_configure(&AVR32_AES, &AesConf);
//****************************************************************************
// - input of 16 32bit words in CPUSRAM
// - output of 16 32bit words in CPUSRAM
//****************************************************************************
print(DMACA_AES_EVAL_USART, "\r\n---------------------------------------------------\r\n");
print(DMACA_AES_EVAL_USART, "------ Cipher in DMA Mode: CPUSRAM -> AES -> CPUSRAM ------\r\n");
print(DMACA_AES_EVAL_USART, " - 256bit cryptographic key\r\n");
print(DMACA_AES_EVAL_USART, " - CBC cipher mode\r\n");
print(DMACA_AES_EVAL_USART, " - No counter measures\r\n");
print(DMACA_AES_EVAL_USART, " - input of 16 32bit words in CPUSRAM\r\n");
print(DMACA_AES_EVAL_USART, " - output of 16 32bit words in CPUSRAM\r\n");
print(DMACA_AES_EVAL_USART, "---------------------------------------------------\r\n");
test_ram_aes_ram(16, (unsigned int *)InputData, (unsigned int *)OutputData);
gpio_clr_gpio_pin(DMACA_AES_EVAL_LED1);
//****************************************************************************
// - input of 256 32bit words in CPUSRAM
// - output of 256 32bit words in CPUSRAM
//****************************************************************************
print(DMACA_AES_EVAL_USART, "\r\n---------------------------------------------------\r\n");
print(DMACA_AES_EVAL_USART, "------ Cipher in DMA Mode: CPUSRAM -> AES -> CPUSRAM ------\r\n");
print(DMACA_AES_EVAL_USART, " - 256bit cryptographic key\r\n");
print(DMACA_AES_EVAL_USART, " - CBC cipher mode\r\n");
print(DMACA_AES_EVAL_USART, " - No counter measures\r\n");
print(DMACA_AES_EVAL_USART, " - input of 256 32bit words in CPUSRAM\r\n");
print(DMACA_AES_EVAL_USART, " - output of 256 32bit words in CPUSRAM\r\n");
print(DMACA_AES_EVAL_USART, "---------------------------------------------------\r\n");
test_ram_aes_ram(256, (unsigned int *)InputData, (unsigned int *)OutputData);
gpio_clr_gpio_pin(DMACA_AES_EVAL_LED2);
//****************************************************************************
// - input of 256 32bit words in HSBSRAM0
// - output of 256 32bit words in HSBSRAM1
//****************************************************************************
print(DMACA_AES_EVAL_USART, "\r\n---------------------------------------------------\r\n");
print(DMACA_AES_EVAL_USART, "------ Cipher in DMA Mode: HSBSRAM0 -> AES -> HSBSRAM1 ------\r\n");
print(DMACA_AES_EVAL_USART, " - 256bit cryptographic key\r\n");
print(DMACA_AES_EVAL_USART, " - CBC cipher mode\r\n");
print(DMACA_AES_EVAL_USART, " - No counter measures\r\n");
print(DMACA_AES_EVAL_USART, " - Input of 256 32bit words in HSBSRAM0\r\n");
print(DMACA_AES_EVAL_USART, " - Output of 256 32bit words in HSBSRAM1\r\n");
print(DMACA_AES_EVAL_USART, "---------------------------------------------------\r\n");
// Set the Src and Dst array addresses to respectively HSBSRAM0 & HSBRAM1.
pSrcData_HsbSram = (unsigned int *)AVR32_INTRAM0_ADDRESS;
pDstData_HsbSram = (unsigned int *)AVR32_INTRAM1_ADDRESS;
// Init the input array.
for(i=0; i<DMACA_AES_EVAL_BUF_SIZE; i+=DMACA_AES_EVAL_REFBUF_SIZE)
{
memcpy(pSrcData_HsbSram+i, RefInputData, DMACA_AES_EVAL_REFBUF_SIZE*sizeof(unsigned int));
}
test_ram_aes_ram(256, pSrcData_HsbSram, (unsigned int *)pDstData_HsbSram);
gpio_clr_gpio_pin(DMACA_AES_EVAL_LED3);
print(DMACA_AES_EVAL_USART, "\r\nDone!");
// End of tests: go to sleep.
SLEEP(AVR32_PM_SMODE_STATIC);
while (true);
}
static int handle_clustergroup(FILE *stream, const struct printf_info *info,
const void *const *args)
{
return print_ulong(stream, info, args,
OCFS2_RAW_SB(query_fs->fs_super)->s_first_cluster_group);
}
static int handle_sysdir(FILE *stream, const struct printf_info *info,
const void *const *args)
{
return print_ulong(stream, info, args,
OCFS2_RAW_SB(query_fs->fs_super)->s_system_dir_blkno);
}
static int handle_numslots(FILE *stream, const struct printf_info *info,
const void *const *args)
{
return print_ulong(stream, info, args,
OCFS2_RAW_SB(query_fs->fs_super)->s_max_slots);
}
static int handle_clustersize(FILE *stream, const struct printf_info *info,
const void *const *args)
{
return print_ulong(stream, info, args, query_fs->fs_clustersize);
}
void
print_generic_offset_makervalue(FILE *inptr,unsigned short byteorder,
struct ifd_entry *entry_ptr,unsigned long fileoffset_base,char *parent_name,
char *prefix,int indent,int make,int model,int at_offset)
{
unsigned long value_offset;
unsigned long dumplength;
int chpr = 0;
if((value_type_size(entry_ptr->value_type) * entry_ptr->count) > 4)
{
value_offset = fileoffset_base + entry_ptr->value;
if(PRINT_VALUE)
{
if(at_offset)
{
print_tag_address(ENTRY,value_offset,indent,prefix);
if(entry_ptr->value_type == UNDEFINED)
print_makertagid(entry_ptr,MAKERTAGWIDTH," : ",make,model);
else
print_makertagid(entry_ptr,MAKERTAGWIDTH," = ",make,model);
}
else
{
if((PRINT_OFFSET) && (entry_ptr->value_type != UNDEFINED))
chpr += printf(" = ");
}
switch(entry_ptr->value_type)
{
case UNDEFINED:
/* Could make a pseudo-tag for 'count' in LIST */
/* mode... */
if((PRINT_SECTION) && at_offset && (PRINT_VALUE_AT_OFFSET))
chpr += printf("length %-9lu # UNDEFINED",entry_ptr->count);
else
{
if(!(PRINT_OFFSET))
chpr += printf("@%lu",value_offset);
chpr += printf(":%-9lu # UNDEFINED",entry_ptr->count);
}
if(Max_undefined == 0)
{
if((PRINT_SECTION))
printred(" (not dumped, use -U)");
}
else
{
/* Even in LIST and REPORT modes */
if((Max_undefined == DUMPALL)
|| (Max_undefined > entry_ptr->count))
dumplength = entry_ptr->count;
else
dumplength = Max_undefined;
chpr = newline(1);
hexdump(inptr,entry_ptr->value + fileoffset_base,
entry_ptr->count,dumplength,12,
indent,SUBINDENT);
}
/* make certain we're at the end */
fseek(inptr,entry_ptr->value + fileoffset_base + entry_ptr->count,SEEK_SET);
break;
case ASCII:
print_ascii(inptr,entry_ptr->count,value_offset);
break;
case BYTE:
print_ubytes(inptr,entry_ptr->count,value_offset);
break;
case SBYTE:
print_sbytes(inptr,entry_ptr->count,value_offset);
break;
case SHORT:
print_ushort(inptr,entry_ptr->count,byteorder,value_offset);
break;
case SSHORT:
print_sshort(inptr,entry_ptr->count,byteorder,value_offset);
break;
case LONG:
print_ulong(inptr,entry_ptr->count,byteorder,value_offset);
break;
case SLONG:
print_slong(inptr,entry_ptr->count,byteorder,value_offset);
break;
case RATIONAL:
print_urational(inptr,entry_ptr->count,byteorder,value_offset);
break;
case SRATIONAL:
print_srational(inptr,entry_ptr->count,byteorder,value_offset);
break;
case FLOAT:
print_float(inptr,entry_ptr->count,byteorder,value_offset);
break;
case DOUBLE:
print_double(inptr,entry_ptr->count,byteorder,value_offset);
break;
default:
chpr = printf(" INVALID TYPE %#x",entry_ptr->value_type);
break;
}
}
}
if(ferror(inptr) || feof(inptr))
clearerr(inptr);
setcharsprinted(chpr);
}
