void gic_init(vaddr_t gicc_base, vaddr_t gicd_base)
{
size_t n;
gic.gicc_base = gicc_base;
gic.gicd_base = gicd_base;
gic.max_it = probe_max_it();
for (n = 0; n <= gic.max_it / NUM_INTS_PER_REG; n++) {
/* Disable interrupts */
write32(0xffffffff, gic.gicd_base + GICD_ICENABLER(n));
/* Make interrupts non-pending */
write32(0xffffffff, gic.gicd_base + GICD_ICPENDR(n));
/* Mark interrupts non-secure */
if (n == 0) {
/* per-CPU inerrupts config:
* ID0-ID7(SGI) for Non-secure interrupts
* ID8-ID15(SGI) for Secure interrupts.
* All PPI config as Non-secure interrupts.
*/
write32(0xffff00ff, gic.gicd_base + GICD_IGROUPR(n));
} else {
write32(0xffffffff, gic.gicd_base + GICD_IGROUPR(n));
}
}
/* Enable GIC */
write32(GICC_CTLR_ENABLEGRP0 | GICC_CTLR_ENABLEGRP1 | GICC_CTLR_FIQEN,
gic.gicc_base + GICC_CTLR);
write32(GICD_CTLR_ENABLEGRP0 | GICD_CTLR_ENABLEGRP1,
gic.gicd_base + GICD_CTLR);
}
void gic_init(vaddr_t gicc_base, vaddr_t gicd_base)
{
size_t n;
gic.gicc_base = gicc_base;
gic.gicd_base = gicd_base;
gic.max_it = probe_max_it();
for (n = 0; n <= gic.max_it / 32; n++) {
/* Disable interrupts */
write32(0xffffffff, gic.gicd_base + GICD_ICENABLER(n));
/* Make interrupts non-pending */
write32(0xffffffff, gic.gicd_base + GICD_ICPENDR(n));
/* Mark interrupts non-secure */
write32(0xffffffff, gic.gicd_base + GICD_IGROUPR(n));
}
/* Enable GIC */
write32(GICC_CTLR_ENABLEGRP0 | GICC_CTLR_ENABLEGRP1 | GICC_CTLR_FIQEN,
gic.gicc_base + GICC_CTLR);
write32(GICD_CTLR_ENABLEGRP0 | GICD_CTLR_ENABLEGRP1,
gic.gicd_base + GICD_CTLR);
}
void gic_init_base_addr(struct gic_data *gd, vaddr_t gicc_base,
vaddr_t gicd_base)
{
gd->gicc_base = gicc_base;
gd->gicd_base = gicd_base;
gd->max_it = probe_max_it(gicc_base, gicd_base);
gd->chip.ops = &gic_ops;
}
void gic_init_base_addr(vaddr_t gicc_base, vaddr_t gicd_base)
{
gic.gicc_base = gicc_base;
gic.gicd_base = gicd_base;
gic.max_it = probe_max_it();
}
