void psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask) { if ((dev_priv->pipestat[pipe] & mask) != mask) { u32 reg = psb_pipestat(pipe); u32 writeVal = PSB_RVDC32(reg); dev_priv->pipestat[pipe] |= mask; /* Enable the interrupt, clear any pending status */ writeVal |= (mask | (mask >> 16)); PSB_WVDC32(writeVal, reg); (void) PSB_RVDC32(reg); }
void psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask) { if ((dev_priv->pipestat[pipe] & mask) != mask) { u32 reg = psb_pipestat(pipe); dev_priv->pipestat[pipe] |= mask; /* Enable the interrupt, clear any pending status */ if (ospm_power_using_hw_begin (OSPM_DISPLAY_ISLAND, OSPM_UHB_ONLY_IF_ON)) { u32 writeVal = PSB_RVDC32(reg); writeVal |= (mask | (mask >> 16)); PSB_WVDC32(writeVal, reg); (void)PSB_RVDC32(reg); ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND); } }