int do_psc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int psc_module;
int res;
if (argc != 3)
goto psc_cmd_usage;
psc_module = simple_strtoul(argv[1], NULL, 10);
if (strcmp(argv[2], "en") == 0) {
res = psc_enable_module(psc_module);
printf("psc_enable_module(%d) - %s\n", psc_module,
(res) ? "ERROR" : "OK");
return 0;
}
if (strcmp(argv[2], "di") == 0) {
res = psc_disable_module(psc_module);
printf("psc_disable_module(%d) - %s\n", psc_module,
(res) ? "ERROR" : "OK");
return 0;
}
if (strcmp(argv[2], "domain") == 0) {
res = psc_disable_domain(psc_module);
printf("psc_disable_domain(%d) - %s\n", psc_module,
(res) ? "ERROR" : "OK");
return 0;
}
psc_cmd_usage:
return cmd_usage(cmdtp);
}
int board_init(void)
{
#if CONFIG_IS_ENABLED(DM_USB)
int rc = psc_enable_module(KS2_LPSC_USB);
if (rc)
puts("Cannot enable USB0 module");
#ifdef KS2_LPSC_USB_1
rc = psc_enable_module(KS2_LPSC_USB_1);
if (rc)
puts("Cannot enable USB1 module");
#endif
#endif
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
return 0;
}
int board_mmc_init(bd_t *bis)
{
if (psc_enable_module(KS2_LPSC_MMC)) {
printf("%s module enabled failed\n", __func__);
return -1;
}
omap_mmc_init(0, 0, 0, -1, -1);
omap_mmc_init(1, 0, 0, -1, -1);
return 0;
}
int board_early_init_f(void)
{
init_plls();
k2g_mux_config();
/* deassert FLASH_HOLD */
clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
BIT(9));
setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
BIT(9));
if (psc_enable_module(KS2_LPSC_GPMC))
printf("%s can't enable gpmc\n", __func__);
return 0;
}
void osr_init(void)
{
u32 i;
u32 j;
u32 val;
u32 base = KS2_OSR_CFG_BASE;
u32 ecc_ctrl[KS2_OSR_NUM_RAM_BANKS];
/* Enable the OSR clock domain */
psc_enable_module(KS2_LPSC_OSR);
/* Disable OSR ECC check for all the ram banks */
for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++) {
val = i | KS2_OSR_ECC_VEC_TRIG_RD |
(KS2_OSR_ECC_CTRL << KS2_OSR_ECC_VEC_RD_ADDR_SH);
writel(val , base + KS2_OSR_ECC_VEC);
/**
* wait till read is done.
* Print should be added after earlyprintk support is added.
*/
for (j = 0; j < 10000; j++) {
val = readl(base + KS2_OSR_ECC_VEC);
if (val & KS2_OSR_ECC_VEC_RD_DONE)
break;
}
ecc_ctrl[i] = readl(base + KS2_OSR_ECC_CTRL) ^
KS2_OSR_ECC_CTRL_CHK;
writel(ecc_ctrl[i], KS2_MSMC_DATA_BASE + i * 4);
writel(ecc_ctrl[i], base + KS2_OSR_ECC_CTRL);
}
/* Reset OSR memory to all zeros */
for (i = 0; i < KS2_OSR_SIZE; i += 4)
writel(0, KS2_OSR_DATA_BASE + i);
/* Enable OSR ECC check for all the ram banks */
for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++)
writel(ecc_ctrl[i] |
KS2_OSR_ECC_CTRL_CHK, base + KS2_OSR_ECC_CTRL);
}
static int ks2_eth_probe(struct udevice *dev)
{
struct ks2_eth_priv *priv = dev_get_priv(dev);
struct mii_dev *mdio_bus;
int ret;
priv->dev = dev;
/* These clock enables has to be moved to common location */
if (cpu_is_k2g())
writel(KS2_ETHERNET_RGMII, KS2_ETHERNET_CFG);
/* By default, select PA PLL clock as PA clock source */
#ifndef CONFIG_SOC_K2G
if (psc_enable_module(KS2_LPSC_PA))
return -EACCES;
#endif
if (psc_enable_module(KS2_LPSC_CPGMAC))
return -EACCES;
if (psc_enable_module(KS2_LPSC_CRYPTO))
return -EACCES;
if (cpu_is_k2e() || cpu_is_k2l())
pll_pa_clk_sel();
priv->net_rx_buffs.buff_ptr = rx_buffs;
priv->net_rx_buffs.num_buffs = RX_BUFF_NUMS;
priv->net_rx_buffs.buff_len = RX_BUFF_LEN;
if (priv->slave_port == 1) {
/*
* Register MDIO bus for slave 0 only, other slave have
* to re-use the same
*/
mdio_bus = mdio_alloc();
if (!mdio_bus) {
error("MDIO alloc failed\n");
return -ENOMEM;
}
priv->mdio_bus = mdio_bus;
mdio_bus->read = keystone2_mdio_read;
mdio_bus->write = keystone2_mdio_write;
mdio_bus->reset = keystone2_mdio_reset;
mdio_bus->priv = priv->mdio_base;
sprintf(mdio_bus->name, "ethernet-mdio");
ret = mdio_register(mdio_bus);
if (ret) {
error("MDIO bus register failed\n");
return ret;
}
} else {
/* Get the MDIO bus from slave 0 device */
struct ks2_eth_priv *parent_priv;
parent_priv = dev_get_priv(dev->parent);
priv->mdio_bus = parent_priv->mdio_bus;
}
#ifndef CONFIG_SOC_K2G
keystone2_net_serdes_setup();
#endif
priv->netcp_pktdma = &netcp_pktdma;
if (priv->has_mdio) {
priv->phydev = phy_connect(priv->mdio_bus, priv->phy_addr,
dev, priv->phy_if);
phy_config(priv->phydev);
}
return 0;
}
int xhci_hcd_init(int index,
struct xhci_hccr **ret_hccr, struct xhci_hcor **ret_hcor)
{
u32 val;
int ret;
struct xhci_hccr *hcd;
struct xhci_hcor *hcor;
struct kdwc3_irq_regs *usbss;
struct keystone_xhci_phy *phy;
usbss = (struct kdwc3_irq_regs *)CONFIG_USB_SS_BASE;
phy = (struct keystone_xhci_phy *)CONFIG_DEV_USB_PHY_BASE;
/* Enable the PHY REFCLK clock gate with phy_ref_ssp_en = 1 */
val = readl(&(phy->phy_clock));
val |= USB3_PHY_REF_SSP_EN;
writel(val, &phy->phy_clock);
mdelay(100);
/* Release USB from reset */
ret = psc_enable_module(KS2_LPSC_USB);
if (ret) {
puts("Cannot enable USB module");
return -1;
}
mdelay(100);
/* Initialize usb phy */
keystone_xhci_phy_set(phy);
/* soft reset usbss */
writel(1, &usbss->sysconfig);
while (readl(&usbss->sysconfig) & 1)
;
val = readl(&usbss->revision);
debug("usbss revision %x\n", val);
/* Initialize usb core */
hcd = (struct xhci_hccr *)CONFIG_USB_HOST_XHCI_BASE;
keystone.dwc3_reg = (struct dwc3 *)(CONFIG_USB_HOST_XHCI_BASE +
DWC3_REG_OFFSET);
keystone_xhci_core_init(keystone.dwc3_reg);
/* set register addresses */
hcor = (struct xhci_hcor *)((uint32_t)hcd +
HC_LENGTH(readl(&hcd->cr_capbase)));
debug("Keystone2-xhci: init hccr %08x and hcor %08x hc_length %d\n",
(u32)hcd, (u32)hcor,
(u32)HC_LENGTH(xhci_readl(&hcd->cr_capbase)));
keystone.usbss = usbss;
keystone.phy = phy;
keystone.hcd = hcd;
keystone.hcor = hcor;
*ret_hccr = hcd;
*ret_hcor = hcor;
return 0;
}
