static int am33xx_pm_suspend(unsigned int state)
{
int i, ret = 0;
struct wkup_m3_wakeup_src wakeup_src;
omap_set_pwrdm_state(gfx_pwrdm, PWRDM_POWER_OFF);
am33xx_pm->ops->pre_suspend(state);
ret = cpu_suspend((long unsigned int) &susp_params,
am33xx_do_sram_idle);
am33xx_pm->ops->post_suspend(state);
if (ret) {
pr_err("PM: Kernel suspend failure\n");
} else {
i = wkup_m3_pm_status();
switch (i) {
case 0:
pr_info("PM: Successfully put all powerdomains to target state\n");
/*
* The PRCM registers on AM335x do not contain
* previous state information like those present on
* OMAP4 so we must manually indicate transition so
* state counters are properly incremented
*/
pwrdm_post_transition(mpu_pwrdm);
pwrdm_post_transition(per_pwrdm);
break;
case 1:
pr_err("PM: Could not transition all powerdomains to target state\n");
ret = -1;
break;
default:
pr_err("PM: CM3 returned unknown result = %d\n", i);
ret = -1;
}
/* print the wakeup reason */
wakeup_src = wkup_m3_wake_src();
pr_info("PM: Wakeup source %s\n", wakeup_src.src);
}
return ret;
}
/**
* omap4_enter_lowpower: OMAP4 MPUSS Low Power Entry Function
* The purpose of this function is to manage low power programming
* of OMAP4 MPUSS subsystem
* @cpu : CPU ID
* @power_state: Low power state.
*
* MPUSS states for the context save:
* save_state =
* 0 - Nothing lost and no need to save: MPUSS INACTIVE
* 1 - CPUx L1 and logic lost: MPUSS CSWR
* 2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
* 3 - CPUx L1 and logic lost + GIC + L2 lost: DEVICE OFF
*/
int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
{
unsigned int save_state = 0;
unsigned int wakeup_cpu;
if (omap_rev() == OMAP4430_REV_ES1_0)
return -ENXIO;
switch (power_state) {
case PWRDM_POWER_ON:
case PWRDM_POWER_INACTIVE:
save_state = 0;
break;
case PWRDM_POWER_OFF:
save_state = 1;
break;
case PWRDM_POWER_RET:
default:
/*
* CPUx CSWR is invalid hardware state. Also CPUx OSWR
* doesn't make much scense, since logic is lost and $L1
* needs to be cleaned because of coherency. This makes
* CPUx OSWR equivalent to CPUX OFF and hence not supported
*/
WARN_ON(1);
return -ENXIO;
}
pwrdm_pre_transition(NULL);
/*
* Check MPUSS next state and save interrupt controller if needed.
* In MPUSS OSWR or device OFF, interrupt controller contest is lost.
*/
mpuss_clear_prev_logic_pwrst();
if ((pwrdm_read_next_pwrst(mpuss_pd) == PWRDM_POWER_RET) &&
(pwrdm_read_logic_retst(mpuss_pd) == PWRDM_POWER_OFF))
save_state = 2;
cpu_clear_prev_logic_pwrst(cpu);
set_cpu_next_pwrst(cpu, power_state);
set_cpu_wakeup_addr(cpu, virt_to_phys(omap4_cpu_resume));
scu_pwrst_prepare(cpu, power_state);
l2x0_pwrst_prepare(cpu, save_state);
/*
* Call low level function with targeted low power state.
*/
cpu_suspend(save_state, omap4_finish_suspend);
/*
* Restore the CPUx power state to ON otherwise CPUx
* power domain can transitions to programmed low power
* state while doing WFI outside the low powe code. On
* secure devices, CPUx does WFI which can result in
* domain transition
*/
wakeup_cpu = smp_processor_id();
set_cpu_next_pwrst(wakeup_cpu, PWRDM_POWER_ON);
pwrdm_post_transition(NULL);
return 0;
}
/**
* omap4_enter_idle - Programs OMAP4 to enter the specified state
* @dev: cpuidle device
* @state: The target state to be programmed
*
* Called from the CPUidle framework to program the device to the
* specified low power state selected by the governor.
* Returns the amount of time spent in the low power state.
*/
static int omap4_enter_idle(struct cpuidle_device *dev,
struct cpuidle_state *state)
{
struct omap4_processor_cx *cx = cpuidle_get_statedata(state);
struct timespec ts_preidle, ts_postidle, ts_idle;
u32 cpu1_state;
int cpu_id = smp_processor_id();
/* Used to keep track of the total time in idle */
getnstimeofday(&ts_preidle);
local_irq_disable();
local_fiq_disable();
/*
* Do only WFI for non-boot CPU(aux cores)
*/
if (dev->cpu) {
wmb();
DO_WFI();
goto return_sleep_time;
}
/*
* Do only a WFI as long as CPU1 is online
*/
if (num_online_cpus() > 1) {
wmb();
DO_WFI();
goto return_sleep_time;
}
/*
* Hold on till CPU1 hits OFF
*/
cpu1_state = pwrdm_read_pwrst(cpu1_pd);
if (cpu1_state != PWRDM_POWER_OFF) {
wmb();
DO_WFI();
goto return_sleep_time;
}
if (cx->type > OMAP4_STATE_C1)
clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id);
#ifdef CONFIG_PM_DEBUG
pwrdm_pre_transition();
#endif
pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
omap4_set_pwrdm_state(mpu_pd, cx->mpu_state);
pwrdm_set_logic_retst(core_pd, cx->core_logic_state);
omap4_set_pwrdm_state(core_pd, cx->core_state);
omap4_enter_sleep(dev->cpu, cx->cpu0_state);
/* restore the MPU and CORE states to ON */
omap4_set_pwrdm_state(mpu_pd, PWRDM_POWER_ON);
omap4_set_pwrdm_state(core_pd, PWRDM_POWER_ON);
#ifdef CONFIG_PM_DEBUG
pwrdm_post_transition();
#endif
if (cx->type > OMAP4_STATE_C1)
clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id);
return_sleep_time:
getnstimeofday(&ts_postidle);
ts_idle = timespec_sub(ts_postidle, ts_preidle);
local_irq_enable();
local_fiq_enable();
return ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * USEC_PER_SEC;;
}
