static void __init csb226_map_io(void)
{
pxa_map_io();
iotable_init(csb226_io_desc, ARRAY_SIZE(csb226_io_desc));
/* This enables the BTUART */
CKEN |= CKEN7_BTUART;
pxa_gpio_mode(GPIO42_BTRXD_MD);
pxa_gpio_mode(GPIO43_BTTXD_MD);
pxa_gpio_mode(GPIO44_BTCTS_MD);
pxa_gpio_mode(GPIO45_BTRTS_MD);
#if defined(CONFIG_CIRRUS)
/* This is for the CS8900 chip select */
pxa_gpio_mode(GPIO78_nCS_2_MD);
#endif
/* setup sleep mode values */
PWER = 0x00000002;
PFER = 0x00000000;
PRER = 0x00000002;
PGSR0 = 0x00008000;
PGSR1 = 0x003F0202;
PGSR2 = 0x0001C000;
PCFR |= PCFR_OPDE;
}
static void __init cmx2xx_map_io(void)
{
pxa_map_io();
iotable_init(cmx2xx_io_desc, ARRAY_SIZE(cmx2xx_io_desc));
it8152_base_address = CMX2XX_IT8152_VIRT;
}
static void __init ez_pxa270_map_io(void)
{
pxa_map_io();
iotable_init(ez_pxa270_io_desc, ARRAY_SIZE(ez_pxa270_io_desc));
// FF-UART
pxa_gpio_mode(GPIO34_FFRXD_MD);
pxa_gpio_mode(GPIO39_FFTXD_MD);
// ST-UART
pxa_gpio_mode(GPIO46_STRXD_MD);
pxa_gpio_mode(GPIO47_STTXD_MD);
// BT-UART
pxa_gpio_mode(GPIO42_BTRXD_MD);
pxa_gpio_mode(GPIO43_BTTXD_MD);
// AC97
pxa_gpio_mode(GPIO89_SYSCLK_AC97_MD);
// FB
pxafb_set_gpio();
// pxa_gpio_mode(19|GPIO_OUT);
// pxa_gpio_set_value(19, 1);
set_pxa_fb_info(&falinux_ezlcd);
}
static int __init gumstix_init(void)
{
printk("gumstix_init: Initialising board...\n");
pxa_map_io();
pxa_generic_init();
/* Set up nPWE */
pxa_gpio_mode(GPIO49_nPWE_MD);
/* Set up the chip selects */
pxa_gpio_mode(GPIO15_nCS_1_MD);
(void) platform_add_devices(devices, ARRAY_SIZE(devices));
pxa_gpio_func(36, GPIO_MODE, GPIO_IN);
/* Set rising edge detect for GPIO 36 */
GFER(36) &= ~GPIO_BIT(36);
GRER(36) |= (GPIO_BIT(36));
/* We assume that the bootloader has set up the rest for us */
// set_irq_type(IBOX_ETH_IRQ, IRQT_RISING);
return 0;
}
static void __init lubbock_map_io(void)
{
pxa_map_io();
iotable_init(lubbock_io_desc, ARRAY_SIZE(lubbock_io_desc));
PCFR |= PCFR_OPDE;
}
static void __init mainstone_map_io(void)
{
pxa_map_io();
iotable_init(mainstone_io_desc, ARRAY_SIZE(mainstone_io_desc));
/* for use I SRAM as framebuffer. */
PSLR |= 0xF04;
PCFR = 0x66;
}
static void __init trizeps4_map_io(void)
{
pxa_map_io();
iotable_init(trizeps4_io_desc, ARRAY_SIZE(trizeps4_io_desc));
/* for DiskOnChip */
pxa_gpio_mode(GPIO15_nCS_1_MD);
/* for off-module PIC on ConXS board */
pxa_gpio_mode(GPIO_PIC | GPIO_IN);
/* UCB1400 irq */
pxa_gpio_mode(GPIO_UCB1400 | GPIO_IN);
/* for DM9000 LAN */
pxa_gpio_mode(GPIO78_nCS_2_MD);
pxa_gpio_mode(GPIO_DM9000 | GPIO_IN);
/* for PCMCIA device */
pxa_gpio_mode(GPIO_PCD | GPIO_IN);
pxa_gpio_mode(GPIO_PRDY | GPIO_IN);
/* for I2C adapter */
pxa_gpio_mode(GPIO117_I2CSCL_MD);
pxa_gpio_mode(GPIO118_I2CSDA_MD);
/* MMC_DET s.o. */
pxa_gpio_mode(GPIO_MMC_DET | GPIO_IN);
/* whats that for ??? */
pxa_gpio_mode(GPIO79_nCS_3_MD);
#ifdef CONFIG_LEDS
pxa_gpio_mode( GPIO_SYS_BUSY_LED | GPIO_OUT); /* LED1 */
pxa_gpio_mode( GPIO_HEARTBEAT_LED | GPIO_OUT); /* LED2 */
#endif
#ifdef CONFIG_MACH_TRIZEPS4_CONXS
#ifdef CONFIG_IDE_PXA_CF
/* if boot direct from compact flash dont disable power */
trizeps_conxs_bcr = 0x0009;
#else
/* this is the reset value */
trizeps_conxs_bcr = 0x00A0;
#endif
ConXS_BCR = trizeps_conxs_bcr;
#endif
PWER = 0x00000002;
PFER = 0x00000000;
PRER = 0x00000002;
PGSR0 = 0x0158C000;
PGSR1 = 0x00FF0080;
PGSR2 = 0x0001C004;
/* Stop 3.6MHz and drive HIGH to PCMCIA and CS */
PCFR |= PCFR_OPDE;
}
static void __init pcm027_map_io(void)
{
pxa_map_io();
/* initialize sleep mode regs (wake-up sources, etc) */
PGSR0 = 0x01308000;
PGSR1 = 0x00CF0002;
PGSR2 = 0x0E294000;
PGSR3 = 0x0000C000;
PWER = 0x40000000 | PWER_GPIO0 | PWER_GPIO1;
PRER = 0x00000000;
PFER = 0x00000003;
}
static void __init hx4700_map_io(void)
{
pxa_map_io();
#if 0
iotable_init( hx4700_io_desc, ARRAY_SIZE(hx4700_io_desc) );
#endif
pxa_set_stuart_info(&hx4700_pxa_irda_funcs);
#ifdef EARLY_SIR_CONSOLE
hx4700_irda_configure(NULL, 1);
hx4700_irda_set_txrx(NULL, PXA_SERIAL_TX);
#endif
pxa_set_btuart_info(&hx4700_pxa_bt_funcs);
}
static void __init falinux_pxa255_map_io(void)
{
pxa_map_io();
iotable_init(falinux_pxa255_io_desc, ARRAY_SIZE(falinux_pxa255_io_desc));
// FF-UART
pxa_gpio_mode(GPIO34_FFRXD_MD);
pxa_gpio_mode(GPIO39_FFTXD_MD);
// ST-UART
pxa_gpio_mode(GPIO46_STRXD_MD);
pxa_gpio_mode(GPIO47_STTXD_MD);
}
static void __init poodle_map_io(void)
{
pxa_map_io();
iotable_init(poodle_io_desc, ARRAY_SIZE(poodle_io_desc));
/* setup sleep mode values */
PWER = 0x00000002;
PFER = 0x00000000;
PRER = 0x00000002;
PGSR0 = 0x00008000;
PGSR1 = 0x003F0202;
PGSR2 = 0x0001C000;
PCFR |= PCFR_OPDE;
}
static void __init idp_map_io(void)
{
pxa_map_io();
iotable_init(idp_io_desc, ARRAY_SIZE(idp_io_desc));
// serial ports 2 & 3
pxa_gpio_mode(GPIO42_BTRXD_MD);
pxa_gpio_mode(GPIO43_BTTXD_MD);
pxa_gpio_mode(GPIO44_BTCTS_MD);
pxa_gpio_mode(GPIO45_BTRTS_MD);
pxa_gpio_mode(GPIO46_STRXD_MD);
pxa_gpio_mode(GPIO47_STTXD_MD);
}
static void __init corgi_map_io(void)
{
pxa_map_io();
iotable_init(corgi_io_desc,ARRAY_SIZE(corgi_io_desc));
/* setup sleep mode values */
PWER = 0x00000002;
PFER = 0x00000000;
PRER = 0x00000002;
PGSR0 = 0x0158C000;
PGSR1 = 0x00FF0080;
PGSR2 = 0x0001C004;
/* Stop 3.6MHz and drive HIGH to PCMCIA and CS */
PCFR |= PCFR_OPDE;
}
static void __init zeus_map_io(void)
{
pxa_map_io();
iotable_init(zeus_io_desc, ARRAY_SIZE(zeus_io_desc));
/* Clear PSPR to ensure a full restart on wake-up. */
PMCR = PSPR = 0;
/* enable internal 32.768Khz oscillator (ignore OSCC_OOK) */
OSCC |= OSCC_OON;
/* Some clock cycles later (from OSCC_ON), programme PCFR (OPDE...).
* float chip selects and PCMCIA */
PCFR = PCFR_OPDE | PCFR_DC_EN | PCFR_FS | PCFR_FP;
}
static void __init lpd270_map_io(void)
{
pxa_map_io();
iotable_init(lpd270_io_desc, ARRAY_SIZE(lpd270_io_desc));
/* initialize sleep mode regs (wake-up sources, etc) */
PGSR0 = 0x00008800;
PGSR1 = 0x00000002;
PGSR2 = 0x0001FC00;
PGSR3 = 0x00001F81;
PWER = 0xC0000002;
PRER = 0x00000002;
PFER = 0x00000002;
/* for use I SRAM as framebuffer. */
PSLR |= 0x00000F04;
PCFR = 0x00000066;
}
static void __init yf255_map_io(void)
{
pxa_map_io();
iotable_init(yf255_io_desc, ARRAY_SIZE(yf255_io_desc));
#if 1
//zkj add start --------------------------------------
/* low power mode setting */
/* if you can make the power consumption less, change the setting below */
PGSR0 = 0xC3E39FFC;
PGSR1 = 0xFCFFAB8C;
PGSR2 = 0x0001FFFF;
//zkj add end --------------------------------------
#endif
PCFR |= PCFR_OPDE;
#if 1
OSCC |= OSCC_OON; //zkj.
#endif
}
static void __init ez_x5_map_io(void)
{
pxa_map_io();
iotable_init(ez_x5_io_desc, ARRAY_SIZE(ez_x5_io_desc));
// FF-UART
pxa_gpio_mode(GPIO34_FFRXD_MD);
pxa_gpio_mode(GPIO39_FFTXD_MD);
// ST-UART
pxa_gpio_mode(GPIO46_STRXD_MD);
pxa_gpio_mode(GPIO47_STTXD_MD);
// BT-UART
pxa_gpio_mode(GPIO42_BTRXD_MD);
pxa_gpio_mode(GPIO43_BTTXD_MD);
// FB
set_pxa_fb_info(&falinux_ezlcd);
}
static int __init ibox_init(void)
{
pxa_map_io();
pxa_generic_init();
/* initialise I2C and give a slave address */
i2c_init(0xFF);
(void) platform_add_devices(devices, ARRAY_SIZE(devices));
pxa_gpio_func(21, GPIO_MODE, GPIO_IN);
/* Set rising edge detect for GPIO 21 */
GFER(21) &= ~GPIO_BIT(21);
GRER(21) |= (GPIO_BIT(21));
// set_irq_type(IBOX_ETH_IRQ, IRQT_RISING);
return 0;
}
static void __init roverp5p_map_io(void)
{
/* Initialize standard IO maps */
pxa_map_io();
//#ifdef DEBUG
// iotable_init(roverp5p_io_desc, ARRAY_SIZE(roverp5p_io_desc));
//#endif
/* Configure power management stuff. */
PWER = PWER_GPIO0 | PWER_RTC;
PFER = PWER_GPIO0 | PWER_RTC;
PRER = 0;
PCFR = PCFR_OPDE;
CKEN = CKEN6_FFUART;
PGSR0 = GPSRx_SleepValue;
PGSR1 = GPSRy_SleepValue;
PGSR2 = GPSRz_SleepValue;
/* Set up GPIO direction and alternate function registers */
GAFR0_L = GAFR0x_InitValue;
GAFR0_U = GAFR1x_InitValue;
GAFR1_L = GAFR0y_InitValue;
GAFR1_U = GAFR1y_InitValue;
GAFR2_L = GAFR0z_InitValue;
GAFR2_U = GAFR1z_InitValue;
GPDR0 = GPDRx_InitValue;
GPDR1 = GPDRy_InitValue;
GPDR2 = GPDRz_InitValue;
GPSR0 = GPSRx_InitValue;
GPSR1 = GPSRy_InitValue;
GPSR2 = GPSRz_InitValue;
GPCR0 = ~GPSRx_InitValue;
GPCR1 = ~GPSRy_InitValue;
GPCR2 = ~GPSRz_InitValue;
// GPCR0 = 0x0fffffff; /* All outputs are set low by default */
// printk("map_io done \n");
}
static void __init mainstone_map_io(void)
{
pxa_map_io();
iotable_init(mainstone_io_desc, ARRAY_SIZE(mainstone_io_desc));
/* initialize sleep mode regs (wake-up sources, etc) */
PGSR0 = 0x00008800;
PGSR1 = 0x00000002;
PGSR2 = 0x0001FC00;
PGSR3 = 0x00001F81;
PWER = 0xC0000002;
PRER = 0x00000002;
PFER = 0x00000002;
/* for use I SRAM as framebuffer. */
PSLR |= 0xF04;
PCFR = 0x66;
/* For Keypad wakeup. */
KPC &=~KPC_ASACT;
KPC |=KPC_AS;
PKWR = 0x000FD000;
/* Need read PKWR back after set it. */
PKWR;
}
static void __init lubbock_map_io(void)
{
pxa_map_io();
iotable_init(lubbock_io_desc, ARRAY_SIZE(lubbock_io_desc));
/* This enables the BTUART */
pxa_gpio_mode(GPIO42_BTRXD_MD);
pxa_gpio_mode(GPIO43_BTTXD_MD);
pxa_gpio_mode(GPIO44_BTCTS_MD);
pxa_gpio_mode(GPIO45_BTRTS_MD);
/* This is for the SMC chip select */
pxa_gpio_mode(GPIO79_nCS_3_MD);
/* setup sleep mode values */
PWER = 0x00000002;
PFER = 0x00000000;
PRER = 0x00000002;
PGSR0 = 0x00008000;
PGSR1 = 0x003F0202;
PGSR2 = 0x0001C000;
PCFR |= PCFR_OPDE;
}
static void __init csb226_map_io(void)
{
pxa_map_io();
iotable_init(csb226_io_desc);
/* This enables the BTUART */
CKEN |= CKEN7_BTUART;
set_GPIO_mode(GPIO42_BTRXD_MD);
set_GPIO_mode(GPIO43_BTTXD_MD);
set_GPIO_mode(GPIO44_BTCTS_MD);
set_GPIO_mode(GPIO45_BTRTS_MD);
/* This is for the CS8900 chip select */
set_GPIO_mode(GPIO78_nCS_2_MD);
/* setup sleep mode values */
PWER = 0x00000002;
PFER = 0x00000000;
PRER = 0x00000002;
PGSR0 = 0x00008000;
PGSR1 = 0x003F0202;
PGSR2 = 0x0001C000;
PCFR |= PCFR_OPDE;
}
static void __init balloon3_map_io(void)
{
pxa_map_io();
iotable_init(balloon3_io_desc, ARRAY_SIZE(balloon3_io_desc));
}
static void __init idp_map_io(void)
{
pxa_map_io();
iotable_init(idp_io_desc, ARRAY_SIZE(idp_io_desc));
}
static void __init cmx2xx_map_io(void)
{
pxa_map_io();
}
void __init pxa25x_map_io(void)
{
pxa_map_io();
iotable_init(ARRAY_AND_SIZE(pxa25x_io_desc));
pxa25x_get_clk_frequency_khz(1);
}
static void __init cmx270_map_io(void)
{
pxa_map_io();
iotable_init(cmx270_io_desc, ARRAY_SIZE(cmx270_io_desc));
}
/* Initialization code */
static void __init a730_map_io(void)
{
pxa_map_io();
}
static void __init simcom_map_io(void)
{
pxa_map_io();
}
static void __init palmld_map_io(void)
{
pxa_map_io();
iotable_init(palmld_io_desc, ARRAY_SIZE(palmld_io_desc));
}