/*******************************************************************************
* miiSmiIfWriteRegister
*
* DESCRIPTION:
* This function writes to a register throw the SMI / MII interface, to be
* used by upper layers.
*
* INPUTS:
* phyAddr - The PHY address to be read.
* regAddr - The register address to read.
* data - The data to be written to the register.
*
* OUTPUTS:
* None.
*
* RETURNS:
* GT_OK - on success
* GT_FAIL - on error
*
* COMMENTS:
* None.
*
*******************************************************************************/
GT_STATUS miiSmiIfWriteRegister
(
IN GT_QD_DEV *dev,
IN GT_U8 phyAddr,
IN GT_U8 regAddr,
IN GT_U16 data
)
{
#ifdef GT_RMGMT_ACCESS
if((dev->accessMode == SMI_MULTI_ADDR_MODE) &&
(dev->fgtHwAccessMod == HW_ACCESS_MODE_SMI))
#else
if(dev->accessMode == SMI_MULTI_ADDR_MODE)
#endif
{
if(qdMultiAddrWrite(dev,(GT_U32)phyAddr,(GT_U32)regAddr,(GT_U32)data) != GT_TRUE)
{
return GT_FAIL;
}
}
else
{
if(fgtWriteMii(dev,(GT_U32)phyAddr,(GT_U32)regAddr,(GT_U32)data) != GT_TRUE)
{
return GT_FAIL;
}
}
return GT_OK;
}
/*******************************************************************************
* miiSmiIfWriteRegister
*
* DESCRIPTION:
* This function writes to a register throw the SMI / MII interface, to be
* used by upper layers.
*
* INPUTS:
* phyAddr - The PHY address to be read.
* regAddr - The register address to read.
* data - The data to be written to the register.
*
* OUTPUTS:
* None.
*
* RETURNS:
* GT_OK - on success
* GT_FAIL - on error
*
* COMMENTS:
* None.
*
*******************************************************************************/
GT_STATUS miiSmiIfWriteRegister
(
IN GT_QD_DEV *dev,
IN GT_U8 phyAddr,
IN GT_U8 regAddr,
IN GT_U16 data
)
{
if(dev->accessMode == SMI_MULTI_ADDR_MODE)
{
if(qdMultiAddrWrite(dev,(GT_U32)phyAddr,(GT_U32)regAddr,(GT_U32)data) != GT_TRUE)
{
return GT_FAIL;
}
}
else
{
if(dev->fgtWriteMii(dev,(GT_U32)phyAddr,(GT_U32)regAddr,(GT_U32)data) != GT_TRUE)
{
return GT_FAIL;
}
}
return GT_OK;
}
