static void qib_msix_setup(struct qib_devdata *dd, int pos, u32 *msixcnt,
struct msix_entry *msix_entry)
{
int ret;
u32 tabsize = 0;
u16 msix_flags;
pci_read_config_word(dd->pcidev, pos + PCI_MSIX_FLAGS, &msix_flags);
tabsize = 1 + (msix_flags & PCI_MSIX_FLAGS_QSIZE);
if (tabsize > *msixcnt)
tabsize = *msixcnt;
ret = pci_enable_msix(dd->pcidev, msix_entry, tabsize);
if (ret > 0) {
qib_dbg("Couldn't get %d MSIx vectors, "
"trying to get %d\n", tabsize, ret);
tabsize = ret;
ret = pci_enable_msix(dd->pcidev, msix_entry, tabsize);
}
if (ret) {
qib_dev_err(dd, "pci_enable_msix %d vectors failed: %d, "
"falling back to INTx\n", tabsize, ret);
tabsize = 0;
}
*msixcnt = tabsize;
if (ret)
qib_enable_intx(dd->pcidev);
}
/*
* Do remaining PCIe setup, once dd is allocated, and save away
* fields required to re-initialize after a chip reset, or for
* various other purposes
*/
int qib_pcie_ddinit(struct qib_devdata *dd, struct pci_dev *pdev,
const struct pci_device_id *ent)
{
unsigned long len;
resource_size_t addr;
dd->pcidev = pdev;
pci_set_drvdata(pdev, dd);
addr = pci_resource_start(pdev, 0);
len = pci_resource_len(pdev, 0);
qib_cdbg(VERBOSE, "regbase (0) %llx len %ld vend %x/%x "
"driver_data %p\n", (unsigned long long)addr, len,
ent->vendor, ent->device, pci_get_drvdata(pdev));
#if defined(__powerpc__)
/* There isn't a generic way to specify writethrough mappings */
dd->kregbase = __ioremap(addr, len, _PAGE_NO_CACHE | _PAGE_WRITETHRU);
#else
dd->kregbase = ioremap_nocache(addr, len);
#endif
if (!dd->kregbase) {
qib_dbg("Unable to map io addr %llx to kvirt, failing\n",
(unsigned long long)addr);
return -ENOMEM;
}
dd->kregend = (u64 __iomem *)((void __iomem *) dd->kregbase + len);
dd->physaddr = addr; /* used for io_remap, etc. */
/* for user mmap */
qib_cdbg(VERBOSE, "mapped io addr %llx to kregbase %p through %p\n",
(unsigned long long)addr, dd->kregbase, dd->kregend);
/*
* Save BARs to rewrite after device reset. Save all 64 bits of
* BAR, just in case.
*/
dd->pcibar0 = addr;
dd->pcibar1 = addr >> 32;
dd->deviceid = ent->device; /* save for later use */
dd->vendorid = ent->vendor;
return 0;
}
/*
* Initialize structures that control access to QSFP. Called once per port
* on cards that support QSFP.
*/
void qib_qsfp_init(struct qib_qsfp_data *qd,
void (*fevent)(struct work_struct *))
{
u32 mask, highs;
int pins;
struct qib_devdata *dd = qd->ppd->dd;
/* Initialize work struct for later QSFP events */
INIT_WORK(&qd->work, fevent);
/*
* Later, we may want more validation. For now, just set up pins and
* blip reset. If module is present, call qib_refresh_qsfp_cache(),
* to do further init.
*/
mask = QSFP_GPIO_MOD_SEL_N | QSFP_GPIO_MOD_RST_N | QSFP_GPIO_LP_MODE;
highs = mask - QSFP_GPIO_MOD_RST_N;
if (qd->ppd->hw_pidx) {
mask <<= QSFP_GPIO_PORT2_SHIFT;
highs <<= QSFP_GPIO_PORT2_SHIFT;
}
dd->f_gpio_mod(dd, highs, mask, mask);
udelay(20); /* Generous RST dwell */
dd->f_gpio_mod(dd, mask, mask, mask);
/* Spec says module can take up to two seconds! */
mask = QSFP_GPIO_MOD_PRS_N;
if (qd->ppd->hw_pidx)
mask <<= QSFP_GPIO_PORT2_SHIFT;
/* Do not try to wait here. Better to let event handle it */
pins = dd->f_gpio_mod(dd, 0, 0, 0);
if (pins & mask) {
qib_dbg("IB%u:%u has no QSFP module present\n",
qd->ppd->dd->unit, qd->ppd->port);
goto bail;
}
/* We see a module, but it may be unwise to look yet. Just schedule */
qd->t_insert = get_jiffies_64();
schedule_work(&qd->work);
bail:
return;
}
/*
* Initialize structures that control access to QSFP. Called once per port
* on cards that support QSFP.
*/
void qib_qsfp_init(struct qib_qsfp_data *qd,
void (*fevent)(struct work_struct *))
{
u32 mask, highs;
struct qib_devdata *dd = qd->ppd->dd;
/* Initialize work struct for later QSFP events */
INIT_WORK(&qd->work, fevent);
/*
* Later, we may want more validation. For now, just set up pins and
* blip reset. If module is present, call qib_refresh_qsfp_cache(),
* to do further init.
*/
mask = QSFP_GPIO_MOD_SEL_N | QSFP_GPIO_MOD_RST_N | QSFP_GPIO_LP_MODE;
highs = mask - QSFP_GPIO_MOD_RST_N;
if (qd->ppd->hw_pidx) {
mask <<= QSFP_GPIO_PORT2_SHIFT;
highs <<= QSFP_GPIO_PORT2_SHIFT;
}
dd->f_gpio_mod(dd, highs, mask, mask);
udelay(20); /* Generous RST dwell */
dd->f_gpio_mod(dd, mask, mask, mask);
/* Spec says module can take up to two seconds! */
mask = QSFP_GPIO_MOD_PRS_N;
if (qd->ppd->hw_pidx)
mask <<= QSFP_GPIO_PORT2_SHIFT;
/* Do not try to wait here. Better to let event handle it */
if (!qib_qsfp_mod_present(qd->ppd))
qib_dbg("IB%u:%u has no QSFP module present\n",
qd->ppd->dd->unit, qd->ppd->port);
return;
}
int qib_alloc_lkey(struct qib_mregion *mr, int dma_region)
{
unsigned long flags;
u32 r;
u32 n;
int ret = 0;
struct qib_ibdev *dev = to_idev(mr->pd->device);
struct qib_lkey_table *rkt = &dev->lk_table;
spin_lock_irqsave(&rkt->lock, flags);
/* special case for dma_mr lkey == 0 */
if (dma_region) {
struct qib_mregion *tmr;
tmr = rcu_dereference(dev->dma_mr);
if (!tmr) {
qib_get_mr(mr);
rcu_assign_pointer(dev->dma_mr, mr);
mr->lkey_published = 1;
}
goto success;
}
/* Find the next available LKEY */
r = rkt->next;
n = r;
for (;;) {
if (rkt->table[r] == NULL)
break;
r = (r + 1) & (rkt->max - 1);
if (r == n) {
qib_dbg("LKEY table full\n");
goto bail;
}
}
rkt->next = (r + 1) & (rkt->max - 1);
/*
* Make sure lkey is never zero which is reserved to indicate an
* unrestricted LKEY.
*/
rkt->gen++;
mr->lkey = (r << (32 - ib_qib_lkey_table_size)) |
((((1 << (24 - ib_qib_lkey_table_size)) - 1) & rkt->gen)
<< 8);
if (mr->lkey == 0) {
mr->lkey |= 1 << 8;
rkt->gen++;
}
qib_get_mr(mr);
rcu_assign_pointer(rkt->table[r], mr);
mr->lkey_published = 1;
success:
spin_unlock_irqrestore(&rkt->lock, flags);
out:
return ret;
bail:
spin_unlock_irqrestore(&rkt->lock, flags);
ret = -ENOMEM;
goto out;
}
int qib_qsfp_dump(struct qib_pportdata *ppd, char *buf, int len)
{
struct qib_qsfp_cache cd;
u8 bin_buff[QSFP_DUMP_CHUNK];
char lenstr[6];
int sofar, ret;
int bidx = 0;
sofar = 0;
ret = qib_refresh_qsfp_cache(ppd, &cd);
if (ret < 0) {
qib_dbg("IB%u:%u QSFP cache-refresh failed\n", ppd->dd->unit,
ppd->port);
goto bail;
}
lenstr[0] = ' ';
lenstr[1] = '\0';
if (QSFP_IS_CU(cd.tech))
sprintf(lenstr, "%dM ", cd.len);
sofar += scnprintf(buf + sofar, len - sofar, "PWR:%.3sW\n", pwr_codes +
(QSFP_PWR(cd.pwr) * 4));
sofar += scnprintf(buf + sofar, len - sofar, "TECH:%s%s\n", lenstr,
qib_qsfp_devtech[cd.tech >> 4]);
sofar += scnprintf(buf + sofar, len - sofar, "Vendor:%.*s\n",
QSFP_VEND_LEN, cd.vendor);
sofar += scnprintf(buf + sofar, len - sofar, "OUI:%06X\n",
QSFP_OUI(cd.oui));
sofar += scnprintf(buf + sofar, len - sofar, "Part#:%.*s\n",
QSFP_PN_LEN, cd.partnum);
sofar += scnprintf(buf + sofar, len - sofar, "Rev:%.*s\n",
QSFP_REV_LEN, cd.rev);
if (QSFP_IS_CU(cd.tech))
sofar += scnprintf(buf + sofar, len - sofar, "Atten:%d, %d\n",
QSFP_ATTEN_SDR(cd.atten),
QSFP_ATTEN_DDR(cd.atten));
sofar += scnprintf(buf + sofar, len - sofar, "Serial:%.*s\n",
QSFP_SN_LEN, cd.serial);
sofar += scnprintf(buf + sofar, len - sofar, "Date:%.*s\n",
QSFP_DATE_LEN, cd.date);
sofar += scnprintf(buf + sofar, len - sofar, "Lot:%.*s\n",
QSFP_LOT_LEN, cd.date);
while (bidx < QSFP_DEFAULT_HDR_CNT) {
int iidx;
ret = qsfp_read(ppd, bidx, bin_buff, QSFP_DUMP_CHUNK);
if (ret < 0)
goto bail;
for (iidx = 0; iidx < ret; ++iidx) {
sofar += scnprintf(buf + sofar, len-sofar, " %02X",
bin_buff[iidx]);
}
sofar += scnprintf(buf + sofar, len - sofar, "\n");
bidx += QSFP_DUMP_CHUNK;
}
ret = sofar;
bail:
return ret;
}
static int qsfp_read(struct qib_pportdata *ppd, int addr, void *bp, int len)
{
struct qib_devdata *dd = ppd->dd;
u32 out, mask;
int ret, cnt, pass = 0;
int stuck = 0;
u8 *buff = bp;
qib_cdbg(VERBOSE, "Grabbing Mutex for QSFP in %d:%d\n", dd->unit,
ppd->port);
ret = mutex_lock_interruptible(&dd->eep_lock);
if (ret)
goto no_unlock;
if (dd->twsi_eeprom_dev == QIB_TWSI_NO_DEV) {
qib_dbg("QSFP read on board without QSFP\n");
ret = -ENXIO;
goto bail;
}
/*
* We presume, if we are called at all, that this board has
* QSFP. This is on the same i2c chain as the legacy parts,
* but only responds if the module is selected via GPIO pins.
* Further, there are very long setup and hold requirements
* on MODSEL.
*/
mask = QSFP_GPIO_MOD_SEL_N | QSFP_GPIO_MOD_RST_N | QSFP_GPIO_LP_MODE;
out = QSFP_GPIO_MOD_RST_N | QSFP_GPIO_LP_MODE;
if (ppd->hw_pidx) {
mask <<= QSFP_GPIO_PORT2_SHIFT;
out <<= QSFP_GPIO_PORT2_SHIFT;
}
dd->f_gpio_mod(dd, out, mask, mask);
/*
* Module could take up to 2 Msec to respond to MOD_SEL, and there
* is no way to tell if it is ready, so we must wait.
*/
msleep(2);
/* Make sure TWSI bus is in sane state. */
ret = qib_twsi_reset(dd);
if (ret) {
qib_dev_porterr(dd, ppd->port,
"QSFP interface Reset for read failed\n");
ret = -EIO;
stuck = 1;
goto deselect;
}
/* All QSFP modules are at A0 */
cnt = 0;
while (cnt < len) {
unsigned in_page;
int wlen = len - cnt;
in_page = addr % QSFP_PAGESIZE;
if ((in_page + wlen) > QSFP_PAGESIZE)
wlen = QSFP_PAGESIZE - in_page;
ret = qib_twsi_blk_rd(dd, QSFP_DEV, addr, buff + cnt, wlen);
/* Some QSFP's fail first try. Retry as experiment */
if (ret && cnt == 0 && ++pass < QSFP_MAX_RETRY)
continue;
if (ret) {
/* qib_twsi_blk_rd() 1 for error, else 0 */
ret = -EIO;
goto deselect;
}
addr += wlen;
cnt += wlen;
}
ret = cnt;
deselect:
/*
* Module could take up to 10 uSec after transfer before
* ready to respond to MOD_SEL negation, and there is no way
* to tell if it is ready, so we must wait.
*/
udelay(10);
/* set QSFP MODSEL, RST. LP all high */
dd->f_gpio_mod(dd, mask, mask, mask);
/*
* Module could take up to 2 Msec to respond to MOD_SEL
* going away, and there is no way to tell if it is ready.
* so we must wait.
*/
if (stuck)
qib_dev_err(dd, "QSFP interface bus stuck non-idle\n");
if (pass >= QSFP_MAX_RETRY && ret)
qib_dev_porterr(dd, ppd->port, "QSFP failed even retrying\n");
else if (pass)
qib_dev_porterr(dd, ppd->port, "QSFP retries: %d\n", pass);
msleep(2);
bail:
mutex_unlock(&dd->eep_lock);
qib_cdbg(VERBOSE, "Released Mutex for QSFP %d:%d, ret %d\n", dd->unit,
ppd->port, ret);
no_unlock:
return ret;
}
int qib_refresh_qsfp_cache(struct qib_pportdata *ppd, struct qib_qsfp_cache *cp)
{
int ret;
int idx;
u16 cks;
u8 peek[4];
/* ensure sane contents on invalid reads, for cable swaps */
memset(cp, 0, sizeof(*cp));
if (!qib_qsfp_mod_present(ppd)) {
qib_dbg("No QSFP module in %d:%d\n", ppd->dd->unit, ppd->port);
ret = -ENODEV;
goto bail;
}
ret = qsfp_read(ppd, 0, peek, 3);
if (ret < 0)
goto bail;
if ((peek[0] & 0xFE) != 0x0C)
qib_dev_porterr(ppd->dd, ppd->port,
"QSFP byte0 is 0x%02X, S/B 0x0C/D\n", peek[0]);
if ((peek[2] & 2) == 0) {
/*
* If cable is paged, rather than "flat memory", we need to
* set the page to zero, Even if it already appears to be zero.
*/
u8 poke = 0;
ret = qib_qsfp_write(ppd, 127, &poke, 1);
udelay(50);
if (ret != 1) {
qib_dev_porterr(ppd->dd, ppd->port,
"Failed QSFP Page set\n");
goto bail;
}
}
ret = qsfp_read(ppd, QSFP_MOD_ID_OFFS, &cp->id, 1);
if (ret < 0)
goto bail;
if ((cp->id & 0xFE) != 0x0C)
qib_dev_porterr(ppd->dd, ppd->port,
"QSFP ID byte is 0x%02X, S/B 0x0C/D\n", cp->id);
cks = cp->id;
ret = qsfp_read(ppd, QSFP_MOD_PWR_OFFS, &cp->pwr, 1);
if (ret < 0)
goto bail;
cks += cp->pwr;
ret = qsfp_cks(ppd, QSFP_MOD_PWR_OFFS + 1, QSFP_MOD_LEN_OFFS);
if (ret < 0)
goto bail;
cks += ret;
ret = qsfp_read(ppd, QSFP_MOD_LEN_OFFS, &cp->len, 1);
if (ret < 0)
goto bail;
cks += cp->len;
ret = qsfp_read(ppd, QSFP_MOD_TECH_OFFS, &cp->tech, 1);
if (ret < 0)
goto bail;
cks += cp->tech;
ret = qsfp_read(ppd, QSFP_VEND_OFFS, &cp->vendor, QSFP_VEND_LEN);
if (ret < 0)
goto bail;
for (idx = 0; idx < QSFP_VEND_LEN; ++idx)
cks += cp->vendor[idx];
ret = qsfp_read(ppd, QSFP_IBXCV_OFFS, &cp->xt_xcv, 1);
if (ret < 0)
goto bail;
cks += cp->xt_xcv;
ret = qsfp_read(ppd, QSFP_VOUI_OFFS, &cp->oui, QSFP_VOUI_LEN);
if (ret < 0)
goto bail;
for (idx = 0; idx < QSFP_VOUI_LEN; ++idx)
cks += cp->oui[idx];
ret = qsfp_read(ppd, QSFP_PN_OFFS, &cp->partnum, QSFP_PN_LEN);
if (ret < 0)
goto bail;
for (idx = 0; idx < QSFP_PN_LEN; ++idx)
cks += cp->partnum[idx];
ret = qsfp_read(ppd, QSFP_REV_OFFS, &cp->rev, QSFP_REV_LEN);
if (ret < 0)
goto bail;
for (idx = 0; idx < QSFP_REV_LEN; ++idx)
cks += cp->rev[idx];
ret = qsfp_read(ppd, QSFP_ATTEN_OFFS, &cp->atten, QSFP_ATTEN_LEN);
if (ret < 0)
goto bail;
for (idx = 0; idx < QSFP_ATTEN_LEN; ++idx)
cks += cp->atten[idx];
ret = qsfp_cks(ppd, QSFP_ATTEN_OFFS + QSFP_ATTEN_LEN, QSFP_CC_OFFS);
if (ret < 0)
goto bail;
cks += ret;
cks &= 0xFF;
ret = qsfp_read(ppd, QSFP_CC_OFFS, &cp->cks1, 1);
if (ret < 0)
goto bail;
if (cks != cp->cks1)
qib_dev_porterr(ppd->dd, ppd->port,
"QSFP cks1 is %02X, computed %02X\n", cp->cks1,
cks);
/* Second checksum covers 192 to (serial, date, lot) */
ret = qsfp_cks(ppd, QSFP_CC_OFFS + 1, QSFP_SN_OFFS);
if (ret < 0)
goto bail;
cks = ret;
ret = qsfp_read(ppd, QSFP_SN_OFFS, &cp->serial, QSFP_SN_LEN);
if (ret < 0)
goto bail;
for (idx = 0; idx < QSFP_SN_LEN; ++idx)
cks += cp->serial[idx];
ret = qsfp_read(ppd, QSFP_DATE_OFFS, &cp->date, QSFP_DATE_LEN);
if (ret < 0)
goto bail;
for (idx = 0; idx < QSFP_DATE_LEN; ++idx)
cks += cp->date[idx];
ret = qsfp_read(ppd, QSFP_LOT_OFFS, &cp->lot, QSFP_LOT_LEN);
if (ret < 0)
goto bail;
for (idx = 0; idx < QSFP_LOT_LEN; ++idx)
cks += cp->lot[idx];
ret = qsfp_cks(ppd, QSFP_LOT_OFFS + QSFP_LOT_LEN, QSFP_CC_EXT_OFFS);
if (ret < 0)
goto bail;
cks += ret;
ret = qsfp_read(ppd, QSFP_CC_EXT_OFFS, &cp->cks2, 1);
if (ret < 0)
goto bail;
cks &= 0xFF;
if (cks != cp->cks2)
qib_dev_porterr(ppd->dd, ppd->port,
"QSFP cks2 is %02X, computed %02X\n", cp->cks2,
cks);
return 0;
bail:
cp->id = 0;
return ret;
}
/*
* Do all the common PCIe setup and initialization.
* devdata is not yet allocated, and is not allocated until after this
* routine returns success. Therefore qib_dev_err() can't be used for error
* printing.
*/
int qib_pcie_init(struct pci_dev *pdev, const struct pci_device_id *ent)
{
int ret;
ret = pci_enable_device(pdev);
if (ret) {
/*
* This can happen (in theory) iff:
* We did a chip reset, and then failed to reprogram the
* BAR, or the chip reset due to an internal error. We then
* unloaded the driver and reloaded it.
*
* Both reset cases set the BAR back to initial state. For
* the latter case, the AER sticky error bit at offset 0x718
* should be set, but the Linux kernel doesn't yet know
* about that, it appears. If the original BAR was retained
* in the kernel data structures, this may be OK.
*/
qib_early_err(&pdev->dev, "pci enable failed: error %d\n",
-ret);
goto done;
}
ret = pci_request_regions(pdev, QIB_DRV_NAME);
if (ret) {
qib_devinfo(pdev, "pci_request_regions fails: err %d\n",
-ret);
goto bail;
}
ret = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
if (ret) {
/*
* If the 64 bit setup fails, try 32 bit. Some systems
* do not setup 64 bit maps on systems with 2GB or less
* memory installed.
*/
ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
if (ret) {
qib_devinfo(pdev, "Unable to set DMA mask: %d\n", ret);
goto bail;
}
qib_dbg("No 64bit DMA mask, used 32 bit mask\n");
ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
} else
ret = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
if (ret) {
qib_early_err(&pdev->dev,
"Unable to set DMA consistent mask: %d\n", ret);
goto bail;
}
pci_set_master(pdev);
#ifdef CONFIG_PCIEAER
/* enable basic AER reporting. Perhaps more later */
if (pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR)) {
ret = pci_enable_pcie_error_reporting(pdev);
if (ret)
qib_early_err(&pdev->dev,
"Unable to enable pcie error reporting"
": %d\n", ret);
ret = 0;
} else
qib_dbg("AER capability not found! AER reports not enabled\n");
#endif
goto done;
bail:
pci_disable_device(pdev);
pci_release_regions(pdev);
done:
return ret;
}
int qib_pcie_params(struct qib_devdata *dd, u32 minw, u32 *nent,
struct msix_entry *entry)
{
u16 linkstat, speed;
int pos = 0, pose, ret = 1;
pose = pci_find_capability(dd->pcidev, PCI_CAP_ID_EXP);
if (!pose) {
qib_dev_err(dd, "Can't find PCI Express capability!\n");
/* set up something... */
dd->lbus_width = 1;
dd->lbus_speed = 2500; /* Gen1, 2.5GHz */
goto bail;
}
#ifdef CONFIG_PCI_MSI
pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSIX);
if (nent && *nent && pos) {
qib_msix_setup(dd, pos, nent, entry);
ret = 0; /* did it, either MSIx or INTx */
} else {
pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI);
if (pos)
ret = qib_msi_setup(dd, pos);
else
qib_dev_err(dd, "No PCI MSI or MSIx capability!\n");
}
#else
ret = 0; /* no MSI or MSIx support; OK */
#endif /* CONFIG_PCI_MSI */
if (!pos)
qib_enable_intx(dd->pcidev);
pci_read_config_word(dd->pcidev, pose + PCI_EXP_LNKSTA, &linkstat);
/*
* speed is bits 0-3, linkwidth is bits 4-8
* no defines for them in headers
*/
speed = linkstat & 0xf;
linkstat >>= 4;
linkstat &= 0x1f;
dd->lbus_width = linkstat;
switch (speed) {
case 1:
dd->lbus_speed = 2500; /* Gen1, 2.5GHz */
break;
case 2:
dd->lbus_speed = 5000; /* Gen1, 5GHz */
break;
default: /* not defined, assume gen1 */
qib_dbg("PCIe unexpected link speed %u\n", speed);
dd->lbus_speed = 2500;
break;
}
/*
* check against expected pcie width and complain if "wrong"
* on first initialization, not afterwards (i.e., reset).
*/
if (minw && linkstat < minw)
qib_dev_err(dd,
"PCIe width %u (x%u HCA), performance reduced\n",
linkstat, minw);
else
qib_cdbg(VERBOSE, "PCIe speed %u width %u (x8 HCA)\n",
dd->lbus_speed, linkstat);
qib_tune_pcie_caps(dd);
qib_tune_pcie_coalesce(dd);
bail:
/* fill in string, even on errors */
snprintf(dd->lbus_info, sizeof(dd->lbus_info),
"PCIe,%uMHz,x%u\n", dd->lbus_speed, dd->lbus_width);
return ret;
}
