static void r300_setup_miptree(struct r300_screen *screen,
struct r300_resource *tex,
boolean align_for_cbzb)
{
struct pipe_resource *base = &tex->b.b.b;
unsigned stride, size, layer_size, nblocksy, i;
boolean rv350_mode = screen->caps.family >= CHIP_FAMILY_R350;
boolean aligned_for_cbzb;
tex->tex.size_in_bytes = 0;
SCREEN_DBG(screen, DBG_TEXALLOC,
"r300: Making miptree for texture, format %s\n",
util_format_short_name(base->format));
for (i = 0; i <= base->last_level; i++) {
/* Let's see if this miplevel can be macrotiled. */
tex->tex.macrotile[i] =
(tex->tex.macrotile[0] == RADEON_LAYOUT_TILED &&
r300_texture_macro_switch(tex, i, rv350_mode, DIM_WIDTH) &&
r300_texture_macro_switch(tex, i, rv350_mode, DIM_HEIGHT)) ?
RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
stride = r300_texture_get_stride(screen, tex, i);
/* Compute the number of blocks in Y, see if the CBZB clear can be
* used on the texture. */
aligned_for_cbzb = FALSE;
if (align_for_cbzb && tex->tex.cbzb_allowed[i])
nblocksy = r300_texture_get_nblocksy(tex, i, &aligned_for_cbzb);
else
nblocksy = r300_texture_get_nblocksy(tex, i, NULL);
layer_size = stride * nblocksy;
if (base->nr_samples) {
layer_size *= base->nr_samples;
}
if (base->target == PIPE_TEXTURE_CUBE)
size = layer_size * 6;
else
size = layer_size * u_minify(tex->tex.depth0, i);
tex->tex.offset_in_bytes[i] = tex->tex.size_in_bytes;
tex->tex.size_in_bytes = tex->tex.offset_in_bytes[i] + size;
tex->tex.layer_size_in_bytes[i] = layer_size;
tex->tex.stride_in_bytes[i] = stride;
tex->tex.stride_in_pixels[i] = stride_to_width(tex->b.b.b.format, stride);
tex->tex.cbzb_allowed[i] = tex->tex.cbzb_allowed[i] && aligned_for_cbzb;
SCREEN_DBG(screen, DBG_TEXALLOC, "r300: Texture miptree: Level %d "
"(%dx%dx%d px, pitch %d bytes) %d bytes total, macrotiled %s\n",
i, u_minify(tex->tex.width0, i), u_minify(tex->tex.height0, i),
u_minify(tex->tex.depth0, i), stride, tex->tex.size_in_bytes,
tex->tex.macrotile[i] ? "TRUE" : "FALSE");
}
}
static void r300_setup_tiling(struct r300_screen *screen,
struct r300_resource *tex)
{
enum pipe_format format = tex->b.b.format;
boolean rv350_mode = screen->caps.family >= CHIP_R350;
boolean is_zb = util_format_is_depth_or_stencil(format);
boolean dbg_no_tiling = SCREEN_DBG_ON(screen, DBG_NO_TILING);
boolean force_microtiling =
(tex->b.b.flags & R300_RESOURCE_FORCE_MICROTILING) != 0;
if (tex->b.b.nr_samples > 1) {
tex->tex.microtile = RADEON_LAYOUT_TILED;
tex->tex.macrotile[0] = RADEON_LAYOUT_TILED;
return;
}
tex->tex.microtile = RADEON_LAYOUT_LINEAR;
tex->tex.macrotile[0] = RADEON_LAYOUT_LINEAR;
if (tex->b.b.usage == PIPE_USAGE_STAGING) {
return;
}
if (!util_format_is_plain(format)) {
return;
}
/* If height == 1, disable microtiling except for zbuffer. */
if (!force_microtiling && !is_zb &&
(tex->b.b.height0 == 1 || dbg_no_tiling)) {
return;
}
/* Set microtiling. */
switch (util_format_get_blocksize(format)) {
case 1:
case 4:
case 8:
tex->tex.microtile = RADEON_LAYOUT_TILED;
break;
case 2:
tex->tex.microtile = RADEON_LAYOUT_SQUARETILED;
break;
}
if (dbg_no_tiling) {
return;
}
/* Set macrotiling. */
if (r300_texture_macro_switch(tex, 0, rv350_mode, DIM_WIDTH) &&
r300_texture_macro_switch(tex, 0, rv350_mode, DIM_HEIGHT)) {
tex->tex.macrotile[0] = RADEON_LAYOUT_TILED;
}
}
static void r300_setup_tiling(struct r300_screen *screen,
struct r300_texture_desc *desc)
{
struct r300_winsys_screen *rws = screen->rws;
enum pipe_format format = desc->b.b.format;
boolean rv350_mode = screen->caps.family >= CHIP_FAMILY_R350;
boolean is_zb = util_format_is_depth_or_stencil(format);
boolean dbg_no_tiling = SCREEN_DBG_ON(screen, DBG_NO_TILING);
if (!util_format_is_plain(format)) {
return;
}
/* If height == 1, disable microtiling except for zbuffer. */
if (!is_zb && (desc->b.b.height0 == 1 || dbg_no_tiling)) {
return;
}
/* Set microtiling. */
switch (util_format_get_blocksize(format)) {
case 1:
case 4:
desc->microtile = R300_BUFFER_TILED;
break;
case 2:
case 8:
if (rws->get_value(rws, R300_VID_SQUARE_TILING_SUPPORT)) {
desc->microtile = R300_BUFFER_SQUARETILED;
}
break;
}
if (dbg_no_tiling) {
return;
}
/* Set macrotiling. */
if (r300_texture_macro_switch(desc, 0, rv350_mode, DIM_WIDTH) &&
r300_texture_macro_switch(desc, 0, rv350_mode, DIM_HEIGHT)) {
desc->macrotile[0] = R300_BUFFER_TILED;
}
}
static void r300_setup_miptree(struct r300_screen* screen,
struct r300_texture* tex)
{
struct pipe_texture* base = &tex->tex;
unsigned stride, size, layer_size, nblocksy, i;
boolean rv350_mode = screen->caps->family >= CHIP_FAMILY_RV350;
SCREEN_DBG(screen, DBG_TEX, "r300: Making miptree for texture, format %s\n",
util_format_name(base->format));
for (i = 0; i <= base->last_level; i++) {
/* Let's see if this miplevel can be macrotiled. */
tex->mip_macrotile[i] = (tex->macrotile == R300_BUFFER_TILED &&
r300_texture_macro_switch(tex, i, rv350_mode)) ?
R300_BUFFER_TILED : R300_BUFFER_LINEAR;
stride = r300_texture_get_stride(screen, tex, i);
nblocksy = r300_texture_get_nblocksy(tex, i);
layer_size = stride * nblocksy;
if (base->target == PIPE_TEXTURE_CUBE)
size = layer_size * 6;
else
size = layer_size * u_minify(base->depth0, i);
tex->offset[i] = tex->size;
tex->size = tex->offset[i] + size;
tex->layer_size[i] = layer_size;
tex->pitch[i] = stride / util_format_get_blocksize(base->format);
SCREEN_DBG(screen, DBG_TEX, "r300: Texture miptree: Level %d "
"(%dx%dx%d px, pitch %d bytes) %d bytes total, macrotiled %s\n",
i, u_minify(base->width0, i), u_minify(base->height0, i),
u_minify(base->depth0, i), stride, tex->size,
tex->mip_macrotile[i] ? "TRUE" : "FALSE");
}
}
