static void radeonDRI2Flush(__DRIdrawable *drawable) { radeonContextPtr rmesa; rmesa = (radeonContextPtr) drawable->driContextPriv->driverPrivate; radeonFlush(&rmesa->glCtx); }
/** * Copy a region of [@a width x @a height] pixels from source buffer * to destination buffer. * @param[in] r200 r200 context * @param[in] src_bo source radeon buffer object * @param[in] src_offset offset of the source image in the @a src_bo * @param[in] src_mesaformat source image format * @param[in] src_pitch aligned source image width * @param[in] src_width source image width * @param[in] src_height source image height * @param[in] src_x_offset x offset in the source image * @param[in] src_y_offset y offset in the source image * @param[in] dst_bo destination radeon buffer object * @param[in] dst_offset offset of the destination image in the @a dst_bo * @param[in] dst_mesaformat destination image format * @param[in] dst_pitch aligned destination image width * @param[in] dst_width destination image width * @param[in] dst_height destination image height * @param[in] dst_x_offset x offset in the destination image * @param[in] dst_y_offset y offset in the destination image * @param[in] width region width * @param[in] height region height * @param[in] flip_y set if y coords of the source image need to be flipped */ unsigned r200_blit(GLcontext *ctx, struct radeon_bo *src_bo, intptr_t src_offset, gl_format src_mesaformat, unsigned src_pitch, unsigned src_width, unsigned src_height, unsigned src_x_offset, unsigned src_y_offset, struct radeon_bo *dst_bo, intptr_t dst_offset, gl_format dst_mesaformat, unsigned dst_pitch, unsigned dst_width, unsigned dst_height, unsigned dst_x_offset, unsigned dst_y_offset, unsigned reg_width, unsigned reg_height, unsigned flip_y) { struct r200_context *r200 = R200_CONTEXT(ctx); if (!r200_check_blit(dst_mesaformat)) return GL_FALSE; /* Make sure that colorbuffer has even width - hw limitation */ if (dst_pitch % 2 > 0) ++dst_pitch; /* Rendering to small buffer doesn't work. * Looks like a hw limitation. */ if (dst_pitch < 32) return GL_FALSE; /* Need to clamp the region size to make sure * we don't read outside of the source buffer * or write outside of the destination buffer. */ if (reg_width + src_x_offset > src_width) reg_width = src_width - src_x_offset; if (reg_height + src_y_offset > src_height) reg_height = src_height - src_y_offset; if (reg_width + dst_x_offset > dst_width) reg_width = dst_width - dst_x_offset; if (reg_height + dst_y_offset > dst_height) reg_height = dst_height - dst_y_offset; if (src_bo == dst_bo) { return GL_FALSE; } if (src_offset % 32 || dst_offset % 32) { return GL_FALSE; } if (0) { fprintf(stderr, "src: size [%d x %d], pitch %d, " "offset [%d x %d], format %s, bo %p\n", src_width, src_height, src_pitch, src_x_offset, src_y_offset, _mesa_get_format_name(src_mesaformat), src_bo); fprintf(stderr, "dst: pitch %d, offset[%d x %d], format %s, bo %p\n", dst_pitch, dst_x_offset, dst_y_offset, _mesa_get_format_name(dst_mesaformat), dst_bo); fprintf(stderr, "region: %d x %d\n", reg_width, reg_height); } /* Flush is needed to make sure that source buffer has correct data */ radeonFlush(r200->radeon.glCtx); rcommonEnsureCmdBufSpace(&r200->radeon, 78, __FUNCTION__); if (!validate_buffers(r200, src_bo, dst_bo)) return GL_FALSE; /* 14 */ emit_vtx_state(r200); /* 28 */ emit_tx_setup(r200, src_mesaformat, src_bo, src_offset, src_width, src_height, src_pitch); /* 22 */ emit_cb_setup(r200, dst_bo, dst_offset, dst_mesaformat, dst_pitch, dst_width, dst_height); /* 14 */ emit_draw_packet(r200, src_width, src_height, src_x_offset, src_y_offset, dst_x_offset, dst_y_offset, reg_width, reg_height, flip_y); radeonFlush(ctx); return GL_TRUE; }
/* ================================================================ * Buffer clear */ static void r200Clear( struct gl_context *ctx, GLbitfield mask ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); __DRIdrawable *dPriv = radeon_get_drawable(&rmesa->radeon); GLuint flags = 0; GLuint orig_mask = mask; if ( R200_DEBUG & RADEON_IOCTL ) { if (rmesa->radeon.sarea) fprintf( stderr, "r200Clear %x %d\n", mask, rmesa->radeon.sarea->pfCurrentPage); else fprintf( stderr, "r200Clear %x radeon->sarea is NULL\n", mask); } { LOCK_HARDWARE( &rmesa->radeon ); UNLOCK_HARDWARE( &rmesa->radeon ); if ( dPriv->numClipRects == 0 ) return; } radeonFlush( ctx ); if ( mask & BUFFER_BIT_FRONT_LEFT ) { flags |= RADEON_FRONT; mask &= ~BUFFER_BIT_FRONT_LEFT; } if ( mask & BUFFER_BIT_BACK_LEFT ) { flags |= RADEON_BACK; mask &= ~BUFFER_BIT_BACK_LEFT; } if ( mask & BUFFER_BIT_DEPTH ) { flags |= RADEON_DEPTH; mask &= ~BUFFER_BIT_DEPTH; } if ( (mask & BUFFER_BIT_STENCIL) ) { flags |= RADEON_STENCIL; mask &= ~BUFFER_BIT_STENCIL; } if ( mask ) { if (R200_DEBUG & RADEON_FALLBACKS) fprintf(stderr, "%s: swrast clear, mask: %x\n", __FUNCTION__, mask); _swrast_Clear( ctx, mask ); } if ( !flags ) return; if (rmesa->using_hyperz) { flags |= RADEON_USE_COMP_ZBUF; /* if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) flags |= RADEON_USE_HIERZ; */ if (!((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) && ((rmesa->radeon.state.stencil.clear & R200_STENCIL_WRITE_MASK) == R200_STENCIL_WRITE_MASK))) { flags |= RADEON_CLEAR_FASTZ; } } if (rmesa->radeon.radeonScreen->kernel_mm) radeonUserClear(ctx, orig_mask); else { r200KernelClear(ctx, flags); rmesa->radeon.hw.all_dirty = GL_TRUE; } }