void radio_reset() {
volatile uint16_t delay;
cc2420_MDMCTRL0_reg_t cc2420_MDMCTRL0_reg;
cc2420_TXCTRL_reg_t cc2420_TXCTRL_reg;
cc2420_RXCTRL1_reg_t cc2420_RXCTRL1_reg;
// set radio VREG pin high
PORT_PIN_RADIO_VREG_HIGH();
for (delay=0xffff;delay>0;delay--); // max. VREG start-up time is 0.6ms
// set radio RESET pin low
PORT_PIN_RADIO_RESET_LOW();
for (delay=0xffff;delay>0;delay--);
// set radio RESET pin high
PORT_PIN_RADIO_RESET_HIGH();
for (delay=0xffff;delay>0;delay--);
// disable address recognition
cc2420_MDMCTRL0_reg.PREAMBLE_LENGTH = 2; // 3 leading zero's (IEEE802.15.4 compliant)
cc2420_MDMCTRL0_reg.AUTOACK = 0;
cc2420_MDMCTRL0_reg.AUTOCRC = 1;
cc2420_MDMCTRL0_reg.CCA_MODE = 3;
cc2420_MDMCTRL0_reg.CCA_HYST = 2;
cc2420_MDMCTRL0_reg.ADR_DECODE = 0; // turn OFF address recognition
cc2420_MDMCTRL0_reg.PAN_COORDINATOR = 0;
cc2420_MDMCTRL0_reg.RESERVED_FRAME_MODE = 1; // accept all frame types
cc2420_MDMCTRL0_reg.reserved_w0 = 0;
radio_spiWriteReg(CC2420_MDMCTRL0_ADDR,
&radio_vars.radioStatusByte,
*(uint16_t*)&cc2420_MDMCTRL0_reg);
// speed up time to TX
cc2420_TXCTRL_reg.PA_LEVEL = 31;// max. TX power (~0dBm)
cc2420_TXCTRL_reg.reserved_w1 = 1;
cc2420_TXCTRL_reg.PA_CURRENT = 3;
cc2420_TXCTRL_reg.TXMIX_CURRENT = 0;
cc2420_TXCTRL_reg.TXMIX_CAP_ARRAY = 0;
cc2420_TXCTRL_reg.TX_TURNAROUND = 0; // faster STXON->SFD timing (128us)
cc2420_TXCTRL_reg.TXMIXBUF_CUR = 2;
radio_spiWriteReg(CC2420_TXCTRL_ADDR,
&radio_vars.radioStatusByte,
*(uint16_t*)&cc2420_TXCTRL_reg);
// apply correction recommended in datasheet
cc2420_RXCTRL1_reg.RXMIX_CURRENT = 2;
cc2420_RXCTRL1_reg.RXMIX_VCM = 1;
cc2420_RXCTRL1_reg.RXMIX_TAIL = 1;
cc2420_RXCTRL1_reg.LNA_CAP_ARRAY = 1;
cc2420_RXCTRL1_reg.MED_HGM = 0;
cc2420_RXCTRL1_reg.HIGH_HGM = 1;
cc2420_RXCTRL1_reg.MED_LOWGAIN = 0;
cc2420_RXCTRL1_reg.LOW_LOWGAIN = 1;
cc2420_RXCTRL1_reg.RXBPF_MIDCUR = 0;
cc2420_RXCTRL1_reg.RXBPF_LOCUR = 1; // use this setting as per datasheet
cc2420_RXCTRL1_reg.reserved_w0 = 0;
radio_spiWriteReg(CC2420_RXCTRL1_ADDR,
&radio_vars.radioStatusByte,
*(uint16_t*)&cc2420_RXCTRL1_reg);
}
void radio_setFrequency(uint8_t frequency) {
// change state
radio_vars.state = RADIOSTATE_SETTING_FREQUENCY;
// configure the radio to the right frequecy
radio_spiWriteReg(RG_PHY_CC_CCA,0x20+frequency);
// change state
radio_vars.state = RADIOSTATE_FREQUENCY_SET;
}
void radio_setFrequency(uint8_t frequency) {
cc1101_FREQ0_reg_t cc1101_FREQ0_reg;
cc1101_FREQ1_reg_t cc1101_FREQ1_reg;
cc1101_FREQ2_reg_t cc1101_FREQ2_reg;
// change state
radio_vars.state = RADIOSTATE_SETTING_FREQUENCY;
// setting least significant bits
cc1101_FREQ0_reg.FREQ = frequency;
radio_spiWriteReg(CC1101_FREQ0,
&radio_vars.radioStatusByte,
*(uint8_t*)&cc1101_FREQ0_reg);
cc1101_FREQ1_reg.FREQ = 0;
radio_spiWriteReg(CC1101_FREQ1,
&radio_vars.radioStatusByte,
*(uint8_t*)&cc1101_FREQ1_reg);
cc1101_FREQ2_reg.FREQ_1 = 0; // always 0
cc1101_FREQ2_reg.FREQ_2 = 0;
radio_spiWriteReg(CC1101_FREQ2,
&radio_vars.radioStatusByte,
*(uint8_t*)&cc1101_FREQ2_reg);
// change state
radio_vars.state = RADIOSTATE_FREQUENCY_SET;
}
void radio_init() {
// clear variables
memset(&radio_vars,0,sizeof(radio_vars_t));
// change state
radio_vars.state = RADIOSTATE_STOPPED;
// configure the radio
radio_spiWriteReg(RG_TRX_STATE, CMD_FORCE_TRX_OFF); // turn radio off
radio_spiWriteReg(RG_IRQ_MASK,
(AT_IRQ_RX_START| AT_IRQ_TRX_END)); // tell radio to fire interrupt on TRX_END and RX_START
radio_spiReadReg(RG_IRQ_STATUS); // deassert the interrupt pin in case is high
radio_spiWriteReg(RG_ANT_DIV, RADIO_CHIP_ANTENNA); // use chip antenna
#define RG_TRX_CTRL_1 0x04
radio_spiWriteReg(RG_TRX_CTRL_1, 0x20); // have the radio calculate CRC
//busy wait until radio status is TRX_OFF
while((radio_spiReadReg(RG_TRX_STATUS) & 0x1F) != TRX_OFF);
// change state
radio_vars.state = RADIOSTATE_RFOFF;
}
void radio_txEnable() {
// change state
radio_vars.state = RADIOSTATE_ENABLING_TX;
// wiggle debug pin
debugpins_radio_set();
leds_radio_on();
// turn on radio's PLL
radio_spiWriteReg(RG_TRX_STATE, CMD_PLL_ON);
while((radio_spiReadReg(RG_TRX_STATUS) & 0x1F) != PLL_ON); // busy wait until done
// change state
radio_vars.state = RADIOSTATE_TX_ENABLED;
}
void radio_rfOff() {
// change state
radio_vars.state = RADIOSTATE_TURNING_OFF;
radio_spiReadReg(RG_TRX_STATUS);
// turn radio off
radio_spiWriteReg(RG_TRX_STATE, CMD_FORCE_TRX_OFF);
//radio_spiWriteReg(RG_TRX_STATE, CMD_TRX_OFF);
while((radio_spiReadReg(RG_TRX_STATUS) & 0x1F) != TRX_OFF); // busy wait until done
// wiggle debug pin
debugpins_radio_clr();
leds_radio_off();
// change state
radio_vars.state = RADIOSTATE_RFOFF;
}
void radio_rxEnable() {
// change state
radio_vars.state = RADIOSTATE_ENABLING_RX;
// put radio in reception mode
radio_spiWriteReg(RG_TRX_STATE, CMD_RX_ON);
// wiggle debug pin
debugpins_radio_set();
leds_radio_on();
// busy wait until radio really listening
while((radio_spiReadReg(RG_TRX_STATUS) & 0x1F) != RX_ON);
// change state
radio_vars.state = RADIOSTATE_LISTENING;
}
void radio_setFrequency(uint8_t frequency) {
cc2420_FSCTRL_reg_t cc2420_FSCTRL_reg;
// change state
radio_vars.state = RADIOSTATE_SETTING_FREQUENCY;
cc2420_FSCTRL_reg.FREQ = frequency-11;
cc2420_FSCTRL_reg.FREQ *= 5;
cc2420_FSCTRL_reg.FREQ += 357;
cc2420_FSCTRL_reg.LOCK_STATUS = 0;
cc2420_FSCTRL_reg.LOCK_LENGTH = 0;
cc2420_FSCTRL_reg.CAL_RUNNING = 0;
cc2420_FSCTRL_reg.CAL_DONE = 0;
cc2420_FSCTRL_reg.LOCK_THR = 1;
radio_spiWriteReg(CC2420_FSCTRL_ADDR,
&radio_vars.radioStatusByte,
*(uint16_t*)&cc2420_FSCTRL_reg);
// change state
radio_vars.state = RADIOSTATE_FREQUENCY_SET;
}
void radio_reset() {
cc1101_IOCFG0_reg_t cc1101_IOCFG0_reg;
cc1101_PKTCTRL0_reg_t cc1101_PKTCTRL0_reg;
cc1101_PKTLEN_reg_t cc1101_PKTLEN_reg;
cc1101_MDMCFG2_reg_t cc1101_MDMCFG2_reg;
cc1101_MCSM0_reg_t cc1101_MCSM0_reg;
// global reset
radio_spiStrobe(CC1101_SRES, &radio_vars.radioStatusByte);
// default setting as recommended in datasheet
cc1101_IOCFG0_reg.GDO0_CFG = 63;
cc1101_IOCFG0_reg.GDO0_INV = 0;
cc1101_IOCFG0_reg.TEMP_SENSOR_ENABLE = 0;
radio_spiWriteReg(CC1101_IOCFG0,
&radio_vars.radioStatusByte,
*(uint8_t*)&cc1101_IOCFG0_reg);
// setting packet control
cc1101_PKTCTRL0_reg.LENGTH_CONFIG = 0; // Fixing packet length
cc1101_PKTCTRL0_reg.CRC_EN = 1; // Enabling CRC calculation
cc1101_PKTCTRL0_reg.unused_r0_2 = 0;
cc1101_PKTCTRL0_reg.PKT_FORMAT = 0;
cc1101_PKTCTRL0_reg.WHITE_DATA = 1; // Data whitening
radio_spiWriteReg(CC1101_PKTCTRL0,
&radio_vars.radioStatusByte,
*(uint8_t*)&cc1101_PKTCTRL0_reg);
// Setting packet length to 128 bytes
cc1101_PKTLEN_reg.PACKET_LENGTH = 128;
radio_spiWriteReg(CC1101_PKTLEN,
&radio_vars.radioStatusByte,
*(uint8_t*)&cc1101_PKTLEN_reg);
//Emulating 32 bits word as recommended in datasheet
cc1101_MDMCFG2_reg.SYNC_MODE = 3; // 32 bits sync word
cc1101_MDMCFG2_reg.MANCHESTER_EN = 0;
cc1101_MDMCFG2_reg.MOD_FORMAT = 0;
cc1101_MDMCFG2_reg.DEM_DCFILT_OFF = 0;
radio_spiWriteReg(CC1101_MDMCFG2,
&radio_vars.radioStatusByte,
*(uint8_t*)&cc1101_MDMCFG2_reg);
// setting main control state machine
cc1101_MCSM0_reg.FS_AUTOCAL = 0;
cc1101_MCSM0_reg.PO_TIMEOUT = 1;
cc1101_MCSM0_reg.PIN_CTRL_EN = 0;
cc1101_MCSM0_reg.XOSC_FORCE_ON = 1; // Forcing the XOSC to stay on even in SLEEP state
radio_spiWriteReg(CC1101_MCSM0,
&radio_vars.radioStatusByte,
*(uint8_t*)&cc1101_MCSM0_reg);
}
