void OBC1::write(unsigned addr, uint8 data) {
addr &= 0x1fff;
switch(addr) {
case 0x1ff0: ram_write(status.baseptr + (status.address << 2) + 0, data); return;
case 0x1ff1: ram_write(status.baseptr + (status.address << 2) + 1, data); return;
case 0x1ff2: ram_write(status.baseptr + (status.address << 2) + 2, data); return;
case 0x1ff3: ram_write(status.baseptr + (status.address << 2) + 3, data); return;
case 0x1ff4: {
uint8 temp = ram_read(status.baseptr + (status.address >> 2) + 0x200);
temp = (temp & ~(3 << status.shift)) | ((data & 3) << status.shift);
ram_write(status.baseptr + (status.address >> 2) + 0x200, temp);
} return;
case 0x1ff5:
status.baseptr = (data & 1) ? 0x1800 : 0x1c00;
ram_write(addr, data);
return;
case 0x1ff6:
status.address = (data & 0x7f);
status.shift = (data & 3) << 1;
ram_write(addr, data);
return;
case 0x1ff7:
ram_write(addr, data);
return;
}
return ram_write(addr, data);
}
static ssize_t ram_bwrite(FAR struct mtd_dev_s *dev, off_t startblock,
size_t nblocks, FAR const uint8_t *buf)
{
FAR struct ram_dev_s *priv = (FAR struct ram_dev_s *)dev;
off_t offset;
off_t maxblock;
size_t nbytes;
DEBUGASSERT(dev && buf);
/* Don't let the write exceed the size of the ram buffer */
maxblock = priv->nblocks * CONFIG_RAMMTD_BLKPER;
if (startblock >= maxblock)
{
return 0;
}
if (startblock + nblocks > maxblock)
{
nblocks = maxblock - startblock;
}
/* Get the offset corresponding to the first block and the size
* corresponding to the number of blocks.
*/
offset = startblock * CONFIG_RAMMTD_BLOCKSIZE;
nbytes = nblocks * CONFIG_RAMMTD_BLOCKSIZE;
/* Then write the data to RAM */
ram_write(&priv->start[offset], buf, nbytes);
return nblocks;
}
int main(void) {
unsigned short addr1 = 0x1234; // the address for writing the ram
char data[] = "Help, I'm stuck in the RAM!"; // the test message
char read[] = "***************************"; // buffer for reading from ram
char buf[100]; // buffer for comm. with the user
unsigned char status; // used to verify we set the status
NU32_Startup(); // cache on, interrupts on, LED/button init, UART init
ram_init();
// check the ram status
CS = 0;
spi_io(0x5); // ram read status command
status = spi_io(0); // the actual status
CS = 1;
sprintf(buf, "Status 0x%x\r\n",status);
NU32_WriteUART3(buf);
sprintf(buf,"Writing \"%s\" to ram at address 0x%x\r\n", data, addr1);
NU32_WriteUART3(buf);
// write the data to the ram
ram_write(addr1, data, strlen(data) + 1); // +1, to send the '\0' character
ram_read(addr1, read, strlen(data) + 1); // read the data back
sprintf(buf,"Read \"%s\" from ram at address 0x%x\r\n", read, addr1);
NU32_WriteUART3(buf);
while(1) {
;
}
return 0;
}
alwaysinline void sSMP::op_buswrite(uint16 addr, uint8 data) {
if((addr & 0xfff0) == 0x00f0) {
//addr >= 0x00f0 && addr >= 0x00ff
if(status.mmio_disabled == true) return;
switch(addr) {
case 0xf0: { //TEST
if(regs.p.p) break; //writes only valid when P flag is clear
//multiplier table may not be 100% accurate, some settings crash
//the processor due to S-SMP <> S-DSP bus access misalignment
//static uint8 clock_speed_tbl[16] =
//{ 3, 5, 9, 17, 4, 6, 10, 18, 6, 8, 12, 20, 10, 12, 16, 24 };
//status.clock_speed = 24 * clock_speed_tbl[data >> 4] / 3;
status.mmio_disabled = !!(data & 0x04);
status.ram_writable = !!(data & 0x02);
//if((data >> 4) != 0) {
//dprintf("* S-SMP critical warning: $00f0 (TEST) clock speed control modified!");
//dprintf("* S-SMP may crash on hardware as a result!");
//}
} break;
case 0xf1: { //CONTROL
status.iplrom_enabled = !!(data & 0x80);
if(data & 0x30) {
//one-time clearing of APU port read registers,
//emulated by simulating CPU writes of 0x00
scheduler.sync_smpcpu();
if(data & 0x20) {
cpu.port_write(2, 0x00);
cpu.port_write(3, 0x00);
}
if(data & 0x10) {
cpu.port_write(0, 0x00);
cpu.port_write(1, 0x00);
}
}
//0->1 transistion resets timers
if(t2.enabled == false && (data & 0x04)) {
t2.stage2_ticks = 0;
t2.stage3_ticks = 0;
}
t2.enabled = !!(data & 0x04);
if(t1.enabled == false && (data & 0x02)) {
t1.stage2_ticks = 0;
t1.stage3_ticks = 0;
}
t1.enabled = !!(data & 0x02);
if(t0.enabled == false && (data & 0x01)) {
t0.stage2_ticks = 0;
t0.stage3_ticks = 0;
}
t0.enabled = !!(data & 0x01);
} break;
case 0xf2: { //DSPADDR
status.dsp_addr = data;
} break;
case 0xf3: { //DSPDATA
//0x80-0xff is a read-only mirror of 0x00-0x7f
if(!(status.dsp_addr & 0x80)) {
dsp.write(status.dsp_addr & 0x7f, data);
}
} break;
case 0xf4: //CPUIO0
case 0xf5: //CPUIO1
case 0xf6: //CPUIO2
case 0xf7: { //CPUIO3
scheduler.sync_smpcpu();
port_write(addr & 3, data);
} break;
case 0xf8: { //???
status.smp_f8 = data;
} break;
case 0xf9: { //???
status.smp_f9 = data;
} break;
case 0xfa: { //T0TARGET
t0.target = data;
} break;
case 0xfb: { //T1TARGET
t1.target = data;
} break;
case 0xfc: { //T2TARGET
t2.target = data;
} break;
case 0xfd: //T0OUT
case 0xfe: //T1OUT
case 0xff: { //T2OUT -- read-only registers
} break;
}
}
//all writes, even to MMIO registers, appear on bus
if(status.ram_writable == true) {
ram_write(addr, data);
}
}
int SPI_DOWNLOAD_THREAD::fx3_usbboot_download(const char *filename)
{
unsigned char *fwBuf;
unsigned int *data_p;
unsigned int i, checksum;
unsigned int address, length;
int r, index;
fwBuf = (unsigned char *)calloc (1, MAX_FWIMG_SIZE);
if ( fwBuf == 0 ) {
printf("Failed to allocate buffer to store firmware binary\n");
sb->showMessage("Error: Failed to get memory for download\n", 5000);
return -1;
}
// Read the firmware image into the local RAM buffer.
r = read_firmware_image(filename, fwBuf, NULL);
if ( r != 0 ) {
printf("Failed to read firmware file %s\n", filename);
sb->showMessage("Error: Failed to read firmware binary\n", 5000);
free(fwBuf);
return -2;
}
// Run through each section of code, and use vendor commands to download them to RAM.
index = 4;
checksum = 0;
while ( index < filesize ) {
data_p = (unsigned int *)(fwBuf + index);
length = data_p[0];
address = data_p[1];
if (length != 0) {
for (i = 0; i < length; i++)
checksum += data_p[2 + i];
r = ram_write(fwBuf + index + 8, address, length * 4);
if (r != 0) {
printf("Failed to download data to FX3 RAM\n");
sb->showMessage("Error: Write to FX3 RAM failed", 5000);
free(fwBuf);
return -3;
}
} else {
if (checksum != data_p[2]) {
printf ("Checksum error in firmware binary\n");
sb->showMessage("Error: Firmware checksum error", 5000);
free(fwBuf);
return -4;
}
r = cyusb_control_transfer(h, 0x40, 0xA0, GET_LSW(address), GET_MSW(address), NULL,
0, VENDORCMD_TIMEOUT);
if ( r != 0 )
printf("Ignored error in control transfer: %d\n", r);
break;
}
index += (8 + length * 4);
}
free(fwBuf);
return 0;
}
void SMP::op_buswrite(uint16 addr, uint8 data) {
switch(addr) {
case 0xf0: //TEST
if(regs.p.p) break; //writes only valid when P flag is clear
status.clock_speed = (data >> 6) & 3;
status.timer_speed = (data >> 4) & 3;
status.timers_enable = data & 0x08;
status.ram_disable = data & 0x04;
status.ram_writable = data & 0x02;
status.timers_disable = data & 0x01;
status.timer_step = (1 << status.clock_speed) + (2 << status.timer_speed);
timer0.synchronize_stage1();
timer1.synchronize_stage1();
timer2.synchronize_stage1();
break;
case 0xf1: //CONTROL
status.iplrom_enable = data & 0x80;
if(data & 0x30) {
//one-time clearing of APU port read registers,
//emulated by simulating CPU writes of 0x00
synchronize_cpu_force();
if(data & 0x20) {
cpu.port_write(2, 0x00);
cpu.port_write(3, 0x00);
}
if(data & 0x10) {
cpu.port_write(0, 0x00);
cpu.port_write(1, 0x00);
}
}
//0->1 transistion resets timers
if(timer2.enable == false && (data & 0x04)) {
timer2.stage2_ticks = 0;
timer2.stage3_ticks = 0;
}
timer2.enable = data & 0x04;
if(timer1.enable == false && (data & 0x02)) {
timer1.stage2_ticks = 0;
timer1.stage3_ticks = 0;
}
timer1.enable = data & 0x02;
if(timer0.enable == false && (data & 0x01)) {
timer0.stage2_ticks = 0;
timer0.stage3_ticks = 0;
}
timer0.enable = data & 0x01;
break;
case 0xf2: //DSPADDR
status.dsp_addr = data;
break;
case 0xf3: //DSPDATA
if(status.dsp_addr & 0x80) break; //0x80-0xff are read-only mirrors of 0x00-0x7f
dsp.write(status.dsp_addr & 0x7f, data);
break;
case 0xf4: //CPUIO0
case 0xf5: //CPUIO1
case 0xf6: //CPUIO2
case 0xf7: //CPUIO3
synchronize_cpu_force();
port_write(addr, data);
break;
case 0xf8: //RAM0
status.ram00f8 = data;
break;
case 0xf9: //RAM1
status.ram00f9 = data;
break;
case 0xfa: //T0TARGET
timer0.target = data;
break;
case 0xfb: //T1TARGET
timer1.target = data;
break;
case 0xfc: //T2TARGET
timer2.target = data;
break;
case 0xfd: //T0OUT
case 0xfe: //T1OUT
case 0xff: //T2OUT -- read-only registers
break;
}
ram_write(addr, data); //all writes, even to MMIO registers, appear on bus
}
alwaysinline void SMP::op_buswrite(uint16 addr, uint8 data) {
if((addr & 0xfff0) == 0x00f0) { //$00f0-00ff
switch(addr) {
case 0xf0: { //TEST
if(regs.p.p) break; //writes only valid when P flag is clear
status.clock_speed = (data >> 6) & 3;
status.timer_speed = (data >> 4) & 3;
status.timers_enabled = data & 0x08;
status.ram_disabled = data & 0x04;
status.ram_writable = data & 0x02;
status.timers_disabled = data & 0x01;
status.timer_step = (1 << status.clock_speed) + (2 << status.timer_speed);
t0.sync_stage1();
t1.sync_stage1();
t2.sync_stage1();
} break;
case 0xf1: { //CONTROL
status.iplrom_enabled = data & 0x80;
if(data & 0x30) {
//one-time clearing of APU port read registers
synchronize_cpu();
if(data & 0x20) {
port.cpu_to_smp[2] = 0;
port.cpu_to_smp[3] = 0;
}
if(data & 0x10) {
port.cpu_to_smp[0] = 0;
port.cpu_to_smp[1] = 0;
}
}
//0->1 transistion resets timers
if(t2.enabled == false && (data & 0x04)) {
t2.stage2_ticks = 0;
t2.stage3_ticks = 0;
}
t2.enabled = data & 0x04;
if(t1.enabled == false && (data & 0x02)) {
t1.stage2_ticks = 0;
t1.stage3_ticks = 0;
}
t1.enabled = data & 0x02;
if(t0.enabled == false && (data & 0x01)) {
t0.stage2_ticks = 0;
t0.stage3_ticks = 0;
}
t0.enabled = data & 0x01;
} break;
case 0xf2: { //DSPADDR
status.dsp_addr = data;
} break;
case 0xf3: { //DSPDATA
//0x80-0xff are read-only mirrors of 0x00-0x7f
if(!(status.dsp_addr & 0x80)) {
dsp.write(status.dsp_addr & 0x7f, data);
}
if (dump_spc && status.dsp_addr == 0x4c /* r_kon */ && data) {
save_spc_dump();
}
} break;
case 0xf4: //CPUIO0
case 0xf5: //CPUIO1
case 0xf6: //CPUIO2
case 0xf7: { //CPUIO3
synchronize_cpu();
port.smp_to_cpu[addr & 3] = data;
} break;
case 0xf8: //PORT4
case 0xf9: { //PORT5
port.aux[addr & 1] = data;
} break;
case 0xfa: { //T0TARGET
t0.target = data;
} break;
case 0xfb: { //T1TARGET
t1.target = data;
} break;
case 0xfc: { //T2TARGET
t2.target = data;
} break;
case 0xfd: //T0OUT
case 0xfe: //T1OUT
case 0xff: { //T2OUT -- read-only registers
} break;
}
}
//all writes, even to MMIO registers, appear on bus
ram_write(addr, data);
}
