/****************************************************************************
REMARKS:
Enables the Cyrix CPUID instruction to properly detect MediaGX and 6x86
processors.
****************************************************************************/
static void _CPU_enableCyrixCPUID(void)
{
uchar ccr3;
PM_init();
ccr3 = rdinx(0x22,0xC3);
wrinx(0x22,0xC3,(uchar)(ccr3 | 0x10));
wrinx(0x22,0xE8,(uchar)(rdinx(0x22,0xE8) | 0x80));
wrinx(0x22,0xC3,ccr3);
}
static void
PVGA1lcd24power(int PowerManagementMode)
{
static unsigned char lcd_off = 0;
unsigned char lock_val, reg_val, seq1, sync2;
int crt_on; /* allow sync to turn off? */
if (!xf86VTSema) return;
/* Turn LCD on or off and blank/unblank screen */
switch (PowerManagementMode)
{
case DPMSModeOn:
/* Turn LCD on */
if (lcd_off) {
/* this is a wd90c24 LCD which we have turned off */
lcd_off = 0; /* Don't allow nested calls */
/* Unlock extended PR registers */
wrinx(0x3C4, 0x06, 0x48);
reg_val = rdinx(0x3C4, 0x19); /* PR57 */
/* PNLOFF low */
wrinx(0x3C4, 0x19, reg_val | 0x04); /* set bit 2 */
usleep(100000);
lock_val = rdinx(0x3CE, 0x0F);
/* Unlock PR0-PR4 */
wrinx(0x3CE, 0x0F, (0xF8 & lock_val) | 0x05);
reg_val = rdinx(0x3CE, 0x0E); /* PR4 */
/* Drive FP interface pins active */
wrinx(0x3CE, 0x0E, 0xDF & reg_val); /* clear bit 5 */
wrinx(0x3CE, 0x0F, lock_val); /* restore lock */
usleep(100000);
lock_val = rdinx(vgaIOBase+0x04, 0x34);
/* Unlock FP Reg */
wrinx(vgaIOBase+0x04, 0x34, (0x0F & lock_val) | 0xA0);
reg_val = rdinx(vgaIOBase+0x04, 0x032);
/* Turn on LCD */
wrinx(vgaIOBase+0x04, 0x32, 0x10 | reg_val); /* set PR19, bit 4 */
wrinx(vgaIOBase+0x04, 0x34, lock_val); /* restore locks*/
}
/* Unblank Screen */
outw(0x3C4, 0x0100); /* Synchronous Reset */
outb(0x3C4, 0x01); /* Select SEQ1 */
seq1 = inb(0x3C5) & ~0x20;
outb(0x3C5, seq1);
outw(0x3C4, 0x0300); /* End Reset */
usleep(10000);
break;
case DPMSModeStandby:
case DPMSModeSuspend:
case DPMSModeOff:
/* Turn LCD off */
lock_val = rdinx(vgaIOBase+0x04, 0x34);
/* Unlock FP Reg */
wrinx(vgaIOBase+0x04, 0x34, (0x0F & lock_val) | 0xA0);
reg_val = rdinx(vgaIOBase+0x04, 0x032); /* PR19 */
crt_on = ((reg_val & 0x20) == 0x20); /* CRT on? */
if (reg_val & 0x10) {
/* this is a wd90c24 with LCD on */
lcd_off ++;
/* Turn off LCD */
wrinx(vgaIOBase+0x04, 0x32, 0xEF & reg_val); /* clear PR19, bit 4 */
wrinx(vgaIOBase+0x04, 0x34, lock_val); /* restore locks*/
lock_val = rdinx(0x3CE, 0x0F);
/* Unlock PR0-PR4 */
wrinx(0x3CE, 0x0F, (0xF8 & lock_val) | 0x05);
reg_val = rdinx(0x3CE, 0x0E); /* PR4 */
/* Tri-state FP interfacee pins */
wrinx(0x3CE, 0x0E, reg_val | 0x20); /* set bit 5 */
wrinx(0x3CE, 0x0F, lock_val); /* restore lock */
lock_val = rdinx(0x3C4, 0x06);
/* Unlock extended PR registers */
wrinx(0x3C4, 0x06, 0x48);
reg_val = rdinx(0x3C4, 0x19); /* PR57 */
/* PNLOFF high */
wrinx(0x3C4, 0x19, 0xFB & reg_val); /* clear bit 2 */
}
else {
wrinx(vgaIOBase+0x04, 0x34, lock_val); /* restore locks*/
}
/* Blank screen */
if (crt_on) { /* blank only if monitor in use */
outw(0x3C4, 0x0100); /* Synchronous Reset */
outb(0x3C4, 0x01); /* Select SEQ1 */
seq1 = inb(0x3C5) | 0x20;
outb(0x3C5, seq1);
outw(0x3C4, 0x0300); /* End Reset */
usleep(10000);
}
break;
}
/* Manipulate HSync and VSync */
switch (PowerManagementMode)
{
case DPMSModeOn:
/* Screen: On; HSync: On, VSync: On */
outb(vgaIOBase + 4, 0x17);
sync2 = inb(vgaIOBase + 5);
sync2 |= 0x80; /* enable sync */
usleep(10000);
outb(vgaIOBase + 5, sync2);
break;
case DPMSModeStandby:
/* Screen: Off; HSync: Off, VSync: On */
/* This may be supported later */
break;
case DPMSModeSuspend:
/* Screen: Off; HSync: On, VSync: Off */
/* This may be supported later */
break;
case DPMSModeOff:
/* Screen: Off; HSync: Off, VSync: Off */
if (crt_on) { /* disable sync only if monitor in use */
outb(vgaIOBase + 4, 0x17);
sync2 = inb(vgaIOBase + 5);
sync2 &= ~0x80; /* disable sync */
usleep(10000);
outb(vgaIOBase + 5, sync2);
}
break;
}
}
